Sparc-Size-Translations - Using as
Description: Using as

Previous: Sparc-Relocs, Up: Sparc-Syntax

##### 9.36.3.5 Size Translations

Often it is desirable to write code in an operand size agnostic manner. `as` provides support for this via operand size opcode translations. Translations are supported for loads, stores, shifts, compare-and-swap atomics, and the ‘`clr`’ synthetic instruction.

If generating 32-bit code, `as` will generate the 32-bit opcode. Whereas if 64-bit code is being generated, the 64-bit opcode will be emitted. For example `ldn` will be transformed into `ld` for 32-bit code and `ldx` for 64-bit code.

Here is an example meant to demonstrate all the supported opcode translations:

         ldn   [%o0], %o1
         ldna  [%o0] %asi, %o2
         stn   %o1, [%o0]
         stna  %o2, [%o0] %asi
         slln  %o3, 3, %o3
         srln  %o4, 8, %o4
         sran  %o5, 12, %o5
         casn  [%o0], %o1, %o2
         casna [%o0] %asi, %o1, %o2
         clrn  %g1

In 32-bit mode `as` will emit:

         ld   [%o0], %o1
         lda  [%o0] %asi, %o2
         st   %o1, [%o0]
         sta  %o2, [%o0] %asi
         sll  %o3, 3, %o3
         srl  %o4, 8, %o4
         sra  %o5, 12, %o5
         cas  [%o0], %o1, %o2
         casa [%o0] %asi, %o1, %o2
         clr  %g1

And in 64-bit mode `as` will emit:

         ldx   [%o0], %o1
         ldxa  [%o0] %asi, %o2
         stx   %o1, [%o0]
         stxa  %o2, [%o0] %asi
         sllx  %o3, 3, %o3
         srlx  %o4, 8, %o4
         srax  %o5, 12, %o5
         casx  [%o0], %o1, %o2
         casxa [%o0] %asi, %o1, %o2
         clrx  %g1

Finally, the ‘`.nword`’ translating directive is supported as well. It is documented in the section on Sparc machine directives.