/* Generated automatically by the program `genconstants'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CONSTANTS_H
#define GCC_INSN_CONSTANTS_H

#define UNSPECV_SEI 5
#define UNSPECV_WRITE_SP_IRQ_ON 2
#define UNSPECV_PROLOGUE_SAVES 0
#define UNSPEC_FMULSU 5
#define UNSPEC_STRLEN 0
#define UNSPECV_DELAY_CYCLES_2_TINY 105
#define UNSPECV_CLI 6
#define UNSPECV_NOP2 8
#define ZERO_REGNO 1
#define TMP_REGNO 0
#define ZERO_REGNO_AVRTINY10 17
#define UNSPECV_WDR 10
#define UNSPECV_SLEEP 9
#define UNSPECV_EPILOGUE_RESTORES 1
#define REG_W 24
#define REG_X 26
#define REG_Y 28
#define REG_Z 30
#define UNSPECV_NOP 7
#define UNSPECV_DELAY_CYCLES_3 103
#define UNSPEC_FMULS 4
#define UNSPEC_INDEX_JMP 1
#define UNSPEC_FMUL 3
#define UNSPEC_SWAP 2
#define UNSPECV_DELAY_CYCLES 100
#define TMP_REGNO_AVRTINY10 16
#define UNSPECV_GOTO_RECEIVER 4
#define UNSPECV_WRITE_SP_IRQ_OFF 3
#define UNSPECV_DELAY_CYCLES_1 101
#define UNSPECV_DELAY_CYCLES_2 102
#define REG_SP 32
#define UNSPECV_DELAY_CYCLES_4 104

#endif /* GCC_INSN_CONSTANTS_H */
