Design of MCS-51 Evaluation Boards

| II.4 Design of MCS-51 Evaluation Boards When developing embedded systems, debugging aspects should be taken into account as soon as possible. That is why MCS-51 prototype boards should always be armed with a download RAM in the hardware design phase, even if the serial model (probably) doesn't need an external RAM! A $3 RAM can save a $3000 in-circuit emulator and weeks of trouble! Before discussing the basic concepts of program download, it is essential to understand the memory organization of the MCS-51 architecture. First of all, there is an 8-bit address space for internal RAM. Parts of it are directly addressable (DATA space), indirectly addressable (IDATA space), or bit-addressable (BIT space). These address spaces are fully or partly overlapping. Furthermore, the four register banks and the Special Function Registers (SFR) are mapped into this internal address space. This is hard to understand for newbies, but plays no role for program download. Aside of the internal memory, the MCS-51 architecture provides a bus interface for external memory. There are two separate 16-bit address spaces for 64K of program memory (ROM) and 64K of data memory (RAM). Program memory (CODE space) can only be read with the -PSEN bus signal, and data memory (XDATA space) can be read and written with the -RD and -WR bus signals. The -PSEN signal becomes active during instruction fetch cycles and MOVC instructions. The -RD and -WR signals become active during read and write operations with MOVX instructions. The obvious problem is: a downloaded program can only be stored in external RAM, mapped into the XDATA space, whereas program code can only be executed from memory in the CODE space. There must be a way to execute a downloaded program, although it is stored in external RAM! Fortunately, there is a simple trick to solve this: The -OE input of the (usually static) RAM must be driven by a logic AND of the -RD and -PSEN signals of the MCU, rather than by -RD alone. That's all! Then the external RAM can be read and written with MOVX instructions (using -RD and -WR), and program code can be executed from it (using -PSEN). For example, a typical 8051 evaluation board could be designed as follows: A 32K EPROM (e.g. 27C256) is mapped into the CODE space from address 0000H to 7FFFH, containing BOOT-51 at address 0000H. A 32K static RAM (e.g. 62256) is mapped into both the CODE and XDATA spaces from address 8000H to FFFFH. After reset, the MCU starts program execution at address 0000H, and BOOT-51 is running, waiting for commands. When it receives an UPLOAD command from the host computer, it reads an Intel-HEX file and stores it at its start address in the external RAM (e.g. 8000H). If BOOT-51 receives a GO TO 8000 command, it jumps to the specified address 8000H, and the downloaded program is running. A memory map like this can be obtained with a minimum of hardware: The -CE (chip enable) input of the EPROM must be driven by the A15 signal (P2.7) of the MCU, and -CE of the RAM with the inverted A15 signal respectively, to avoid bus conflicts in the CODE space. The -OE (output enable) input of the EPROM must be driven by the -PSEN signal of the MCU, as usual for CODE memory. The -WE (write enable) input of the RAM must be driven by the -WR signal (P3.6) of the MCU, as usual for XDATA memory. Only the -OE (output enable) input of the RAM must be driven by that famous logical AND of the -RD and -PSEN signals of the MCU, to map the RAM into both the XDATA and CODE space. That's it! Because this is so simple, cheap and (in contrast to many in-circuit emulators) absolutely reliable, most MCS-51 family evaluation boards are working like this or similar. In most cases, it is easy to establish a suitable memory map, even on target boards that do not originally support it. If there is no spare AND gate, it may also do, to simply connect the -OE input of the RAM to the -PSEN signal of the MCU only. In this case, the RAM can still be written, but no longer be read with MOVX instructions. Since program code can also be executed from it, this minimized version can still be used as download RAM, but no longer as external data RAM. (In cases of emergency, it can be read with MOVC instructions, however!)