v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=package
spice_ignore=true
verilog_ignore=true
tedax_ignore=true
template="

-- THIS IS A TEMPLATE, REPLACE WITH ACTUAL CODE OR REMOVE INSTANCE!!
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
 
    package aaa is
      type real_vector is array(natural range <>) of real;
      constant dx : real := 0.001 ;
 
    procedure assegna(
        signal A      : inout real;
        signal A_OLD  : in real;
               A_VAL  : in real
    );
 
    end aaa; -- end package declaration
 
 
    package body aaa is
 
 
    procedure assegna(
        signal A      : inout real;
        signal A_OLD  : in real;
               A_VAL  : in real ) is
    constant tdelay: time := 0.01 ns;
    begin
     if (A /=  A_VAL) then
        A <= A_OLD+dx, A_VAL after tdelay;
     end if;
    end assegna;
 
 
    end aaa; -- end package body
"}
V {}
S {}
E {}
L 4 0 -10 355 -10 {}
T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
T {HIDDEN} 135 -5 0 0 0.3 0.3 {}
