v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=scope
template="name=l1"
highlight=true}
V {}
S {}
E {}
L 4 0 0 10 -20 {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
P 4 5 10 -20 10 -140 140 -140 140 -20 10 -20 {}
T {@#0:net_name} 12.5 -18.125 0 0 0.2 0.2 {layer=4}
T {@#0:spice_get_voltage} 12.5 -139.375 0 0 0.15 0.15 {layer=15}
