v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -60 130 -60 {}
L 4 -130 60 130 60 {}
L 4 -130 -60 -130 60 {}
L 4 130 -60 130 60 {}
L 4 130 -50 150 -50 {}
L 4 -150 -50 -130 -50 {}
L 4 -150 -30 -130 -30 {}
L 4 -150 -10 -130 -10 {}
L 4 -150 10 -130 10 {}
L 4 -150 30 -130 30 {}
L 4 -150 50 -130 50 {}
B 5 147.5 -52.5 152.5 -47.5 {name=LDWL[15:0] dir=out }
B 5 -152.5 -52.5 -147.5 -47.5 {name=LDL1X[15:0] dir=in }
B 5 -152.5 -32.5 -147.5 -27.5 {name=LDL2X dir=in }
B 5 -152.5 -12.5 -147.5 -7.5 {name=LDL3X dir=in }
B 5 -152.5 7.5 -147.5 12.5 {name=LDCP dir=in }
B 5 -152.5 27.5 -147.5 32.5 {name=VSS dir=in}
B 5 -152.5 47.5 -147.5 52.5 {name=VCC dir=in}
T {@symname} -49.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -72 0 0 0.2 0.2 {}
T {LDWL[15:0]} 125 -54 0 1 0.2 0.2 {}
T {LDL1X[15:0]} -125 -54 0 0 0.2 0.2 {}
T {LDL2X} -125 -34 0 0 0.2 0.2 {}
T {LDL3X} -125 -14 0 0 0.2 0.2 {}
T {LDCP} -125 6 0 0 0.2 0.2 {}
T {VSS} -125 26 0 0 0.2 0.2 {}
T {VCC} -125 46 0 0 0.2 0.2 {}
