v {xschem version=3.4.7RC file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {}
V {}
S {}
E {}
L 3 860 -680 910 -660 {}
L 3 830 -800 1150 -800 {}
L 3 1190 -800 1510 -800 {}
L 8 850 -660 900 -680 {}
L 11 850 -670 900 -650 {dash=4}
L 16 860 -650 910 -670 {}
B 2 1200 -780 1489 -574 {flags=image
alpha=0.9
[encoded data, 66595 characters]}
B 2 1200 -560 1490 -410 {flags=graph 
y1 = -0.038
y2 = 20
divy = 5
subdivy=1
x1=-8.50378e-06
x2=0.000191496
divx=9
node="led
panel
sw"
color="11 18 6" unitx=m subdivx=4}
B 2 1200 -400 1490 -270 {flags=graph 
y1 = 0.360479
y2 = 3.04484
divy = 6
subdivy=1
x1=-8.50378e-06
x2=0.000191496
divx=8
node=i(vpanel) unitx=m
color=4}
B 4 890 -630 910 -570 {}
B 6 810 -630 830 -570 {ellipse=0,360}
B 7 850 -610 920 -590 {dash=4}
B 7 850 -580 920 -560 {dash=4 fill=full}
B 8 860 -630 880 -570 {}
A 4 875 -215 35.35533905932738 8.13010235415598 360 {}
A 6 940 -270 70.71067811865476 188.130102354156 89.99999999999997 {}
A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511 {}
P 1 10 880 -480 870 -540 950 -520 910 -500 940 -470 920 -470 910 -450 890 -490 880 -470 880 -480 {dash=3}
P 4 6 830 -460 830 -550 820 -500 780 -560 770 -520 810 -480 {bezier=1}
P 15 11 870 -510 880 -550 900 -520 910 -540 920 -510 940 -520 920 -480 890 -490 860 -470 840 -520 870 -510 {fill=true}
T {Welcome to XSCHEM!} 110 -1130 0 0 1 1 {layer=5}
T {This is a test schematic window 

On the left you see some sample circuits. You may descend into any of these by selecting one with a left mouse button click and
pressing the 'e' key, or by menu 'Edit -> Push Schematic'. You can return here after descending into a schematic by hitting 
'<Ctrl>-e' or by menu 'Edit -> Pop'.} 60 -1060 0 0 0.4 0.4 {}
T {Lines} 960 -680 0 0 0.6 0.6 {layer=4}
T {Rectangles /
Ellipses} 960 -640 0 0 0.6 0.6 {layer=4}
T {Polygons /
Beziers} 970 -550 0 0 0.6 0.6 {layer=4}
T {Electrical
wires} 960 -440 0 0 0.6 0.6 {layer=4}
T {XSCHEM OBJECTS} 860 -840 0 0 0.6 0.6 {layer=7}
T {Components} 960 -330 0 0 0.6 0.6 {layer=4}
T {TEXT} 840 -740 0 0 0.5 0.5 {layer=8}
T {TEXT} 840 -790 1 0 0.7 0.7 {layer=6 font=Monospace}
T {Text} 850 -780 0 0 0.5 0.5 {layer=7 font="serif"}
T {TEXT} 940 -780 1 0 0.5 0.5 {weight=bold}
T {Text} 960 -770 0 0 0.6 0.6 {layer=4}
T {Arcs/Circles} 960 -240 0 0 0.6 0.6 {layer=4}
T {Select the components here under
and press'<Ctrl>-h' or <Ctrl>-click
them to visit xschem websites
or local docs} 400 -290 0 0 0.3 0.3 {slant=oblique }
T {SPECIAL OBJECTS} 1220 -840 0 0 0.6 0.6 {layer=7}
T {Embedded
PNG or JPEG
Images} 1530 -780 0 0 0.6 0.6 {layer=4}
T {Simulation
Graphs
} 1530 -550 0 0 0.6 0.6 {layer=4}
T {Bus rippers} 580 -380 0 0 0.6 0.6 {layer=4}
T {Verilog-A example} 800 -940 0 0 0.4 0.4 {}
T {Ngspice + Verilog Cosimulation example} 1190 -940 0 0 0.4 0.4 {}
N 910 -410 940 -410 {lab=#net1}
N 860 -380 860 -360 {lab=#net2}
N 860 -380 920 -380 {lab=#net2}
N 880 -420 910 -410 {lab=#net1}
N 380 -310 640 -310 {lab=BUS[4:0]}
N 510 -400 510 -320 {lab=BUS[1]}
N 410 -350 410 -320 {lab=BUS[2]}
N 460 -400 460 -320 {lab=BUS[2:1]}
N 860 -450 860 -380 {lab=#net2}
N 820 -410 910 -410 {lab=#net1}
C {poweramp.sym} 160 -140 0 0 {name=x1
tclcommand="xschem descend"}
C {tesla.sym} 160 -700 0 0 {name=x2}
C {test_ne555.sym} 160 -660 0 0 {name=x3}
C {test_lm324.sym} 160 -620 0 0 {name=x4}
C {osc.sym} 160 -740 0 0 {name=x5}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {cmos_example.sym} 160 -780 0 0 {name=x6}
C {greycnt.sym} 160 -820 0 0 {name=x8}
C {loading.sym} 160 -860 0 0 {name=x9}
C {inv_bsource.sym} 880 -320 0 0 {name=B1 TABLE="1.4 3.0 1.6 0.0"}
C {launcher.sym} 460 -140 0 0 {name=h1 
descr="XSCHEM ON REPO.HU" 
url="http://repo.hu/projects/xschem"}
C {launcher.sym} 460 -90 0 0 {name=h3 
descr="Toggle light/dark 
colorscheme" 
tclcommand="xschem toggle_colorscheme"
}
C {launcher.sym} 460 -190 0 0 {name=h2 
descr="LOCAL DOCUMENTATION" 
url="$\{XSCHEM_SHAREDIR\}/../doc/xschem/index.html"


}
C {rlc.sym} 160 -900 0 0 {name=x0}
C {lab_pin.sym} 640 -310 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
C {bus_connect.sym} 500 -310 0 0 {name=l3 lab=BUS[1]}
C {bus_connect_nolab.sym} 400 -310 0 0 {name=r1}
C {lab_pin.sym} 410 -350 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {LCC_instances.sym} 160 -580 0 0 {name=x7}
C {test_backannotated_subckt.sym} 160 -540 0 0 {name=x10}
C {plot_manipulation.sym} 160 -500 0 0 {name=x11}
C {logic_test.sym} 160 -460 0 0 {name=x12}
C {simulate_ff.sym} 160 -420 0 0 {name=x13}
C {test_mos_verilog.sym} 160 -380 0 0 {name=x14}
C {launcher.sym} 1265 -225 0 0 {name=h5 
descr=" Ctrl-Left-Click to load/
unload waveforms" 
tclcommand="xschem raw_read_from_attr"
spice_data="
[encoded data, 170925 characters]
UsA+"
}
C {test_ac.sym} 160 -340 0 0 {name=x15}
C {rom8k.sym} 160 -180 0 0 {name=x17}
C {test_doublepin.sym} 160 -300 0 0 {name=x19}
C {classD_amp.sym} 160 -220 0 0 {name=x20}
C {delta_sigma.sym} 480 -900 0 0 {name=x21}
C {solar_panel.sym} 480 -860 0 0 {name=xsolar}
C {test_extracted_netlist.sym} 160 -260 0 0 {name=x23
tclcommand="xschem descend"}
C {poweramp_lcc.sym} 160 -100 0 0 {name=x16
tclcommand="xschem descend"}
C {test_symbolgen.sym} 480 -820 0 0 {name=x18}
C {inst_sch_select.sym} 480 -740 0 0 {name=x24}
C {test_bus_tap.sym} 480 -700 0 0 {name=x22}
C {bus_tap.sym} 450 -310 1 1 {name=l5 lab=[2:1]}
C {test_jfet.sym} 480 -660 0 0 {name=x25}
C {test_short_option.sym} 480 -620 0 0 {name=x26}
C {test_lvs_ignore.sym} 480 -580 0 0 {name=x27}
C {test_generators.sym} 480 -540 0 0 {name=x28}
C {autozero_comp.sym} 480 -500 0 0 {name=x29}
C {tb_symbol_include.sym} 480 -780 0 0 {name=x30}
C {intuitive_interface_cheatsheet.sym} 1060 -100 0 0 {name=x31}
C {test_nyquist.sym} 480 -460 0 0 {name=x32}
C {tb_diff_amp.sym} 890 -890 0 0 {name=x33}
C {tb_sar_adc.sym} 1360 -890 0 0 {name=x34}
