v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=pjfet
format="@spiceprefix@name @pinlist @model area=@area @extra m=@m"
template="name=J1 model=pjfet area=1 m=1"
}
V {}
S {}
E {}
L 4 5 -30 5 30 {}
L 4 5 -20 20 -20 {}
L 4 20 -30 20 -20 {}
L 4 5 20 20 20 {}
L 4 20 20 20 30 {}
B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
P 4 7 5 0 -7.5 0 -7.5 5 -17.5 0 -7.5 -5 -7.5 0 5 0 {fill=true}
T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
T {@spiceprefix@name} 7.5 6.25 0 0 0.2 0.2 {}
T {D} 25 20 0 0 0.15 0.15 {}
T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@model} 7.5 -18.75 0 0 0.2 0.2 {}
T {area=@area} 7.5 -6.25 0 0 0.2 0.2 {}
