v {xschem version=3.4.6RC file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=vcvs
format="@name @pinlist @vnam @value"
template="name=F1 vnam=v1 value=1"}
V {}
S {}
E {}
L 4 0 -20 20 -0 {}
L 4 -20 0 0 -20 {}
L 4 -20 0 0 20 {}
L 4 0 20 20 0 {}
L 4 0 20 0 30 {}
L 4 0 -30 -0 -20 {}
L 4 -5 5 0 10 {}
L 4 -5 5 5 5 {}
L 4 0 10 5 5 {}
L 4 0 -5 0 5 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=in}
B 5 -2.5 27.5 2.5 32.5 {name=m dir=in}
T {@value} 25 10 0 0 0.2 0.2 {}
T {@name} 25 -15 0 0 0.2 0.2 {}
T {@vnam} 25 -2.5 0 0 0.2 0.2 {}
T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@spice_get_current} -24.375 -5 0 1 0.2 0.2 {layer=17}
