ARC Directives - Using as
Description: Using as

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#### 9.2.4 ARC Machine Directives

The ARC version of `as` supports the following additional machine directives:

`.2byte` expressions
  *TODO*

`.3byte` expressions
  *TODO*

`.4byte` expressions
  *TODO*

`.extAuxRegister` name`,`address`,`mode
  The ARCtangent A4 has extensible auxiliary register space. The auxiliary registers can be defined in the assembler source code by using this directive. The first parameter is the name of the new auxiallry register. The second parameter is the address of the register in the auxiliary register memory map for the variant of the ARC. The third parameter specifies the mode in which the register can be operated is and it can be one of:
  `r (readonly)`
  `w (write only)`
  `r|w (read or write)`

  For example:

                  .extAuxRegister mulhi,0x12,w

  This specifies an extension auxiliary register called mulhi which is at address 0x12 in the memory space and which is only writable.

`.extCondCode` suffix`,`value
  The condition codes on the ARCtangent A4 are extensible and can be specified by means of this assembler directive. They are specified by the suffix and the value for the condition code. They can be used to specify extra condition codes with any values. For example:

                  .extCondCode is_busy,0x14

                   add.is_busy  r1,r2,r3
                   bis_busy     _main

`.extCoreRegister` name`,`regnum`,`mode`,`shortcut
  Specifies an extension core register name for the application. This allows a register name with a valid regnum between 0 and 60, with the following as valid values for mode
  ‘`r (readonly)`’
  ‘`w (write only)`’
  ‘`r|w (read or write)`’

  The other parameter gives a description of the register having a shortcut in the pipeline. The valid values are:

  `can_shortcut`
  `cannot_shortcut`

  For example:

                  .extCoreRegister mlo,57,r,can_shortcut

  This defines an extension core register mlo with the value 57 which can shortcut the pipeline.

`.extInstruction` name`,`opcode`,`subopcode`,`suffixclass`,`syntaxclass
  The ARCtangent A4 allows the user to specify extension instructions. The extension instructions are not macros. The assembler creates encodings for use of these instructions according to the specification by the user. The parameters are:
  •name
    Name of the extension instruction
  •opcode
    Opcode to be used. (Bits 27:31 in the encoding). Valid values 0x10-0x1f or 0x03
  •subopcode
    Subopcode to be used. Valid values are from 0x09-0x3f. However the correct value also depends on syntaxclass
  •suffixclass
    Determines the kinds of suffixes to be allowed. Valid values are `SUFFIX_NONE`, `SUFFIX_COND`, `SUFFIX_FLAG` which indicates the absence or presence of conditional suffixes and flag setting by the extension instruction. It is also possible to specify that an instruction sets the flags and is conditional by using `SUFFIX_CODE` | `SUFFIX_FLAG`.
  •syntaxclass
    Determines the syntax class for the instruction. It can have the following values:
    `SYNTAX_2OP:`
      2 Operand Instruction
    `SYNTAX_3OP:`
      3 Operand Instruction

    In addition there could be modifiers for the syntax class as described below:

    Syntax Class Modifiers are:
    - `OP1_MUST_BE_IMM`: Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with SYNTAX_3OP as given in the example below. This could usually be used to set the flags using specific instructions and not retain results.
    - `OP1_IMM_IMPLIED`: Modifies syntax class SYNTAX_20P, it specifies that there is an implied immediate destination operand which does not appear in the syntax. For example, if the source code contains an instruction like:

                              inst r1,r2

      it really means that the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it with SYNTAX_20P.

  For example, defining 64-bit multiplier with immediate operands:

                .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
                                SYNTAX_3OP|OP1_MUST_BE_IMM

  The above specifies an extension instruction called mp64 which has 3 operands, sets the flags, can be used with a condition code, for which the first operand is an immediate. (Equivalent to discarding the result of the operation).

                 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED

  This describes a 2 operand instruction with an implicit first immediate operand. The result of this operation would be discarded.

`.half` expressions
  *TODO*

`.long` expressions
  *TODO*

`.option` arc|arc5|arc6|arc7|arc8
  The `.option` directive must be followed by the desired core version. Again `arc` is an alias for `arc6`.

  Note: the `.option` directive overrides the command line option `-marc`; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6).

`.short` expressions
  *TODO*

`.word` expressions
  *TODO*