\chapter{MC68HC908 Processor}
\label{processor:MC68HC908}
\index{Processor!68908}
\index{Processor!MC68HC908}

%% Variants of the \mono{MC68HC908} CPU are widely used in DIN-rail mountable Micro-SPS from french manufacturer Crouzet. 
%% Variant mr32  used in  Crouzet XT20 Millenium
%% Variant jb8   used in  USB08 Welcome Kit (Evaluation Board)
The \mono{MC68HC908} CPU is manufactured by Motorola/Freescale/NXP. There is a wide spectrum of CPU variants available.
\dasm has include-file support for the variants {\it{jk1}}, {\it{jk3}}, {\it{jb8}} and {\it{mr32}} in its machines/68hc908 subdirectory.
Some CPU variants can be clocked by a PLL and support advanced PWM generation for motor applications where others feature a USB 1.0 interface 
or special keyboard GPIO. Various numbers of 8- and 16bit timers for input capture / output compare operations are available as well as 10bit 
ADC converters, SPI (sometimes also UART) communication interface and brown-out reset. Onchip flash memory ranges from 2 to 32kByte, RAM ranges 
from 128 to 768 bytes and clocking speeds ranges from 1 to 8MHz.

\section{Endianness}

The \mono{MC68HC908} is a big-endian machine. Byte ordering in words is high, then low.

\section{Adressing modes}

Beside the "standard" addressing modes (listed in table \ref{standard_address_modes_68hc908}) there are 6 special addressing modes that 
apply to 6 distinct opcodes (table \ref{special_address_modes_68hc908}). These addressing modes include inherent given source- \emph{and} destination- 
address mode and optionally an increment operation for the index register. The modes dd, dix+, imd and ix+d apply to move-data mnemonics.
The modes ix+ an ix8+ apply to compare-and-branch-if-equal mnemonic.


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\def\standardAddressingModesCaption68hc908{Abbreviations for standard addressing modes}
\def\specialAddressingModesCaption68hc908{Abbreviations for special addressing modes}

\input{68hc908_standard_addressing_modes.tex}
\input{68hc908_special_addressing_modes.tex}
 
\begin{table}[hbp]
\parbox[t]{.48\linewidth}{
\standardAddressModesTable
}
\hfill
\parbox[t]{.48\linewidth}{
\specialAddressModesTable
}
\end{table}

\newpage
\section{Opcode Summary}

Although dasm mnemonics are case-insensitive they are written in camel-case in table \ref{OpcodeSummary68hc908}.
This is to indicate the inherent given register(s) for the first\footnote{and second operand if given} operand:

\begin{itemize}
\item 8bit-register A
\item 8bit-register X
\item 8bit-register H
\item 16bit-register HX (combined of 8bit-register H and X)
\item 8bit-register P (stack-pointer low byte)
\item 16bit-register S (stack-pointer)
\end{itemize}

There are two opcodes that need operand arguments which don't fit into any scheme
implemented in \dasm. However they can be generated by using 
forced\footnote{see \ref{pseudoop:force}} addressing mode. 
Extension {\it{.ix}} (implied, X-indexed) has to be used in this case.

\begin{table}
\begin{tabular}{ccp{0.5\linewidth}}
Opcode & Mnemonic & Description
\\
\hhline{---}
{\mono{\$71}} & {\mono{cbeq{\it{.ix}}}} & \makebox[2pt]{}{compare register A with value indexed by X, branch relative if not equal and post-increment\footnote{note that also opcode {\mono{\$61}} does post-increment X} X}
\\
{\mono{\$7B}} & {\mono{dbnz{\it{.ix}}}} & \makebox[2pt]{}{decrement value indexed by X and branch relative if not zero.}
\end{tabular}
\caption{}
\end{table}

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	\input{68hc908_opcode_summary.tex}%
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