#include "asm/riscv/init.hpp"

#include "LIEF/asm/riscv/opcodes.hpp"

namespace LIEF::assembly::riscv::py {
template<>
void create<LIEF::assembly::riscv::OPCODE>(nb::module_& m) {
  nb::enum_<LIEF::assembly::riscv::OPCODE> opcodes(m, "OPCODE");
  opcodes.value("PHI", LIEF::assembly::riscv::OPCODE::PHI)
  .value("INLINEASM", LIEF::assembly::riscv::OPCODE::INLINEASM)
  .value("INLINEASM_BR", LIEF::assembly::riscv::OPCODE::INLINEASM_BR)
  .value("CFI_INSTRUCTION", LIEF::assembly::riscv::OPCODE::CFI_INSTRUCTION)
  .value("EH_LABEL", LIEF::assembly::riscv::OPCODE::EH_LABEL)
  .value("GC_LABEL", LIEF::assembly::riscv::OPCODE::GC_LABEL)
  .value("ANNOTATION_LABEL", LIEF::assembly::riscv::OPCODE::ANNOTATION_LABEL)
  .value("KILL", LIEF::assembly::riscv::OPCODE::KILL)
  .value("EXTRACT_SUBREG", LIEF::assembly::riscv::OPCODE::EXTRACT_SUBREG)
  .value("INSERT_SUBREG", LIEF::assembly::riscv::OPCODE::INSERT_SUBREG)
  .value("IMPLICIT_DEF", LIEF::assembly::riscv::OPCODE::IMPLICIT_DEF)
  .value("SUBREG_TO_REG", LIEF::assembly::riscv::OPCODE::SUBREG_TO_REG)
  .value("COPY_TO_REGCLASS", LIEF::assembly::riscv::OPCODE::COPY_TO_REGCLASS)
  .value("DBG_VALUE", LIEF::assembly::riscv::OPCODE::DBG_VALUE)
  .value("DBG_VALUE_LIST", LIEF::assembly::riscv::OPCODE::DBG_VALUE_LIST)
  .value("DBG_INSTR_REF", LIEF::assembly::riscv::OPCODE::DBG_INSTR_REF)
  .value("DBG_PHI", LIEF::assembly::riscv::OPCODE::DBG_PHI)
  .value("DBG_LABEL", LIEF::assembly::riscv::OPCODE::DBG_LABEL)
  .value("REG_SEQUENCE", LIEF::assembly::riscv::OPCODE::REG_SEQUENCE)
  .value("COPY", LIEF::assembly::riscv::OPCODE::COPY)
  .value("BUNDLE", LIEF::assembly::riscv::OPCODE::BUNDLE)
  .value("LIFETIME_START", LIEF::assembly::riscv::OPCODE::LIFETIME_START)
  .value("LIFETIME_END", LIEF::assembly::riscv::OPCODE::LIFETIME_END)
  .value("PSEUDO_PROBE", LIEF::assembly::riscv::OPCODE::PSEUDO_PROBE)
  .value("ARITH_FENCE", LIEF::assembly::riscv::OPCODE::ARITH_FENCE)
  .value("STACKMAP", LIEF::assembly::riscv::OPCODE::STACKMAP)
  .value("FENTRY_CALL", LIEF::assembly::riscv::OPCODE::FENTRY_CALL)
  .value("PATCHPOINT", LIEF::assembly::riscv::OPCODE::PATCHPOINT)
  .value("LOAD_STACK_GUARD", LIEF::assembly::riscv::OPCODE::LOAD_STACK_GUARD)
  .value("PREALLOCATED_SETUP", LIEF::assembly::riscv::OPCODE::PREALLOCATED_SETUP)
  .value("PREALLOCATED_ARG", LIEF::assembly::riscv::OPCODE::PREALLOCATED_ARG)
  .value("STATEPOINT", LIEF::assembly::riscv::OPCODE::STATEPOINT)
  .value("LOCAL_ESCAPE", LIEF::assembly::riscv::OPCODE::LOCAL_ESCAPE)
  .value("FAULTING_OP", LIEF::assembly::riscv::OPCODE::FAULTING_OP)
  .value("PATCHABLE_OP", LIEF::assembly::riscv::OPCODE::PATCHABLE_OP)
  .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_ENTER)
  .value("PATCHABLE_RET", LIEF::assembly::riscv::OPCODE::PATCHABLE_RET)
  .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_EXIT)
  .value("PATCHABLE_TAIL_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_TAIL_CALL)
  .value("PATCHABLE_EVENT_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_EVENT_CALL)
  .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_TYPED_EVENT_CALL)
  .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::riscv::OPCODE::ICALL_BRANCH_FUNNEL)
  .value("MEMBARRIER", LIEF::assembly::riscv::OPCODE::MEMBARRIER)
  .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::riscv::OPCODE::JUMP_TABLE_DEBUG_INFO)
  .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ENTRY)
  .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ANCHOR)
  .value("CONVERGENCECTRL_LOOP", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_LOOP)
  .value("CONVERGENCECTRL_GLUE", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_GLUE)
  .value("G_ASSERT_SEXT", LIEF::assembly::riscv::OPCODE::G_ASSERT_SEXT)
  .value("G_ASSERT_ZEXT", LIEF::assembly::riscv::OPCODE::G_ASSERT_ZEXT)
  .value("G_ASSERT_ALIGN", LIEF::assembly::riscv::OPCODE::G_ASSERT_ALIGN)
  .value("G_ADD", LIEF::assembly::riscv::OPCODE::G_ADD)
  .value("G_SUB", LIEF::assembly::riscv::OPCODE::G_SUB)
  .value("G_MUL", LIEF::assembly::riscv::OPCODE::G_MUL)
  .value("G_SDIV", LIEF::assembly::riscv::OPCODE::G_SDIV)
  .value("G_UDIV", LIEF::assembly::riscv::OPCODE::G_UDIV)
  .value("G_SREM", LIEF::assembly::riscv::OPCODE::G_SREM)
  .value("G_UREM", LIEF::assembly::riscv::OPCODE::G_UREM)
  .value("G_SDIVREM", LIEF::assembly::riscv::OPCODE::G_SDIVREM)
  .value("G_UDIVREM", LIEF::assembly::riscv::OPCODE::G_UDIVREM)
  .value("G_AND", LIEF::assembly::riscv::OPCODE::G_AND)
  .value("G_OR", LIEF::assembly::riscv::OPCODE::G_OR)
  .value("G_XOR", LIEF::assembly::riscv::OPCODE::G_XOR)
  .value("G_IMPLICIT_DEF", LIEF::assembly::riscv::OPCODE::G_IMPLICIT_DEF)
  .value("G_PHI", LIEF::assembly::riscv::OPCODE::G_PHI)
  .value("G_FRAME_INDEX", LIEF::assembly::riscv::OPCODE::G_FRAME_INDEX)
  .value("G_GLOBAL_VALUE", LIEF::assembly::riscv::OPCODE::G_GLOBAL_VALUE)
  .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::riscv::OPCODE::G_PTRAUTH_GLOBAL_VALUE)
  .value("G_CONSTANT_POOL", LIEF::assembly::riscv::OPCODE::G_CONSTANT_POOL)
  .value("G_EXTRACT", LIEF::assembly::riscv::OPCODE::G_EXTRACT)
  .value("G_UNMERGE_VALUES", LIEF::assembly::riscv::OPCODE::G_UNMERGE_VALUES)
  .value("G_INSERT", LIEF::assembly::riscv::OPCODE::G_INSERT)
  .value("G_MERGE_VALUES", LIEF::assembly::riscv::OPCODE::G_MERGE_VALUES)
  .value("G_BUILD_VECTOR", LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR)
  .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR_TRUNC)
  .value("G_CONCAT_VECTORS", LIEF::assembly::riscv::OPCODE::G_CONCAT_VECTORS)
  .value("G_PTRTOINT", LIEF::assembly::riscv::OPCODE::G_PTRTOINT)
  .value("G_INTTOPTR", LIEF::assembly::riscv::OPCODE::G_INTTOPTR)
  .value("G_BITCAST", LIEF::assembly::riscv::OPCODE::G_BITCAST)
  .value("G_FREEZE", LIEF::assembly::riscv::OPCODE::G_FREEZE)
  .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::riscv::OPCODE::G_CONSTANT_FOLD_BARRIER)
  .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_FPTRUNC_ROUND)
  .value("G_INTRINSIC_TRUNC", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_TRUNC)
  .value("G_INTRINSIC_ROUND", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUND)
  .value("G_INTRINSIC_LRINT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LRINT)
  .value("G_INTRINSIC_LLRINT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LLRINT)
  .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUNDEVEN)
  .value("G_READCYCLECOUNTER", LIEF::assembly::riscv::OPCODE::G_READCYCLECOUNTER)
  .value("G_READSTEADYCOUNTER", LIEF::assembly::riscv::OPCODE::G_READSTEADYCOUNTER)
  .value("G_LOAD", LIEF::assembly::riscv::OPCODE::G_LOAD)
  .value("G_SEXTLOAD", LIEF::assembly::riscv::OPCODE::G_SEXTLOAD)
  .value("G_ZEXTLOAD", LIEF::assembly::riscv::OPCODE::G_ZEXTLOAD)
  .value("G_INDEXED_LOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_LOAD)
  .value("G_INDEXED_SEXTLOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_SEXTLOAD)
  .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_ZEXTLOAD)
  .value("G_STORE", LIEF::assembly::riscv::OPCODE::G_STORE)
  .value("G_INDEXED_STORE", LIEF::assembly::riscv::OPCODE::G_INDEXED_STORE)
  .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
  .value("G_ATOMIC_CMPXCHG", LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG)
  .value("G_ATOMICRMW_XCHG", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XCHG)
  .value("G_ATOMICRMW_ADD", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_ADD)
  .value("G_ATOMICRMW_SUB", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_SUB)
  .value("G_ATOMICRMW_AND", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_AND)
  .value("G_ATOMICRMW_NAND", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_NAND)
  .value("G_ATOMICRMW_OR", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_OR)
  .value("G_ATOMICRMW_XOR", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XOR)
  .value("G_ATOMICRMW_MAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MAX)
  .value("G_ATOMICRMW_MIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MIN)
  .value("G_ATOMICRMW_UMAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMAX)
  .value("G_ATOMICRMW_UMIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMIN)
  .value("G_ATOMICRMW_FADD", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FADD)
  .value("G_ATOMICRMW_FSUB", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FSUB)
  .value("G_ATOMICRMW_FMAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMAX)
  .value("G_ATOMICRMW_FMIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMIN)
  .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UINC_WRAP)
  .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UDEC_WRAP)
  .value("G_FENCE", LIEF::assembly::riscv::OPCODE::G_FENCE)
  .value("G_PREFETCH", LIEF::assembly::riscv::OPCODE::G_PREFETCH)
  .value("G_BRCOND", LIEF::assembly::riscv::OPCODE::G_BRCOND)
  .value("G_BRINDIRECT", LIEF::assembly::riscv::OPCODE::G_BRINDIRECT)
  .value("G_INVOKE_REGION_START", LIEF::assembly::riscv::OPCODE::G_INVOKE_REGION_START)
  .value("G_INTRINSIC", LIEF::assembly::riscv::OPCODE::G_INTRINSIC)
  .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS)
  .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT)
  .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS)
  .value("G_ANYEXT", LIEF::assembly::riscv::OPCODE::G_ANYEXT)
  .value("G_TRUNC", LIEF::assembly::riscv::OPCODE::G_TRUNC)
  .value("G_CONSTANT", LIEF::assembly::riscv::OPCODE::G_CONSTANT)
  .value("G_FCONSTANT", LIEF::assembly::riscv::OPCODE::G_FCONSTANT)
  .value("G_VASTART", LIEF::assembly::riscv::OPCODE::G_VASTART)
  .value("G_VAARG", LIEF::assembly::riscv::OPCODE::G_VAARG)
  .value("G_SEXT", LIEF::assembly::riscv::OPCODE::G_SEXT)
  .value("G_SEXT_INREG", LIEF::assembly::riscv::OPCODE::G_SEXT_INREG)
  .value("G_ZEXT", LIEF::assembly::riscv::OPCODE::G_ZEXT)
  .value("G_SHL", LIEF::assembly::riscv::OPCODE::G_SHL)
  .value("G_LSHR", LIEF::assembly::riscv::OPCODE::G_LSHR)
  .value("G_ASHR", LIEF::assembly::riscv::OPCODE::G_ASHR)
  .value("G_FSHL", LIEF::assembly::riscv::OPCODE::G_FSHL)
  .value("G_FSHR", LIEF::assembly::riscv::OPCODE::G_FSHR)
  .value("G_ROTR", LIEF::assembly::riscv::OPCODE::G_ROTR)
  .value("G_ROTL", LIEF::assembly::riscv::OPCODE::G_ROTL)
  .value("G_ICMP", LIEF::assembly::riscv::OPCODE::G_ICMP)
  .value("G_FCMP", LIEF::assembly::riscv::OPCODE::G_FCMP)
  .value("G_SCMP", LIEF::assembly::riscv::OPCODE::G_SCMP)
  .value("G_UCMP", LIEF::assembly::riscv::OPCODE::G_UCMP)
  .value("G_SELECT", LIEF::assembly::riscv::OPCODE::G_SELECT)
  .value("G_UADDO", LIEF::assembly::riscv::OPCODE::G_UADDO)
  .value("G_UADDE", LIEF::assembly::riscv::OPCODE::G_UADDE)
  .value("G_USUBO", LIEF::assembly::riscv::OPCODE::G_USUBO)
  .value("G_USUBE", LIEF::assembly::riscv::OPCODE::G_USUBE)
  .value("G_SADDO", LIEF::assembly::riscv::OPCODE::G_SADDO)
  .value("G_SADDE", LIEF::assembly::riscv::OPCODE::G_SADDE)
  .value("G_SSUBO", LIEF::assembly::riscv::OPCODE::G_SSUBO)
  .value("G_SSUBE", LIEF::assembly::riscv::OPCODE::G_SSUBE)
  .value("G_UMULO", LIEF::assembly::riscv::OPCODE::G_UMULO)
  .value("G_SMULO", LIEF::assembly::riscv::OPCODE::G_SMULO)
  .value("G_UMULH", LIEF::assembly::riscv::OPCODE::G_UMULH)
  .value("G_SMULH", LIEF::assembly::riscv::OPCODE::G_SMULH)
  .value("G_UADDSAT", LIEF::assembly::riscv::OPCODE::G_UADDSAT)
  .value("G_SADDSAT", LIEF::assembly::riscv::OPCODE::G_SADDSAT)
  .value("G_USUBSAT", LIEF::assembly::riscv::OPCODE::G_USUBSAT)
  .value("G_SSUBSAT", LIEF::assembly::riscv::OPCODE::G_SSUBSAT)
  .value("G_USHLSAT", LIEF::assembly::riscv::OPCODE::G_USHLSAT)
  .value("G_SSHLSAT", LIEF::assembly::riscv::OPCODE::G_SSHLSAT)
  .value("G_SMULFIX", LIEF::assembly::riscv::OPCODE::G_SMULFIX)
  .value("G_UMULFIX", LIEF::assembly::riscv::OPCODE::G_UMULFIX)
  .value("G_SMULFIXSAT", LIEF::assembly::riscv::OPCODE::G_SMULFIXSAT)
  .value("G_UMULFIXSAT", LIEF::assembly::riscv::OPCODE::G_UMULFIXSAT)
  .value("G_SDIVFIX", LIEF::assembly::riscv::OPCODE::G_SDIVFIX)
  .value("G_UDIVFIX", LIEF::assembly::riscv::OPCODE::G_UDIVFIX)
  .value("G_SDIVFIXSAT", LIEF::assembly::riscv::OPCODE::G_SDIVFIXSAT)
  .value("G_UDIVFIXSAT", LIEF::assembly::riscv::OPCODE::G_UDIVFIXSAT)
  .value("G_FADD", LIEF::assembly::riscv::OPCODE::G_FADD)
  .value("G_FSUB", LIEF::assembly::riscv::OPCODE::G_FSUB)
  .value("G_FMUL", LIEF::assembly::riscv::OPCODE::G_FMUL)
  .value("G_FMA", LIEF::assembly::riscv::OPCODE::G_FMA)
  .value("G_FMAD", LIEF::assembly::riscv::OPCODE::G_FMAD)
  .value("G_FDIV", LIEF::assembly::riscv::OPCODE::G_FDIV)
  .value("G_FREM", LIEF::assembly::riscv::OPCODE::G_FREM)
  .value("G_FPOW", LIEF::assembly::riscv::OPCODE::G_FPOW)
  .value("G_FPOWI", LIEF::assembly::riscv::OPCODE::G_FPOWI)
  .value("G_FEXP", LIEF::assembly::riscv::OPCODE::G_FEXP)
  .value("G_FEXP2", LIEF::assembly::riscv::OPCODE::G_FEXP2)
  .value("G_FEXP10", LIEF::assembly::riscv::OPCODE::G_FEXP10)
  .value("G_FLOG", LIEF::assembly::riscv::OPCODE::G_FLOG)
  .value("G_FLOG2", LIEF::assembly::riscv::OPCODE::G_FLOG2)
  .value("G_FLOG10", LIEF::assembly::riscv::OPCODE::G_FLOG10)
  .value("G_FLDEXP", LIEF::assembly::riscv::OPCODE::G_FLDEXP)
  .value("G_FFREXP", LIEF::assembly::riscv::OPCODE::G_FFREXP)
  .value("G_FNEG", LIEF::assembly::riscv::OPCODE::G_FNEG)
  .value("G_FPEXT", LIEF::assembly::riscv::OPCODE::G_FPEXT)
  .value("G_FPTRUNC", LIEF::assembly::riscv::OPCODE::G_FPTRUNC)
  .value("G_FPTOSI", LIEF::assembly::riscv::OPCODE::G_FPTOSI)
  .value("G_FPTOUI", LIEF::assembly::riscv::OPCODE::G_FPTOUI)
  .value("G_SITOFP", LIEF::assembly::riscv::OPCODE::G_SITOFP)
  .value("G_UITOFP", LIEF::assembly::riscv::OPCODE::G_UITOFP)
  .value("G_FABS", LIEF::assembly::riscv::OPCODE::G_FABS)
  .value("G_FCOPYSIGN", LIEF::assembly::riscv::OPCODE::G_FCOPYSIGN)
  .value("G_IS_FPCLASS", LIEF::assembly::riscv::OPCODE::G_IS_FPCLASS)
  .value("G_FCANONICALIZE", LIEF::assembly::riscv::OPCODE::G_FCANONICALIZE)
  .value("G_FMINNUM", LIEF::assembly::riscv::OPCODE::G_FMINNUM)
  .value("G_FMAXNUM", LIEF::assembly::riscv::OPCODE::G_FMAXNUM)
  .value("G_FMINNUM_IEEE", LIEF::assembly::riscv::OPCODE::G_FMINNUM_IEEE)
  .value("G_FMAXNUM_IEEE", LIEF::assembly::riscv::OPCODE::G_FMAXNUM_IEEE)
  .value("G_FMINIMUM", LIEF::assembly::riscv::OPCODE::G_FMINIMUM)
  .value("G_FMAXIMUM", LIEF::assembly::riscv::OPCODE::G_FMAXIMUM)
  .value("G_GET_FPENV", LIEF::assembly::riscv::OPCODE::G_GET_FPENV)
  .value("G_SET_FPENV", LIEF::assembly::riscv::OPCODE::G_SET_FPENV)
  .value("G_RESET_FPENV", LIEF::assembly::riscv::OPCODE::G_RESET_FPENV)
  .value("G_GET_FPMODE", LIEF::assembly::riscv::OPCODE::G_GET_FPMODE)
  .value("G_SET_FPMODE", LIEF::assembly::riscv::OPCODE::G_SET_FPMODE)
  .value("G_RESET_FPMODE", LIEF::assembly::riscv::OPCODE::G_RESET_FPMODE)
  .value("G_PTR_ADD", LIEF::assembly::riscv::OPCODE::G_PTR_ADD)
  .value("G_PTRMASK", LIEF::assembly::riscv::OPCODE::G_PTRMASK)
  .value("G_SMIN", LIEF::assembly::riscv::OPCODE::G_SMIN)
  .value("G_SMAX", LIEF::assembly::riscv::OPCODE::G_SMAX)
  .value("G_UMIN", LIEF::assembly::riscv::OPCODE::G_UMIN)
  .value("G_UMAX", LIEF::assembly::riscv::OPCODE::G_UMAX)
  .value("G_ABS", LIEF::assembly::riscv::OPCODE::G_ABS)
  .value("G_LROUND", LIEF::assembly::riscv::OPCODE::G_LROUND)
  .value("G_LLROUND", LIEF::assembly::riscv::OPCODE::G_LLROUND)
  .value("G_BR", LIEF::assembly::riscv::OPCODE::G_BR)
  .value("G_BRJT", LIEF::assembly::riscv::OPCODE::G_BRJT)
  .value("G_VSCALE", LIEF::assembly::riscv::OPCODE::G_VSCALE)
  .value("G_INSERT_SUBVECTOR", LIEF::assembly::riscv::OPCODE::G_INSERT_SUBVECTOR)
  .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::riscv::OPCODE::G_EXTRACT_SUBVECTOR)
  .value("G_INSERT_VECTOR_ELT", LIEF::assembly::riscv::OPCODE::G_INSERT_VECTOR_ELT)
  .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::riscv::OPCODE::G_EXTRACT_VECTOR_ELT)
  .value("G_SHUFFLE_VECTOR", LIEF::assembly::riscv::OPCODE::G_SHUFFLE_VECTOR)
  .value("G_SPLAT_VECTOR", LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR)
  .value("G_VECTOR_COMPRESS", LIEF::assembly::riscv::OPCODE::G_VECTOR_COMPRESS)
  .value("G_CTTZ", LIEF::assembly::riscv::OPCODE::G_CTTZ)
  .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::riscv::OPCODE::G_CTTZ_ZERO_UNDEF)
  .value("G_CTLZ", LIEF::assembly::riscv::OPCODE::G_CTLZ)
  .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::riscv::OPCODE::G_CTLZ_ZERO_UNDEF)
  .value("G_CTPOP", LIEF::assembly::riscv::OPCODE::G_CTPOP)
  .value("G_BSWAP", LIEF::assembly::riscv::OPCODE::G_BSWAP)
  .value("G_BITREVERSE", LIEF::assembly::riscv::OPCODE::G_BITREVERSE)
  .value("G_FCEIL", LIEF::assembly::riscv::OPCODE::G_FCEIL)
  .value("G_FCOS", LIEF::assembly::riscv::OPCODE::G_FCOS)
  .value("G_FSIN", LIEF::assembly::riscv::OPCODE::G_FSIN)
  .value("G_FTAN", LIEF::assembly::riscv::OPCODE::G_FTAN)
  .value("G_FACOS", LIEF::assembly::riscv::OPCODE::G_FACOS)
  .value("G_FASIN", LIEF::assembly::riscv::OPCODE::G_FASIN)
  .value("G_FATAN", LIEF::assembly::riscv::OPCODE::G_FATAN)
  .value("G_FCOSH", LIEF::assembly::riscv::OPCODE::G_FCOSH)
  .value("G_FSINH", LIEF::assembly::riscv::OPCODE::G_FSINH)
  .value("G_FTANH", LIEF::assembly::riscv::OPCODE::G_FTANH)
  .value("G_FSQRT", LIEF::assembly::riscv::OPCODE::G_FSQRT)
  .value("G_FFLOOR", LIEF::assembly::riscv::OPCODE::G_FFLOOR)
  .value("G_FRINT", LIEF::assembly::riscv::OPCODE::G_FRINT)
  .value("G_FNEARBYINT", LIEF::assembly::riscv::OPCODE::G_FNEARBYINT)
  .value("G_ADDRSPACE_CAST", LIEF::assembly::riscv::OPCODE::G_ADDRSPACE_CAST)
  .value("G_BLOCK_ADDR", LIEF::assembly::riscv::OPCODE::G_BLOCK_ADDR)
  .value("G_JUMP_TABLE", LIEF::assembly::riscv::OPCODE::G_JUMP_TABLE)
  .value("G_DYN_STACKALLOC", LIEF::assembly::riscv::OPCODE::G_DYN_STACKALLOC)
  .value("G_STACKSAVE", LIEF::assembly::riscv::OPCODE::G_STACKSAVE)
  .value("G_STACKRESTORE", LIEF::assembly::riscv::OPCODE::G_STACKRESTORE)
  .value("G_STRICT_FADD", LIEF::assembly::riscv::OPCODE::G_STRICT_FADD)
  .value("G_STRICT_FSUB", LIEF::assembly::riscv::OPCODE::G_STRICT_FSUB)
  .value("G_STRICT_FMUL", LIEF::assembly::riscv::OPCODE::G_STRICT_FMUL)
  .value("G_STRICT_FDIV", LIEF::assembly::riscv::OPCODE::G_STRICT_FDIV)
  .value("G_STRICT_FREM", LIEF::assembly::riscv::OPCODE::G_STRICT_FREM)
  .value("G_STRICT_FMA", LIEF::assembly::riscv::OPCODE::G_STRICT_FMA)
  .value("G_STRICT_FSQRT", LIEF::assembly::riscv::OPCODE::G_STRICT_FSQRT)
  .value("G_STRICT_FLDEXP", LIEF::assembly::riscv::OPCODE::G_STRICT_FLDEXP)
  .value("G_READ_REGISTER", LIEF::assembly::riscv::OPCODE::G_READ_REGISTER)
  .value("G_WRITE_REGISTER", LIEF::assembly::riscv::OPCODE::G_WRITE_REGISTER)
  .value("G_MEMCPY", LIEF::assembly::riscv::OPCODE::G_MEMCPY)
  .value("G_MEMCPY_INLINE", LIEF::assembly::riscv::OPCODE::G_MEMCPY_INLINE)
  .value("G_MEMMOVE", LIEF::assembly::riscv::OPCODE::G_MEMMOVE)
  .value("G_MEMSET", LIEF::assembly::riscv::OPCODE::G_MEMSET)
  .value("G_BZERO", LIEF::assembly::riscv::OPCODE::G_BZERO)
  .value("G_TRAP", LIEF::assembly::riscv::OPCODE::G_TRAP)
  .value("G_DEBUGTRAP", LIEF::assembly::riscv::OPCODE::G_DEBUGTRAP)
  .value("G_UBSANTRAP", LIEF::assembly::riscv::OPCODE::G_UBSANTRAP)
  .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FADD)
  .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FMUL)
  .value("G_VECREDUCE_FADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FADD)
  .value("G_VECREDUCE_FMUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMUL)
  .value("G_VECREDUCE_FMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAX)
  .value("G_VECREDUCE_FMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMIN)
  .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAXIMUM)
  .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMINIMUM)
  .value("G_VECREDUCE_ADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_ADD)
  .value("G_VECREDUCE_MUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_MUL)
  .value("G_VECREDUCE_AND", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_AND)
  .value("G_VECREDUCE_OR", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_OR)
  .value("G_VECREDUCE_XOR", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_XOR)
  .value("G_VECREDUCE_SMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMAX)
  .value("G_VECREDUCE_SMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMIN)
  .value("G_VECREDUCE_UMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMAX)
  .value("G_VECREDUCE_UMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMIN)
  .value("G_SBFX", LIEF::assembly::riscv::OPCODE::G_SBFX)
  .value("G_UBFX", LIEF::assembly::riscv::OPCODE::G_UBFX)
  .value("ADJCALLSTACKDOWN", LIEF::assembly::riscv::OPCODE::ADJCALLSTACKDOWN)
  .value("ADJCALLSTACKUP", LIEF::assembly::riscv::OPCODE::ADJCALLSTACKUP)
  .value("BuildPairF64Pseudo", LIEF::assembly::riscv::OPCODE::BuildPairF64Pseudo)
  .value("G_FCLASS", LIEF::assembly::riscv::OPCODE::G_FCLASS)
  .value("G_READ_VLENB", LIEF::assembly::riscv::OPCODE::G_READ_VLENB);
  opcodes.value("G_SPLAT_VECTOR_SPLIT_I64_VL", LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR_SPLIT_I64_VL)
  .value("G_VMCLR_VL", LIEF::assembly::riscv::OPCODE::G_VMCLR_VL)
  .value("G_VMSET_VL", LIEF::assembly::riscv::OPCODE::G_VMSET_VL)
  .value("HWASAN_CHECK_MEMACCESS_SHORTGRANULES", LIEF::assembly::riscv::OPCODE::HWASAN_CHECK_MEMACCESS_SHORTGRANULES)
  .value("KCFI_CHECK", LIEF::assembly::riscv::OPCODE::KCFI_CHECK)
  .value("PseudoAddTPRel", LIEF::assembly::riscv::OPCODE::PseudoAddTPRel)
  .value("PseudoAtomicLoadNand32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand32)
  .value("PseudoAtomicLoadNand64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand64)
  .value("PseudoBR", LIEF::assembly::riscv::OPCODE::PseudoBR)
  .value("PseudoBRIND", LIEF::assembly::riscv::OPCODE::PseudoBRIND)
  .value("PseudoBRINDNonX7", LIEF::assembly::riscv::OPCODE::PseudoBRINDNonX7)
  .value("PseudoBRINDX7", LIEF::assembly::riscv::OPCODE::PseudoBRINDX7)
  .value("PseudoCALL", LIEF::assembly::riscv::OPCODE::PseudoCALL)
  .value("PseudoCALLIndirect", LIEF::assembly::riscv::OPCODE::PseudoCALLIndirect)
  .value("PseudoCALLIndirectNonX7", LIEF::assembly::riscv::OPCODE::PseudoCALLIndirectNonX7)
  .value("PseudoCALLReg", LIEF::assembly::riscv::OPCODE::PseudoCALLReg)
  .value("PseudoCCADD", LIEF::assembly::riscv::OPCODE::PseudoCCADD)
  .value("PseudoCCADDI", LIEF::assembly::riscv::OPCODE::PseudoCCADDI)
  .value("PseudoCCADDIW", LIEF::assembly::riscv::OPCODE::PseudoCCADDIW)
  .value("PseudoCCADDW", LIEF::assembly::riscv::OPCODE::PseudoCCADDW)
  .value("PseudoCCAND", LIEF::assembly::riscv::OPCODE::PseudoCCAND)
  .value("PseudoCCANDI", LIEF::assembly::riscv::OPCODE::PseudoCCANDI)
  .value("PseudoCCANDN", LIEF::assembly::riscv::OPCODE::PseudoCCANDN)
  .value("PseudoCCMOVGPR", LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPR)
  .value("PseudoCCMOVGPRNoX0", LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPRNoX0)
  .value("PseudoCCOR", LIEF::assembly::riscv::OPCODE::PseudoCCOR)
  .value("PseudoCCORI", LIEF::assembly::riscv::OPCODE::PseudoCCORI)
  .value("PseudoCCORN", LIEF::assembly::riscv::OPCODE::PseudoCCORN)
  .value("PseudoCCSLL", LIEF::assembly::riscv::OPCODE::PseudoCCSLL)
  .value("PseudoCCSLLI", LIEF::assembly::riscv::OPCODE::PseudoCCSLLI)
  .value("PseudoCCSLLIW", LIEF::assembly::riscv::OPCODE::PseudoCCSLLIW)
  .value("PseudoCCSLLW", LIEF::assembly::riscv::OPCODE::PseudoCCSLLW)
  .value("PseudoCCSRA", LIEF::assembly::riscv::OPCODE::PseudoCCSRA)
  .value("PseudoCCSRAI", LIEF::assembly::riscv::OPCODE::PseudoCCSRAI)
  .value("PseudoCCSRAIW", LIEF::assembly::riscv::OPCODE::PseudoCCSRAIW)
  .value("PseudoCCSRAW", LIEF::assembly::riscv::OPCODE::PseudoCCSRAW)
  .value("PseudoCCSRL", LIEF::assembly::riscv::OPCODE::PseudoCCSRL)
  .value("PseudoCCSRLI", LIEF::assembly::riscv::OPCODE::PseudoCCSRLI)
  .value("PseudoCCSRLIW", LIEF::assembly::riscv::OPCODE::PseudoCCSRLIW)
  .value("PseudoCCSRLW", LIEF::assembly::riscv::OPCODE::PseudoCCSRLW)
  .value("PseudoCCSUB", LIEF::assembly::riscv::OPCODE::PseudoCCSUB)
  .value("PseudoCCSUBW", LIEF::assembly::riscv::OPCODE::PseudoCCSUBW)
  .value("PseudoCCXNOR", LIEF::assembly::riscv::OPCODE::PseudoCCXNOR)
  .value("PseudoCCXOR", LIEF::assembly::riscv::OPCODE::PseudoCCXOR)
  .value("PseudoCCXORI", LIEF::assembly::riscv::OPCODE::PseudoCCXORI)
  .value("PseudoCmpXchg32", LIEF::assembly::riscv::OPCODE::PseudoCmpXchg32)
  .value("PseudoCmpXchg64", LIEF::assembly::riscv::OPCODE::PseudoCmpXchg64)
  .value("PseudoFLD", LIEF::assembly::riscv::OPCODE::PseudoFLD)
  .value("PseudoFLH", LIEF::assembly::riscv::OPCODE::PseudoFLH)
  .value("PseudoFLW", LIEF::assembly::riscv::OPCODE::PseudoFLW)
  .value("PseudoFROUND_D", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D)
  .value("PseudoFROUND_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_IN32X)
  .value("PseudoFROUND_D_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_INX)
  .value("PseudoFROUND_H", LIEF::assembly::riscv::OPCODE::PseudoFROUND_H)
  .value("PseudoFROUND_H_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_H_INX)
  .value("PseudoFROUND_S", LIEF::assembly::riscv::OPCODE::PseudoFROUND_S)
  .value("PseudoFROUND_S_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_S_INX)
  .value("PseudoFSD", LIEF::assembly::riscv::OPCODE::PseudoFSD)
  .value("PseudoFSH", LIEF::assembly::riscv::OPCODE::PseudoFSH)
  .value("PseudoFSW", LIEF::assembly::riscv::OPCODE::PseudoFSW)
  .value("PseudoJump", LIEF::assembly::riscv::OPCODE::PseudoJump)
  .value("PseudoLA", LIEF::assembly::riscv::OPCODE::PseudoLA)
  .value("PseudoLAImm", LIEF::assembly::riscv::OPCODE::PseudoLAImm)
  .value("PseudoLA_TLSDESC", LIEF::assembly::riscv::OPCODE::PseudoLA_TLSDESC)
  .value("PseudoLA_TLS_GD", LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_GD)
  .value("PseudoLA_TLS_IE", LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_IE)
  .value("PseudoLB", LIEF::assembly::riscv::OPCODE::PseudoLB)
  .value("PseudoLBU", LIEF::assembly::riscv::OPCODE::PseudoLBU)
  .value("PseudoLD", LIEF::assembly::riscv::OPCODE::PseudoLD)
  .value("PseudoLGA", LIEF::assembly::riscv::OPCODE::PseudoLGA)
  .value("PseudoLH", LIEF::assembly::riscv::OPCODE::PseudoLH)
  .value("PseudoLHU", LIEF::assembly::riscv::OPCODE::PseudoLHU)
  .value("PseudoLI", LIEF::assembly::riscv::OPCODE::PseudoLI)
  .value("PseudoLLA", LIEF::assembly::riscv::OPCODE::PseudoLLA)
  .value("PseudoLLAImm", LIEF::assembly::riscv::OPCODE::PseudoLLAImm)
  .value("PseudoLW", LIEF::assembly::riscv::OPCODE::PseudoLW)
  .value("PseudoLWU", LIEF::assembly::riscv::OPCODE::PseudoLWU)
  .value("PseudoLongBEQ", LIEF::assembly::riscv::OPCODE::PseudoLongBEQ)
  .value("PseudoLongBGE", LIEF::assembly::riscv::OPCODE::PseudoLongBGE)
  .value("PseudoLongBGEU", LIEF::assembly::riscv::OPCODE::PseudoLongBGEU)
  .value("PseudoLongBLT", LIEF::assembly::riscv::OPCODE::PseudoLongBLT)
  .value("PseudoLongBLTU", LIEF::assembly::riscv::OPCODE::PseudoLongBLTU)
  .value("PseudoLongBNE", LIEF::assembly::riscv::OPCODE::PseudoLongBNE)
  .value("PseudoMaskedAtomicLoadAdd32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadAdd32)
  .value("PseudoMaskedAtomicLoadMax32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMax32)
  .value("PseudoMaskedAtomicLoadMin32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMin32)
  .value("PseudoMaskedAtomicLoadNand32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadNand32)
  .value("PseudoMaskedAtomicLoadSub32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadSub32)
  .value("PseudoMaskedAtomicLoadUMax32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMax32)
  .value("PseudoMaskedAtomicLoadUMin32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMin32)
  .value("PseudoMaskedAtomicSwap32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicSwap32)
  .value("PseudoMaskedCmpXchg32", LIEF::assembly::riscv::OPCODE::PseudoMaskedCmpXchg32)
  .value("PseudoMovAddr", LIEF::assembly::riscv::OPCODE::PseudoMovAddr)
  .value("PseudoMovImm", LIEF::assembly::riscv::OPCODE::PseudoMovImm)
  .value("PseudoQuietFLE_D", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D)
  .value("PseudoQuietFLE_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_IN32X)
  .value("PseudoQuietFLE_D_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_INX)
  .value("PseudoQuietFLE_H", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H)
  .value("PseudoQuietFLE_H_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H_INX)
  .value("PseudoQuietFLE_S", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S)
  .value("PseudoQuietFLE_S_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S_INX)
  .value("PseudoQuietFLT_D", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D)
  .value("PseudoQuietFLT_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_IN32X)
  .value("PseudoQuietFLT_D_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_INX)
  .value("PseudoQuietFLT_H", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H)
  .value("PseudoQuietFLT_H_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H_INX)
  .value("PseudoQuietFLT_S", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S)
  .value("PseudoQuietFLT_S_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S_INX)
  .value("PseudoRET", LIEF::assembly::riscv::OPCODE::PseudoRET)
  .value("PseudoRV32ZdinxLD", LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxLD)
  .value("PseudoRV32ZdinxSD", LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxSD)
  .value("PseudoRVVInitUndefM1", LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM1)
  .value("PseudoRVVInitUndefM2", LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM2)
  .value("PseudoRVVInitUndefM4", LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM4)
  .value("PseudoRVVInitUndefM8", LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM8)
  .value("PseudoReadVL", LIEF::assembly::riscv::OPCODE::PseudoReadVL)
  .value("PseudoReadVLENB", LIEF::assembly::riscv::OPCODE::PseudoReadVLENB)
  .value("PseudoSB", LIEF::assembly::riscv::OPCODE::PseudoSB)
  .value("PseudoSD", LIEF::assembly::riscv::OPCODE::PseudoSD)
  .value("PseudoSEXT_B", LIEF::assembly::riscv::OPCODE::PseudoSEXT_B)
  .value("PseudoSEXT_H", LIEF::assembly::riscv::OPCODE::PseudoSEXT_H)
  .value("PseudoSH", LIEF::assembly::riscv::OPCODE::PseudoSH)
  .value("PseudoSW", LIEF::assembly::riscv::OPCODE::PseudoSW)
  .value("PseudoTAIL", LIEF::assembly::riscv::OPCODE::PseudoTAIL)
  .value("PseudoTAILIndirect", LIEF::assembly::riscv::OPCODE::PseudoTAILIndirect)
  .value("PseudoTAILIndirectNonX7", LIEF::assembly::riscv::OPCODE::PseudoTAILIndirectNonX7)
  .value("PseudoTHVdotVMAQASU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M1)
  .value("PseudoTHVdotVMAQASU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M1_MASK)
  .value("PseudoTHVdotVMAQASU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M2)
  .value("PseudoTHVdotVMAQASU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M2_MASK)
  .value("PseudoTHVdotVMAQASU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M4)
  .value("PseudoTHVdotVMAQASU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M4_MASK)
  .value("PseudoTHVdotVMAQASU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M8)
  .value("PseudoTHVdotVMAQASU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M8_MASK)
  .value("PseudoTHVdotVMAQASU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_MF2)
  .value("PseudoTHVdotVMAQASU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_MF2_MASK)
  .value("PseudoTHVdotVMAQASU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M1)
  .value("PseudoTHVdotVMAQASU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M1_MASK)
  .value("PseudoTHVdotVMAQASU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M2)
  .value("PseudoTHVdotVMAQASU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M2_MASK)
  .value("PseudoTHVdotVMAQASU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M4)
  .value("PseudoTHVdotVMAQASU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M4_MASK)
  .value("PseudoTHVdotVMAQASU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M8)
  .value("PseudoTHVdotVMAQASU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M8_MASK)
  .value("PseudoTHVdotVMAQASU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_MF2)
  .value("PseudoTHVdotVMAQASU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_MF2_MASK)
  .value("PseudoTHVdotVMAQAUS_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M1)
  .value("PseudoTHVdotVMAQAUS_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M1_MASK)
  .value("PseudoTHVdotVMAQAUS_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M2)
  .value("PseudoTHVdotVMAQAUS_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M2_MASK)
  .value("PseudoTHVdotVMAQAUS_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M4)
  .value("PseudoTHVdotVMAQAUS_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M4_MASK)
  .value("PseudoTHVdotVMAQAUS_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M8)
  .value("PseudoTHVdotVMAQAUS_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M8_MASK)
  .value("PseudoTHVdotVMAQAUS_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_MF2)
  .value("PseudoTHVdotVMAQAUS_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_MF2_MASK)
  .value("PseudoTHVdotVMAQAU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M1)
  .value("PseudoTHVdotVMAQAU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M1_MASK)
  .value("PseudoTHVdotVMAQAU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M2)
  .value("PseudoTHVdotVMAQAU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M2_MASK)
  .value("PseudoTHVdotVMAQAU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M4)
  .value("PseudoTHVdotVMAQAU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M4_MASK)
  .value("PseudoTHVdotVMAQAU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M8)
  .value("PseudoTHVdotVMAQAU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M8_MASK)
  .value("PseudoTHVdotVMAQAU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_MF2)
  .value("PseudoTHVdotVMAQAU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_MF2_MASK)
  .value("PseudoTHVdotVMAQAU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M1)
  .value("PseudoTHVdotVMAQAU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M1_MASK)
  .value("PseudoTHVdotVMAQAU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M2)
  .value("PseudoTHVdotVMAQAU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M2_MASK)
  .value("PseudoTHVdotVMAQAU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M4)
  .value("PseudoTHVdotVMAQAU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M4_MASK)
  .value("PseudoTHVdotVMAQAU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M8)
  .value("PseudoTHVdotVMAQAU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M8_MASK)
  .value("PseudoTHVdotVMAQAU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_MF2)
  .value("PseudoTHVdotVMAQAU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_MF2_MASK)
  .value("PseudoTHVdotVMAQA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M1)
  .value("PseudoTHVdotVMAQA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M1_MASK)
  .value("PseudoTHVdotVMAQA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M2)
  .value("PseudoTHVdotVMAQA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M2_MASK)
  .value("PseudoTHVdotVMAQA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M4)
  .value("PseudoTHVdotVMAQA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M4_MASK)
  .value("PseudoTHVdotVMAQA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M8)
  .value("PseudoTHVdotVMAQA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M8_MASK)
  .value("PseudoTHVdotVMAQA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_MF2)
  .value("PseudoTHVdotVMAQA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_MF2_MASK)
  .value("PseudoTHVdotVMAQA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M1)
  .value("PseudoTHVdotVMAQA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M1_MASK)
  .value("PseudoTHVdotVMAQA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M2)
  .value("PseudoTHVdotVMAQA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M2_MASK)
  .value("PseudoTHVdotVMAQA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M4)
  .value("PseudoTHVdotVMAQA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M4_MASK)
  .value("PseudoTHVdotVMAQA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M8)
  .value("PseudoTHVdotVMAQA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M8_MASK)
  .value("PseudoTHVdotVMAQA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_MF2)
  .value("PseudoTHVdotVMAQA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_MF2_MASK)
  .value("PseudoTLSDESCCall", LIEF::assembly::riscv::OPCODE::PseudoTLSDESCCall)
  .value("PseudoVAADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1)
  .value("PseudoVAADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1_MASK)
  .value("PseudoVAADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2)
  .value("PseudoVAADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2_MASK)
  .value("PseudoVAADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4)
  .value("PseudoVAADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4_MASK)
  .value("PseudoVAADDU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8)
  .value("PseudoVAADDU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8_MASK)
  .value("PseudoVAADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2)
  .value("PseudoVAADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2_MASK)
  .value("PseudoVAADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4)
  .value("PseudoVAADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4_MASK)
  .value("PseudoVAADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8)
  .value("PseudoVAADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8_MASK)
  .value("PseudoVAADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1)
  .value("PseudoVAADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1_MASK)
  .value("PseudoVAADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2)
  .value("PseudoVAADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2_MASK)
  .value("PseudoVAADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4)
  .value("PseudoVAADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4_MASK)
  .value("PseudoVAADDU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8)
  .value("PseudoVAADDU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8_MASK)
  .value("PseudoVAADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2)
  .value("PseudoVAADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2_MASK)
  .value("PseudoVAADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4)
  .value("PseudoVAADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4_MASK)
  .value("PseudoVAADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8)
  .value("PseudoVAADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8_MASK)
  .value("PseudoVAADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1)
  .value("PseudoVAADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1_MASK)
  .value("PseudoVAADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2)
  .value("PseudoVAADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2_MASK)
  .value("PseudoVAADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4)
  .value("PseudoVAADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4_MASK)
  .value("PseudoVAADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8)
  .value("PseudoVAADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8_MASK)
  .value("PseudoVAADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2)
  .value("PseudoVAADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2_MASK)
  .value("PseudoVAADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4)
  .value("PseudoVAADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4_MASK)
  .value("PseudoVAADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8)
  .value("PseudoVAADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8_MASK)
  .value("PseudoVAADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1)
  .value("PseudoVAADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1_MASK)
  .value("PseudoVAADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2)
  .value("PseudoVAADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2_MASK)
  .value("PseudoVAADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4)
  .value("PseudoVAADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4_MASK)
  .value("PseudoVAADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8)
  .value("PseudoVAADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8_MASK)
  .value("PseudoVAADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2)
  .value("PseudoVAADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2_MASK)
  .value("PseudoVAADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4)
  .value("PseudoVAADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4_MASK)
  .value("PseudoVAADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8)
  .value("PseudoVAADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8_MASK)
  .value("PseudoVADC_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M1)
  .value("PseudoVADC_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M2)
  .value("PseudoVADC_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M4)
  .value("PseudoVADC_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M8)
  .value("PseudoVADC_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF2)
  .value("PseudoVADC_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF4)
  .value("PseudoVADC_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF8)
  .value("PseudoVADC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M1)
  .value("PseudoVADC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M2)
  .value("PseudoVADC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M4)
  .value("PseudoVADC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M8)
  .value("PseudoVADC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF2)
  .value("PseudoVADC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF4)
  .value("PseudoVADC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF8)
  .value("PseudoVADC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M1)
  .value("PseudoVADC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M2)
  .value("PseudoVADC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M4)
  .value("PseudoVADC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M8)
  .value("PseudoVADC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF2)
  .value("PseudoVADC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF4)
  .value("PseudoVADC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF8)
  .value("PseudoVADD_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1)
  .value("PseudoVADD_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1_MASK)
  .value("PseudoVADD_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2)
  .value("PseudoVADD_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2_MASK)
  .value("PseudoVADD_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4)
  .value("PseudoVADD_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4_MASK)
  .value("PseudoVADD_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8)
  .value("PseudoVADD_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8_MASK)
  .value("PseudoVADD_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2)
  .value("PseudoVADD_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2_MASK)
  .value("PseudoVADD_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4)
  .value("PseudoVADD_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4_MASK)
  .value("PseudoVADD_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8)
  .value("PseudoVADD_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8_MASK)
  .value("PseudoVADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1)
  .value("PseudoVADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1_MASK)
  .value("PseudoVADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2)
  .value("PseudoVADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2_MASK)
  .value("PseudoVADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4)
  .value("PseudoVADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4_MASK)
  .value("PseudoVADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8)
  .value("PseudoVADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8_MASK)
  .value("PseudoVADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2)
  .value("PseudoVADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2_MASK)
  .value("PseudoVADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4)
  .value("PseudoVADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4_MASK);
  opcodes.value("PseudoVADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8)
  .value("PseudoVADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8_MASK)
  .value("PseudoVADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1)
  .value("PseudoVADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1_MASK)
  .value("PseudoVADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2)
  .value("PseudoVADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2_MASK)
  .value("PseudoVADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4)
  .value("PseudoVADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4_MASK)
  .value("PseudoVADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8)
  .value("PseudoVADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8_MASK)
  .value("PseudoVADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2)
  .value("PseudoVADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2_MASK)
  .value("PseudoVADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4)
  .value("PseudoVADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4_MASK)
  .value("PseudoVADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8)
  .value("PseudoVADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8_MASK)
  .value("PseudoVAESDF_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_M1)
  .value("PseudoVAESDF_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF2)
  .value("PseudoVAESDF_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF4)
  .value("PseudoVAESDF_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF8)
  .value("PseudoVAESDF_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M1)
  .value("PseudoVAESDF_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M2)
  .value("PseudoVAESDF_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF2)
  .value("PseudoVAESDF_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF4)
  .value("PseudoVAESDF_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF8)
  .value("PseudoVAESDF_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M1)
  .value("PseudoVAESDF_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M2)
  .value("PseudoVAESDF_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M4)
  .value("PseudoVAESDF_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF2)
  .value("PseudoVAESDF_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF4)
  .value("PseudoVAESDF_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF8)
  .value("PseudoVAESDF_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M1)
  .value("PseudoVAESDF_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M2)
  .value("PseudoVAESDF_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M4)
  .value("PseudoVAESDF_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF2)
  .value("PseudoVAESDF_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF4)
  .value("PseudoVAESDF_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF8)
  .value("PseudoVAESDF_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF2)
  .value("PseudoVAESDF_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF4)
  .value("PseudoVAESDF_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF8)
  .value("PseudoVAESDF_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M1)
  .value("PseudoVAESDF_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M2)
  .value("PseudoVAESDF_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M4)
  .value("PseudoVAESDF_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M8)
  .value("PseudoVAESDF_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_MF2)
  .value("PseudoVAESDM_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_M1)
  .value("PseudoVAESDM_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF2)
  .value("PseudoVAESDM_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF4)
  .value("PseudoVAESDM_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF8)
  .value("PseudoVAESDM_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M1)
  .value("PseudoVAESDM_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M2)
  .value("PseudoVAESDM_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF2)
  .value("PseudoVAESDM_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF4)
  .value("PseudoVAESDM_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF8)
  .value("PseudoVAESDM_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M1)
  .value("PseudoVAESDM_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M2)
  .value("PseudoVAESDM_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M4)
  .value("PseudoVAESDM_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF2)
  .value("PseudoVAESDM_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF4)
  .value("PseudoVAESDM_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF8)
  .value("PseudoVAESDM_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M1)
  .value("PseudoVAESDM_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M2)
  .value("PseudoVAESDM_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M4)
  .value("PseudoVAESDM_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF2)
  .value("PseudoVAESDM_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF4)
  .value("PseudoVAESDM_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF8)
  .value("PseudoVAESDM_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF2)
  .value("PseudoVAESDM_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF4)
  .value("PseudoVAESDM_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF8)
  .value("PseudoVAESDM_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M1)
  .value("PseudoVAESDM_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M2)
  .value("PseudoVAESDM_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M4)
  .value("PseudoVAESDM_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M8)
  .value("PseudoVAESDM_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_MF2)
  .value("PseudoVAESEF_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_M1)
  .value("PseudoVAESEF_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF2)
  .value("PseudoVAESEF_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF4)
  .value("PseudoVAESEF_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF8)
  .value("PseudoVAESEF_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M1)
  .value("PseudoVAESEF_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M2)
  .value("PseudoVAESEF_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF2)
  .value("PseudoVAESEF_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF4)
  .value("PseudoVAESEF_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF8)
  .value("PseudoVAESEF_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M1)
  .value("PseudoVAESEF_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M2)
  .value("PseudoVAESEF_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M4)
  .value("PseudoVAESEF_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF2)
  .value("PseudoVAESEF_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF4)
  .value("PseudoVAESEF_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF8)
  .value("PseudoVAESEF_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M1)
  .value("PseudoVAESEF_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M2)
  .value("PseudoVAESEF_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M4)
  .value("PseudoVAESEF_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF2)
  .value("PseudoVAESEF_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF4)
  .value("PseudoVAESEF_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF8)
  .value("PseudoVAESEF_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF2)
  .value("PseudoVAESEF_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF4)
  .value("PseudoVAESEF_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF8)
  .value("PseudoVAESEF_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M1)
  .value("PseudoVAESEF_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M2)
  .value("PseudoVAESEF_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M4)
  .value("PseudoVAESEF_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M8)
  .value("PseudoVAESEF_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_MF2)
  .value("PseudoVAESEM_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_M1)
  .value("PseudoVAESEM_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF2)
  .value("PseudoVAESEM_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF4)
  .value("PseudoVAESEM_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF8)
  .value("PseudoVAESEM_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M1)
  .value("PseudoVAESEM_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M2)
  .value("PseudoVAESEM_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF2)
  .value("PseudoVAESEM_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF4)
  .value("PseudoVAESEM_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF8)
  .value("PseudoVAESEM_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M1)
  .value("PseudoVAESEM_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M2)
  .value("PseudoVAESEM_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M4)
  .value("PseudoVAESEM_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF2)
  .value("PseudoVAESEM_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF4)
  .value("PseudoVAESEM_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF8)
  .value("PseudoVAESEM_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M1)
  .value("PseudoVAESEM_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M2)
  .value("PseudoVAESEM_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M4)
  .value("PseudoVAESEM_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF2)
  .value("PseudoVAESEM_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF4)
  .value("PseudoVAESEM_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF8)
  .value("PseudoVAESEM_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF2)
  .value("PseudoVAESEM_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF4)
  .value("PseudoVAESEM_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF8)
  .value("PseudoVAESEM_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M1)
  .value("PseudoVAESEM_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M2)
  .value("PseudoVAESEM_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M4)
  .value("PseudoVAESEM_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M8)
  .value("PseudoVAESEM_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_MF2)
  .value("PseudoVAESKF1_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M1)
  .value("PseudoVAESKF1_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M2)
  .value("PseudoVAESKF1_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M4)
  .value("PseudoVAESKF1_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M8)
  .value("PseudoVAESKF1_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_MF2)
  .value("PseudoVAESKF2_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M1)
  .value("PseudoVAESKF2_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M2)
  .value("PseudoVAESKF2_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M4)
  .value("PseudoVAESKF2_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M8)
  .value("PseudoVAESKF2_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_MF2)
  .value("PseudoVAESZ_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_M1)
  .value("PseudoVAESZ_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF2)
  .value("PseudoVAESZ_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF4)
  .value("PseudoVAESZ_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF8)
  .value("PseudoVAESZ_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M1)
  .value("PseudoVAESZ_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M2)
  .value("PseudoVAESZ_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF2)
  .value("PseudoVAESZ_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF4)
  .value("PseudoVAESZ_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF8)
  .value("PseudoVAESZ_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M1)
  .value("PseudoVAESZ_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M2)
  .value("PseudoVAESZ_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M4)
  .value("PseudoVAESZ_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF2)
  .value("PseudoVAESZ_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF4)
  .value("PseudoVAESZ_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF8)
  .value("PseudoVAESZ_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M1)
  .value("PseudoVAESZ_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M2)
  .value("PseudoVAESZ_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M4)
  .value("PseudoVAESZ_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF2)
  .value("PseudoVAESZ_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF4)
  .value("PseudoVAESZ_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF8)
  .value("PseudoVAESZ_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF2)
  .value("PseudoVAESZ_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF4)
  .value("PseudoVAESZ_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF8)
  .value("PseudoVANDN_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1)
  .value("PseudoVANDN_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1_MASK)
  .value("PseudoVANDN_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2)
  .value("PseudoVANDN_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2_MASK)
  .value("PseudoVANDN_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4)
  .value("PseudoVANDN_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4_MASK)
  .value("PseudoVANDN_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8)
  .value("PseudoVANDN_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8_MASK)
  .value("PseudoVANDN_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2)
  .value("PseudoVANDN_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2_MASK)
  .value("PseudoVANDN_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4)
  .value("PseudoVANDN_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4_MASK)
  .value("PseudoVANDN_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8)
  .value("PseudoVANDN_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8_MASK)
  .value("PseudoVANDN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1)
  .value("PseudoVANDN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1_MASK)
  .value("PseudoVANDN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2)
  .value("PseudoVANDN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2_MASK)
  .value("PseudoVANDN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4)
  .value("PseudoVANDN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4_MASK)
  .value("PseudoVANDN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8)
  .value("PseudoVANDN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8_MASK)
  .value("PseudoVANDN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2)
  .value("PseudoVANDN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2_MASK)
  .value("PseudoVANDN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4)
  .value("PseudoVANDN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4_MASK)
  .value("PseudoVANDN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8)
  .value("PseudoVANDN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8_MASK)
  .value("PseudoVAND_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1)
  .value("PseudoVAND_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1_MASK)
  .value("PseudoVAND_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2)
  .value("PseudoVAND_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2_MASK)
  .value("PseudoVAND_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4)
  .value("PseudoVAND_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4_MASK)
  .value("PseudoVAND_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8)
  .value("PseudoVAND_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8_MASK)
  .value("PseudoVAND_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2)
  .value("PseudoVAND_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2_MASK)
  .value("PseudoVAND_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4)
  .value("PseudoVAND_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4_MASK)
  .value("PseudoVAND_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8)
  .value("PseudoVAND_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8_MASK)
  .value("PseudoVAND_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1)
  .value("PseudoVAND_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1_MASK)
  .value("PseudoVAND_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2)
  .value("PseudoVAND_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2_MASK)
  .value("PseudoVAND_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4)
  .value("PseudoVAND_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4_MASK)
  .value("PseudoVAND_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8)
  .value("PseudoVAND_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8_MASK)
  .value("PseudoVAND_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2)
  .value("PseudoVAND_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2_MASK)
  .value("PseudoVAND_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4)
  .value("PseudoVAND_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4_MASK)
  .value("PseudoVAND_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8)
  .value("PseudoVAND_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8_MASK)
  .value("PseudoVAND_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1)
  .value("PseudoVAND_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1_MASK)
  .value("PseudoVAND_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2)
  .value("PseudoVAND_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2_MASK)
  .value("PseudoVAND_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4)
  .value("PseudoVAND_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4_MASK)
  .value("PseudoVAND_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8)
  .value("PseudoVAND_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8_MASK)
  .value("PseudoVAND_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2)
  .value("PseudoVAND_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2_MASK)
  .value("PseudoVAND_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4)
  .value("PseudoVAND_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4_MASK)
  .value("PseudoVAND_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8)
  .value("PseudoVAND_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8_MASK)
  .value("PseudoVASUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1)
  .value("PseudoVASUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1_MASK)
  .value("PseudoVASUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2)
  .value("PseudoVASUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2_MASK)
  .value("PseudoVASUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4)
  .value("PseudoVASUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4_MASK)
  .value("PseudoVASUBU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8)
  .value("PseudoVASUBU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8_MASK)
  .value("PseudoVASUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2)
  .value("PseudoVASUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2_MASK)
  .value("PseudoVASUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4)
  .value("PseudoVASUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4_MASK)
  .value("PseudoVASUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8)
  .value("PseudoVASUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8_MASK)
  .value("PseudoVASUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1)
  .value("PseudoVASUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1_MASK)
  .value("PseudoVASUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2)
  .value("PseudoVASUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2_MASK)
  .value("PseudoVASUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4)
  .value("PseudoVASUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4_MASK)
  .value("PseudoVASUBU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8)
  .value("PseudoVASUBU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8_MASK)
  .value("PseudoVASUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2)
  .value("PseudoVASUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2_MASK)
  .value("PseudoVASUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4)
  .value("PseudoVASUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4_MASK)
  .value("PseudoVASUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8)
  .value("PseudoVASUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8_MASK)
  .value("PseudoVASUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1)
  .value("PseudoVASUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1_MASK)
  .value("PseudoVASUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2)
  .value("PseudoVASUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2_MASK)
  .value("PseudoVASUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4)
  .value("PseudoVASUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4_MASK)
  .value("PseudoVASUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8)
  .value("PseudoVASUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8_MASK)
  .value("PseudoVASUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2)
  .value("PseudoVASUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2_MASK)
  .value("PseudoVASUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4)
  .value("PseudoVASUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4_MASK)
  .value("PseudoVASUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8)
  .value("PseudoVASUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8_MASK)
  .value("PseudoVASUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1)
  .value("PseudoVASUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1_MASK)
  .value("PseudoVASUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2)
  .value("PseudoVASUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2_MASK)
  .value("PseudoVASUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4)
  .value("PseudoVASUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4_MASK)
  .value("PseudoVASUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8)
  .value("PseudoVASUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8_MASK)
  .value("PseudoVASUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2)
  .value("PseudoVASUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2_MASK)
  .value("PseudoVASUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4)
  .value("PseudoVASUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4_MASK)
  .value("PseudoVASUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8)
  .value("PseudoVASUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8_MASK)
  .value("PseudoVBREV8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1)
  .value("PseudoVBREV8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1_MASK)
  .value("PseudoVBREV8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2)
  .value("PseudoVBREV8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2_MASK)
  .value("PseudoVBREV8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4)
  .value("PseudoVBREV8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4_MASK)
  .value("PseudoVBREV8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8)
  .value("PseudoVBREV8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8_MASK);
  opcodes.value("PseudoVBREV8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2)
  .value("PseudoVBREV8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2_MASK)
  .value("PseudoVBREV8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4)
  .value("PseudoVBREV8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4_MASK)
  .value("PseudoVBREV8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8)
  .value("PseudoVBREV8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8_MASK)
  .value("PseudoVBREV_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1)
  .value("PseudoVBREV_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1_MASK)
  .value("PseudoVBREV_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2)
  .value("PseudoVBREV_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2_MASK)
  .value("PseudoVBREV_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4)
  .value("PseudoVBREV_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4_MASK)
  .value("PseudoVBREV_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8)
  .value("PseudoVBREV_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8_MASK)
  .value("PseudoVBREV_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2)
  .value("PseudoVBREV_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2_MASK)
  .value("PseudoVBREV_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4)
  .value("PseudoVBREV_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4_MASK)
  .value("PseudoVBREV_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8)
  .value("PseudoVBREV_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8_MASK)
  .value("PseudoVCLMULH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1)
  .value("PseudoVCLMULH_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1_MASK)
  .value("PseudoVCLMULH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2)
  .value("PseudoVCLMULH_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2_MASK)
  .value("PseudoVCLMULH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4)
  .value("PseudoVCLMULH_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4_MASK)
  .value("PseudoVCLMULH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8)
  .value("PseudoVCLMULH_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8_MASK)
  .value("PseudoVCLMULH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2)
  .value("PseudoVCLMULH_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2_MASK)
  .value("PseudoVCLMULH_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4)
  .value("PseudoVCLMULH_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4_MASK)
  .value("PseudoVCLMULH_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8)
  .value("PseudoVCLMULH_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8_MASK)
  .value("PseudoVCLMULH_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1)
  .value("PseudoVCLMULH_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1_MASK)
  .value("PseudoVCLMULH_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2)
  .value("PseudoVCLMULH_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2_MASK)
  .value("PseudoVCLMULH_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4)
  .value("PseudoVCLMULH_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4_MASK)
  .value("PseudoVCLMULH_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8)
  .value("PseudoVCLMULH_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8_MASK)
  .value("PseudoVCLMULH_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2)
  .value("PseudoVCLMULH_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2_MASK)
  .value("PseudoVCLMULH_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4)
  .value("PseudoVCLMULH_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4_MASK)
  .value("PseudoVCLMULH_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8)
  .value("PseudoVCLMULH_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8_MASK)
  .value("PseudoVCLMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1)
  .value("PseudoVCLMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1_MASK)
  .value("PseudoVCLMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2)
  .value("PseudoVCLMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2_MASK)
  .value("PseudoVCLMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4)
  .value("PseudoVCLMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4_MASK)
  .value("PseudoVCLMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8)
  .value("PseudoVCLMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8_MASK)
  .value("PseudoVCLMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2)
  .value("PseudoVCLMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2_MASK)
  .value("PseudoVCLMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4)
  .value("PseudoVCLMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4_MASK)
  .value("PseudoVCLMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8)
  .value("PseudoVCLMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8_MASK)
  .value("PseudoVCLMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1)
  .value("PseudoVCLMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1_MASK)
  .value("PseudoVCLMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2)
  .value("PseudoVCLMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2_MASK)
  .value("PseudoVCLMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4)
  .value("PseudoVCLMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4_MASK)
  .value("PseudoVCLMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8)
  .value("PseudoVCLMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8_MASK)
  .value("PseudoVCLMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2)
  .value("PseudoVCLMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2_MASK)
  .value("PseudoVCLMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4)
  .value("PseudoVCLMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4_MASK)
  .value("PseudoVCLMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8)
  .value("PseudoVCLMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8_MASK)
  .value("PseudoVCLZ_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1)
  .value("PseudoVCLZ_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1_MASK)
  .value("PseudoVCLZ_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2)
  .value("PseudoVCLZ_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2_MASK)
  .value("PseudoVCLZ_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4)
  .value("PseudoVCLZ_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4_MASK)
  .value("PseudoVCLZ_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8)
  .value("PseudoVCLZ_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8_MASK)
  .value("PseudoVCLZ_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2)
  .value("PseudoVCLZ_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2_MASK)
  .value("PseudoVCLZ_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4)
  .value("PseudoVCLZ_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4_MASK)
  .value("PseudoVCLZ_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8)
  .value("PseudoVCLZ_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8_MASK)
  .value("PseudoVCOMPRESS_VM_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E16)
  .value("PseudoVCOMPRESS_VM_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E32)
  .value("PseudoVCOMPRESS_VM_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E64)
  .value("PseudoVCOMPRESS_VM_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E8)
  .value("PseudoVCOMPRESS_VM_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E16)
  .value("PseudoVCOMPRESS_VM_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E32)
  .value("PseudoVCOMPRESS_VM_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E64)
  .value("PseudoVCOMPRESS_VM_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E8)
  .value("PseudoVCOMPRESS_VM_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E16)
  .value("PseudoVCOMPRESS_VM_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E32)
  .value("PseudoVCOMPRESS_VM_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E64)
  .value("PseudoVCOMPRESS_VM_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E8)
  .value("PseudoVCOMPRESS_VM_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E16)
  .value("PseudoVCOMPRESS_VM_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E32)
  .value("PseudoVCOMPRESS_VM_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E64)
  .value("PseudoVCOMPRESS_VM_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E8)
  .value("PseudoVCOMPRESS_VM_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E16)
  .value("PseudoVCOMPRESS_VM_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E32)
  .value("PseudoVCOMPRESS_VM_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E8)
  .value("PseudoVCOMPRESS_VM_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E16)
  .value("PseudoVCOMPRESS_VM_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E8)
  .value("PseudoVCOMPRESS_VM_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF8_E8)
  .value("PseudoVCPOP_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1)
  .value("PseudoVCPOP_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16)
  .value("PseudoVCPOP_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16_MASK)
  .value("PseudoVCPOP_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1_MASK)
  .value("PseudoVCPOP_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2)
  .value("PseudoVCPOP_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2_MASK)
  .value("PseudoVCPOP_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32)
  .value("PseudoVCPOP_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32_MASK)
  .value("PseudoVCPOP_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4)
  .value("PseudoVCPOP_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4_MASK)
  .value("PseudoVCPOP_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64)
  .value("PseudoVCPOP_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64_MASK)
  .value("PseudoVCPOP_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8)
  .value("PseudoVCPOP_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8_MASK)
  .value("PseudoVCPOP_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1)
  .value("PseudoVCPOP_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1_MASK)
  .value("PseudoVCPOP_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2)
  .value("PseudoVCPOP_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2_MASK)
  .value("PseudoVCPOP_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4)
  .value("PseudoVCPOP_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4_MASK)
  .value("PseudoVCPOP_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8)
  .value("PseudoVCPOP_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8_MASK)
  .value("PseudoVCPOP_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2)
  .value("PseudoVCPOP_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2_MASK)
  .value("PseudoVCPOP_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4)
  .value("PseudoVCPOP_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4_MASK)
  .value("PseudoVCPOP_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8)
  .value("PseudoVCPOP_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8_MASK)
  .value("PseudoVCTZ_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1)
  .value("PseudoVCTZ_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1_MASK)
  .value("PseudoVCTZ_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2)
  .value("PseudoVCTZ_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2_MASK)
  .value("PseudoVCTZ_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4)
  .value("PseudoVCTZ_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4_MASK)
  .value("PseudoVCTZ_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8)
  .value("PseudoVCTZ_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8_MASK)
  .value("PseudoVCTZ_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2)
  .value("PseudoVCTZ_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2_MASK)
  .value("PseudoVCTZ_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4)
  .value("PseudoVCTZ_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4_MASK)
  .value("PseudoVCTZ_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8)
  .value("PseudoVCTZ_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8_MASK)
  .value("PseudoVC_FPR16VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M1)
  .value("PseudoVC_FPR16VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M2)
  .value("PseudoVC_FPR16VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M4)
  .value("PseudoVC_FPR16VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M8)
  .value("PseudoVC_FPR16VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_MF2)
  .value("PseudoVC_FPR16VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_MF4)
  .value("PseudoVC_FPR16VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M1)
  .value("PseudoVC_FPR16VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M2)
  .value("PseudoVC_FPR16VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M4)
  .value("PseudoVC_FPR16VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M8)
  .value("PseudoVC_FPR16VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_MF2)
  .value("PseudoVC_FPR16VW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_MF4)
  .value("PseudoVC_FPR16V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M1)
  .value("PseudoVC_FPR16V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M2)
  .value("PseudoVC_FPR16V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M4)
  .value("PseudoVC_FPR16V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M8)
  .value("PseudoVC_FPR16V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_MF2)
  .value("PseudoVC_FPR16V_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_MF4)
  .value("PseudoVC_FPR32VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M1)
  .value("PseudoVC_FPR32VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M2)
  .value("PseudoVC_FPR32VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M4)
  .value("PseudoVC_FPR32VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M8)
  .value("PseudoVC_FPR32VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_MF2)
  .value("PseudoVC_FPR32VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M1)
  .value("PseudoVC_FPR32VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M2)
  .value("PseudoVC_FPR32VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M4)
  .value("PseudoVC_FPR32VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M8)
  .value("PseudoVC_FPR32VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_MF2)
  .value("PseudoVC_FPR32V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M1)
  .value("PseudoVC_FPR32V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M2)
  .value("PseudoVC_FPR32V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M4)
  .value("PseudoVC_FPR32V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M8)
  .value("PseudoVC_FPR32V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_MF2)
  .value("PseudoVC_FPR64VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M1)
  .value("PseudoVC_FPR64VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M2)
  .value("PseudoVC_FPR64VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M4)
  .value("PseudoVC_FPR64VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M8)
  .value("PseudoVC_FPR64V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M1)
  .value("PseudoVC_FPR64V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M2)
  .value("PseudoVC_FPR64V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M4)
  .value("PseudoVC_FPR64V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M8)
  .value("PseudoVC_IVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M1)
  .value("PseudoVC_IVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M2)
  .value("PseudoVC_IVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M4)
  .value("PseudoVC_IVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M8)
  .value("PseudoVC_IVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF2)
  .value("PseudoVC_IVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF4)
  .value("PseudoVC_IVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF8)
  .value("PseudoVC_IVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M1)
  .value("PseudoVC_IVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M2)
  .value("PseudoVC_IVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M4)
  .value("PseudoVC_IVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF2)
  .value("PseudoVC_IVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF4)
  .value("PseudoVC_IVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF8)
  .value("PseudoVC_IV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M1)
  .value("PseudoVC_IV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M2)
  .value("PseudoVC_IV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M4)
  .value("PseudoVC_IV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M8)
  .value("PseudoVC_IV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF2)
  .value("PseudoVC_IV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF4)
  .value("PseudoVC_IV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF8)
  .value("PseudoVC_I_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M1)
  .value("PseudoVC_I_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M2)
  .value("PseudoVC_I_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M4)
  .value("PseudoVC_I_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M8)
  .value("PseudoVC_I_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF2)
  .value("PseudoVC_I_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF4)
  .value("PseudoVC_I_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF8)
  .value("PseudoVC_VVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M1)
  .value("PseudoVC_VVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M2)
  .value("PseudoVC_VVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M4)
  .value("PseudoVC_VVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M8)
  .value("PseudoVC_VVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF2)
  .value("PseudoVC_VVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF4)
  .value("PseudoVC_VVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF8)
  .value("PseudoVC_VVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M1)
  .value("PseudoVC_VVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M2)
  .value("PseudoVC_VVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M4)
  .value("PseudoVC_VVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF2)
  .value("PseudoVC_VVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF4)
  .value("PseudoVC_VVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF8)
  .value("PseudoVC_VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M1)
  .value("PseudoVC_VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M2)
  .value("PseudoVC_VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M4)
  .value("PseudoVC_VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M8)
  .value("PseudoVC_VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF2)
  .value("PseudoVC_VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF4)
  .value("PseudoVC_VV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF8)
  .value("PseudoVC_V_FPR16VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M1)
  .value("PseudoVC_V_FPR16VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M2)
  .value("PseudoVC_V_FPR16VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M4)
  .value("PseudoVC_V_FPR16VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M8)
  .value("PseudoVC_V_FPR16VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_MF2)
  .value("PseudoVC_V_FPR16VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_MF4)
  .value("PseudoVC_V_FPR16VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M1)
  .value("PseudoVC_V_FPR16VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M2)
  .value("PseudoVC_V_FPR16VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M4)
  .value("PseudoVC_V_FPR16VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M8)
  .value("PseudoVC_V_FPR16VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_MF2)
  .value("PseudoVC_V_FPR16VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_MF4)
  .value("PseudoVC_V_FPR16VW_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M1)
  .value("PseudoVC_V_FPR16VW_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M2)
  .value("PseudoVC_V_FPR16VW_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M4)
  .value("PseudoVC_V_FPR16VW_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M8)
  .value("PseudoVC_V_FPR16VW_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_MF2)
  .value("PseudoVC_V_FPR16VW_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_MF4)
  .value("PseudoVC_V_FPR16VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M1)
  .value("PseudoVC_V_FPR16VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M2)
  .value("PseudoVC_V_FPR16VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M4)
  .value("PseudoVC_V_FPR16VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M8)
  .value("PseudoVC_V_FPR16VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_MF2)
  .value("PseudoVC_V_FPR16VW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_MF4)
  .value("PseudoVC_V_FPR16V_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M1)
  .value("PseudoVC_V_FPR16V_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M2)
  .value("PseudoVC_V_FPR16V_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M4)
  .value("PseudoVC_V_FPR16V_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M8)
  .value("PseudoVC_V_FPR16V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_MF2)
  .value("PseudoVC_V_FPR16V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_MF4)
  .value("PseudoVC_V_FPR16V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M1)
  .value("PseudoVC_V_FPR16V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M2)
  .value("PseudoVC_V_FPR16V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M4)
  .value("PseudoVC_V_FPR16V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M8)
  .value("PseudoVC_V_FPR16V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_MF2)
  .value("PseudoVC_V_FPR16V_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_MF4)
  .value("PseudoVC_V_FPR32VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M1)
  .value("PseudoVC_V_FPR32VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M2)
  .value("PseudoVC_V_FPR32VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M4)
  .value("PseudoVC_V_FPR32VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M8)
  .value("PseudoVC_V_FPR32VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_MF2)
  .value("PseudoVC_V_FPR32VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M1)
  .value("PseudoVC_V_FPR32VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M2)
  .value("PseudoVC_V_FPR32VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M4)
  .value("PseudoVC_V_FPR32VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M8)
  .value("PseudoVC_V_FPR32VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_MF2)
  .value("PseudoVC_V_FPR32VW_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M1)
  .value("PseudoVC_V_FPR32VW_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M2)
  .value("PseudoVC_V_FPR32VW_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M4)
  .value("PseudoVC_V_FPR32VW_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M8)
  .value("PseudoVC_V_FPR32VW_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_MF2)
  .value("PseudoVC_V_FPR32VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M1)
  .value("PseudoVC_V_FPR32VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M2)
  .value("PseudoVC_V_FPR32VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M4)
  .value("PseudoVC_V_FPR32VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M8)
  .value("PseudoVC_V_FPR32VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_MF2)
  .value("PseudoVC_V_FPR32V_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M1)
  .value("PseudoVC_V_FPR32V_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M2);
  opcodes.value("PseudoVC_V_FPR32V_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M4)
  .value("PseudoVC_V_FPR32V_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M8)
  .value("PseudoVC_V_FPR32V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_MF2)
  .value("PseudoVC_V_FPR32V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M1)
  .value("PseudoVC_V_FPR32V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M2)
  .value("PseudoVC_V_FPR32V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M4)
  .value("PseudoVC_V_FPR32V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M8)
  .value("PseudoVC_V_FPR32V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_MF2)
  .value("PseudoVC_V_FPR64VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M1)
  .value("PseudoVC_V_FPR64VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M2)
  .value("PseudoVC_V_FPR64VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M4)
  .value("PseudoVC_V_FPR64VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M8)
  .value("PseudoVC_V_FPR64VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M1)
  .value("PseudoVC_V_FPR64VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M2)
  .value("PseudoVC_V_FPR64VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M4)
  .value("PseudoVC_V_FPR64VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M8)
  .value("PseudoVC_V_FPR64V_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M1)
  .value("PseudoVC_V_FPR64V_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M2)
  .value("PseudoVC_V_FPR64V_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M4)
  .value("PseudoVC_V_FPR64V_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M8)
  .value("PseudoVC_V_FPR64V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M1)
  .value("PseudoVC_V_FPR64V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M2)
  .value("PseudoVC_V_FPR64V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M4)
  .value("PseudoVC_V_FPR64V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M8)
  .value("PseudoVC_V_IVV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M1)
  .value("PseudoVC_V_IVV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M2)
  .value("PseudoVC_V_IVV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M4)
  .value("PseudoVC_V_IVV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M8)
  .value("PseudoVC_V_IVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF2)
  .value("PseudoVC_V_IVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF4)
  .value("PseudoVC_V_IVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF8)
  .value("PseudoVC_V_IVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M1)
  .value("PseudoVC_V_IVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M2)
  .value("PseudoVC_V_IVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M4)
  .value("PseudoVC_V_IVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M8)
  .value("PseudoVC_V_IVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF2)
  .value("PseudoVC_V_IVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF4)
  .value("PseudoVC_V_IVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF8)
  .value("PseudoVC_V_IVW_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M1)
  .value("PseudoVC_V_IVW_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M2)
  .value("PseudoVC_V_IVW_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M4)
  .value("PseudoVC_V_IVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF2)
  .value("PseudoVC_V_IVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF4)
  .value("PseudoVC_V_IVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF8)
  .value("PseudoVC_V_IVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M1)
  .value("PseudoVC_V_IVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M2)
  .value("PseudoVC_V_IVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M4)
  .value("PseudoVC_V_IVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF2)
  .value("PseudoVC_V_IVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF4)
  .value("PseudoVC_V_IVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF8)
  .value("PseudoVC_V_IV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M1)
  .value("PseudoVC_V_IV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M2)
  .value("PseudoVC_V_IV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M4)
  .value("PseudoVC_V_IV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M8)
  .value("PseudoVC_V_IV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF2)
  .value("PseudoVC_V_IV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF4)
  .value("PseudoVC_V_IV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF8)
  .value("PseudoVC_V_IV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M1)
  .value("PseudoVC_V_IV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M2)
  .value("PseudoVC_V_IV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M4)
  .value("PseudoVC_V_IV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M8)
  .value("PseudoVC_V_IV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF2)
  .value("PseudoVC_V_IV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF4)
  .value("PseudoVC_V_IV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF8)
  .value("PseudoVC_V_I_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M1)
  .value("PseudoVC_V_I_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M2)
  .value("PseudoVC_V_I_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M4)
  .value("PseudoVC_V_I_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M8)
  .value("PseudoVC_V_I_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF2)
  .value("PseudoVC_V_I_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF4)
  .value("PseudoVC_V_I_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF8)
  .value("PseudoVC_V_I_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M1)
  .value("PseudoVC_V_I_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M2)
  .value("PseudoVC_V_I_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M4)
  .value("PseudoVC_V_I_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M8)
  .value("PseudoVC_V_I_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF2)
  .value("PseudoVC_V_I_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF4)
  .value("PseudoVC_V_I_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF8)
  .value("PseudoVC_V_VVV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M1)
  .value("PseudoVC_V_VVV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M2)
  .value("PseudoVC_V_VVV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M4)
  .value("PseudoVC_V_VVV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M8)
  .value("PseudoVC_V_VVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF2)
  .value("PseudoVC_V_VVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF4)
  .value("PseudoVC_V_VVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF8)
  .value("PseudoVC_V_VVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M1)
  .value("PseudoVC_V_VVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M2)
  .value("PseudoVC_V_VVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M4)
  .value("PseudoVC_V_VVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M8)
  .value("PseudoVC_V_VVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF2)
  .value("PseudoVC_V_VVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF4)
  .value("PseudoVC_V_VVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF8)
  .value("PseudoVC_V_VVW_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M1)
  .value("PseudoVC_V_VVW_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M2)
  .value("PseudoVC_V_VVW_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M4)
  .value("PseudoVC_V_VVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF2)
  .value("PseudoVC_V_VVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF4)
  .value("PseudoVC_V_VVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF8)
  .value("PseudoVC_V_VVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M1)
  .value("PseudoVC_V_VVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M2)
  .value("PseudoVC_V_VVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M4)
  .value("PseudoVC_V_VVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF2)
  .value("PseudoVC_V_VVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF4)
  .value("PseudoVC_V_VVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF8)
  .value("PseudoVC_V_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M1)
  .value("PseudoVC_V_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M2)
  .value("PseudoVC_V_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M4)
  .value("PseudoVC_V_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M8)
  .value("PseudoVC_V_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF2)
  .value("PseudoVC_V_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF4)
  .value("PseudoVC_V_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF8)
  .value("PseudoVC_V_VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M1)
  .value("PseudoVC_V_VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M2)
  .value("PseudoVC_V_VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M4)
  .value("PseudoVC_V_VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M8)
  .value("PseudoVC_V_VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF2)
  .value("PseudoVC_V_VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF4)
  .value("PseudoVC_V_VV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF8)
  .value("PseudoVC_V_XVV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M1)
  .value("PseudoVC_V_XVV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M2)
  .value("PseudoVC_V_XVV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M4)
  .value("PseudoVC_V_XVV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M8)
  .value("PseudoVC_V_XVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF2)
  .value("PseudoVC_V_XVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF4)
  .value("PseudoVC_V_XVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF8)
  .value("PseudoVC_V_XVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M1)
  .value("PseudoVC_V_XVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M2)
  .value("PseudoVC_V_XVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M4)
  .value("PseudoVC_V_XVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M8)
  .value("PseudoVC_V_XVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF2)
  .value("PseudoVC_V_XVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF4)
  .value("PseudoVC_V_XVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF8)
  .value("PseudoVC_V_XVW_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M1)
  .value("PseudoVC_V_XVW_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M2)
  .value("PseudoVC_V_XVW_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M4)
  .value("PseudoVC_V_XVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF2)
  .value("PseudoVC_V_XVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF4)
  .value("PseudoVC_V_XVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF8)
  .value("PseudoVC_V_XVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M1)
  .value("PseudoVC_V_XVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M2)
  .value("PseudoVC_V_XVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M4)
  .value("PseudoVC_V_XVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF2)
  .value("PseudoVC_V_XVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF4)
  .value("PseudoVC_V_XVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF8)
  .value("PseudoVC_V_XV_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M1)
  .value("PseudoVC_V_XV_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M2)
  .value("PseudoVC_V_XV_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M4)
  .value("PseudoVC_V_XV_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M8)
  .value("PseudoVC_V_XV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF2)
  .value("PseudoVC_V_XV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF4)
  .value("PseudoVC_V_XV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF8)
  .value("PseudoVC_V_XV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M1)
  .value("PseudoVC_V_XV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M2)
  .value("PseudoVC_V_XV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M4)
  .value("PseudoVC_V_XV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M8)
  .value("PseudoVC_V_XV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF2)
  .value("PseudoVC_V_XV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF4)
  .value("PseudoVC_V_XV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF8)
  .value("PseudoVC_V_X_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M1)
  .value("PseudoVC_V_X_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M2)
  .value("PseudoVC_V_X_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M4)
  .value("PseudoVC_V_X_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M8)
  .value("PseudoVC_V_X_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF2)
  .value("PseudoVC_V_X_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF4)
  .value("PseudoVC_V_X_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF8)
  .value("PseudoVC_V_X_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M1)
  .value("PseudoVC_V_X_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M2)
  .value("PseudoVC_V_X_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M4)
  .value("PseudoVC_V_X_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M8)
  .value("PseudoVC_V_X_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF2)
  .value("PseudoVC_V_X_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF4)
  .value("PseudoVC_V_X_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF8)
  .value("PseudoVC_XVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M1)
  .value("PseudoVC_XVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M2)
  .value("PseudoVC_XVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M4)
  .value("PseudoVC_XVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M8)
  .value("PseudoVC_XVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF2)
  .value("PseudoVC_XVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF4)
  .value("PseudoVC_XVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF8)
  .value("PseudoVC_XVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M1)
  .value("PseudoVC_XVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M2)
  .value("PseudoVC_XVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M4)
  .value("PseudoVC_XVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF2)
  .value("PseudoVC_XVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF4)
  .value("PseudoVC_XVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF8)
  .value("PseudoVC_XV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M1)
  .value("PseudoVC_XV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M2)
  .value("PseudoVC_XV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M4)
  .value("PseudoVC_XV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M8)
  .value("PseudoVC_XV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF2)
  .value("PseudoVC_XV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF4)
  .value("PseudoVC_XV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF8)
  .value("PseudoVC_X_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M1)
  .value("PseudoVC_X_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M2)
  .value("PseudoVC_X_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M4)
  .value("PseudoVC_X_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M8)
  .value("PseudoVC_X_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF2)
  .value("PseudoVC_X_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF4)
  .value("PseudoVC_X_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF8)
  .value("PseudoVDIVU_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16)
  .value("PseudoVDIVU_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16_MASK)
  .value("PseudoVDIVU_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32)
  .value("PseudoVDIVU_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32_MASK)
  .value("PseudoVDIVU_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64)
  .value("PseudoVDIVU_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64_MASK)
  .value("PseudoVDIVU_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8)
  .value("PseudoVDIVU_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8_MASK)
  .value("PseudoVDIVU_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16)
  .value("PseudoVDIVU_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16_MASK)
  .value("PseudoVDIVU_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32)
  .value("PseudoVDIVU_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32_MASK)
  .value("PseudoVDIVU_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64)
  .value("PseudoVDIVU_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64_MASK)
  .value("PseudoVDIVU_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8)
  .value("PseudoVDIVU_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8_MASK)
  .value("PseudoVDIVU_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16)
  .value("PseudoVDIVU_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16_MASK)
  .value("PseudoVDIVU_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32)
  .value("PseudoVDIVU_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32_MASK)
  .value("PseudoVDIVU_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64)
  .value("PseudoVDIVU_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64_MASK)
  .value("PseudoVDIVU_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8)
  .value("PseudoVDIVU_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8_MASK)
  .value("PseudoVDIVU_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16)
  .value("PseudoVDIVU_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16_MASK)
  .value("PseudoVDIVU_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32)
  .value("PseudoVDIVU_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32_MASK)
  .value("PseudoVDIVU_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64)
  .value("PseudoVDIVU_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64_MASK)
  .value("PseudoVDIVU_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8)
  .value("PseudoVDIVU_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8_MASK)
  .value("PseudoVDIVU_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16)
  .value("PseudoVDIVU_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16_MASK)
  .value("PseudoVDIVU_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32)
  .value("PseudoVDIVU_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32_MASK)
  .value("PseudoVDIVU_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8)
  .value("PseudoVDIVU_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8_MASK)
  .value("PseudoVDIVU_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16)
  .value("PseudoVDIVU_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16_MASK)
  .value("PseudoVDIVU_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8)
  .value("PseudoVDIVU_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8_MASK)
  .value("PseudoVDIVU_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8)
  .value("PseudoVDIVU_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8_MASK)
  .value("PseudoVDIVU_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16)
  .value("PseudoVDIVU_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16_MASK)
  .value("PseudoVDIVU_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32)
  .value("PseudoVDIVU_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32_MASK)
  .value("PseudoVDIVU_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64)
  .value("PseudoVDIVU_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64_MASK)
  .value("PseudoVDIVU_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8)
  .value("PseudoVDIVU_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8_MASK)
  .value("PseudoVDIVU_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16)
  .value("PseudoVDIVU_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16_MASK)
  .value("PseudoVDIVU_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32)
  .value("PseudoVDIVU_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32_MASK)
  .value("PseudoVDIVU_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64)
  .value("PseudoVDIVU_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64_MASK)
  .value("PseudoVDIVU_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8)
  .value("PseudoVDIVU_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8_MASK)
  .value("PseudoVDIVU_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16)
  .value("PseudoVDIVU_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16_MASK)
  .value("PseudoVDIVU_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32)
  .value("PseudoVDIVU_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32_MASK)
  .value("PseudoVDIVU_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64)
  .value("PseudoVDIVU_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64_MASK)
  .value("PseudoVDIVU_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8)
  .value("PseudoVDIVU_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8_MASK)
  .value("PseudoVDIVU_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16)
  .value("PseudoVDIVU_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16_MASK)
  .value("PseudoVDIVU_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32)
  .value("PseudoVDIVU_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32_MASK)
  .value("PseudoVDIVU_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64)
  .value("PseudoVDIVU_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64_MASK)
  .value("PseudoVDIVU_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8)
  .value("PseudoVDIVU_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8_MASK)
  .value("PseudoVDIVU_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16)
  .value("PseudoVDIVU_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16_MASK)
  .value("PseudoVDIVU_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32)
  .value("PseudoVDIVU_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32_MASK)
  .value("PseudoVDIVU_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8)
  .value("PseudoVDIVU_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8_MASK)
  .value("PseudoVDIVU_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16)
  .value("PseudoVDIVU_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16_MASK)
  .value("PseudoVDIVU_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8)
  .value("PseudoVDIVU_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8_MASK)
  .value("PseudoVDIVU_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8)
  .value("PseudoVDIVU_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8_MASK)
  .value("PseudoVDIV_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16)
  .value("PseudoVDIV_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16_MASK)
  .value("PseudoVDIV_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32)
  .value("PseudoVDIV_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32_MASK)
  .value("PseudoVDIV_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64)
  .value("PseudoVDIV_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64_MASK)
  .value("PseudoVDIV_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8)
  .value("PseudoVDIV_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8_MASK)
  .value("PseudoVDIV_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16)
  .value("PseudoVDIV_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16_MASK)
  .value("PseudoVDIV_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32)
  .value("PseudoVDIV_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32_MASK)
  .value("PseudoVDIV_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64);
  opcodes.value("PseudoVDIV_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64_MASK)
  .value("PseudoVDIV_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8)
  .value("PseudoVDIV_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8_MASK)
  .value("PseudoVDIV_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16)
  .value("PseudoVDIV_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16_MASK)
  .value("PseudoVDIV_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32)
  .value("PseudoVDIV_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32_MASK)
  .value("PseudoVDIV_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64)
  .value("PseudoVDIV_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64_MASK)
  .value("PseudoVDIV_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8)
  .value("PseudoVDIV_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8_MASK)
  .value("PseudoVDIV_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16)
  .value("PseudoVDIV_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16_MASK)
  .value("PseudoVDIV_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32)
  .value("PseudoVDIV_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32_MASK)
  .value("PseudoVDIV_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64)
  .value("PseudoVDIV_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64_MASK)
  .value("PseudoVDIV_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8)
  .value("PseudoVDIV_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8_MASK)
  .value("PseudoVDIV_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16)
  .value("PseudoVDIV_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16_MASK)
  .value("PseudoVDIV_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32)
  .value("PseudoVDIV_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32_MASK)
  .value("PseudoVDIV_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8)
  .value("PseudoVDIV_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8_MASK)
  .value("PseudoVDIV_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16)
  .value("PseudoVDIV_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16_MASK)
  .value("PseudoVDIV_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8)
  .value("PseudoVDIV_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8_MASK)
  .value("PseudoVDIV_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8)
  .value("PseudoVDIV_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8_MASK)
  .value("PseudoVDIV_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16)
  .value("PseudoVDIV_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16_MASK)
  .value("PseudoVDIV_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32)
  .value("PseudoVDIV_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32_MASK)
  .value("PseudoVDIV_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64)
  .value("PseudoVDIV_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64_MASK)
  .value("PseudoVDIV_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8)
  .value("PseudoVDIV_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8_MASK)
  .value("PseudoVDIV_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16)
  .value("PseudoVDIV_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16_MASK)
  .value("PseudoVDIV_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32)
  .value("PseudoVDIV_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32_MASK)
  .value("PseudoVDIV_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64)
  .value("PseudoVDIV_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64_MASK)
  .value("PseudoVDIV_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8)
  .value("PseudoVDIV_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8_MASK)
  .value("PseudoVDIV_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16)
  .value("PseudoVDIV_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16_MASK)
  .value("PseudoVDIV_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32)
  .value("PseudoVDIV_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32_MASK)
  .value("PseudoVDIV_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64)
  .value("PseudoVDIV_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64_MASK)
  .value("PseudoVDIV_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8)
  .value("PseudoVDIV_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8_MASK)
  .value("PseudoVDIV_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16)
  .value("PseudoVDIV_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16_MASK)
  .value("PseudoVDIV_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32)
  .value("PseudoVDIV_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32_MASK)
  .value("PseudoVDIV_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64)
  .value("PseudoVDIV_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64_MASK)
  .value("PseudoVDIV_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8)
  .value("PseudoVDIV_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8_MASK)
  .value("PseudoVDIV_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16)
  .value("PseudoVDIV_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16_MASK)
  .value("PseudoVDIV_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32)
  .value("PseudoVDIV_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32_MASK)
  .value("PseudoVDIV_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8)
  .value("PseudoVDIV_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8_MASK)
  .value("PseudoVDIV_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16)
  .value("PseudoVDIV_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16_MASK)
  .value("PseudoVDIV_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8)
  .value("PseudoVDIV_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8_MASK)
  .value("PseudoVDIV_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8)
  .value("PseudoVDIV_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8_MASK)
  .value("PseudoVFADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16)
  .value("PseudoVFADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16_MASK)
  .value("PseudoVFADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16)
  .value("PseudoVFADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16_MASK)
  .value("PseudoVFADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16)
  .value("PseudoVFADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16_MASK)
  .value("PseudoVFADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16)
  .value("PseudoVFADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16_MASK)
  .value("PseudoVFADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16)
  .value("PseudoVFADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16_MASK)
  .value("PseudoVFADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16)
  .value("PseudoVFADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16_MASK)
  .value("PseudoVFADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32)
  .value("PseudoVFADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32_MASK)
  .value("PseudoVFADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32)
  .value("PseudoVFADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32_MASK)
  .value("PseudoVFADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32)
  .value("PseudoVFADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32_MASK)
  .value("PseudoVFADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32)
  .value("PseudoVFADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32_MASK)
  .value("PseudoVFADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32)
  .value("PseudoVFADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32_MASK)
  .value("PseudoVFADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64)
  .value("PseudoVFADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64_MASK)
  .value("PseudoVFADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64)
  .value("PseudoVFADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64_MASK)
  .value("PseudoVFADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64)
  .value("PseudoVFADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64_MASK)
  .value("PseudoVFADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64)
  .value("PseudoVFADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64_MASK)
  .value("PseudoVFADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16)
  .value("PseudoVFADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16_MASK)
  .value("PseudoVFADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32)
  .value("PseudoVFADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32_MASK)
  .value("PseudoVFADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64)
  .value("PseudoVFADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64_MASK)
  .value("PseudoVFADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16)
  .value("PseudoVFADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16_MASK)
  .value("PseudoVFADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32)
  .value("PseudoVFADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32_MASK)
  .value("PseudoVFADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64)
  .value("PseudoVFADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64_MASK)
  .value("PseudoVFADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16)
  .value("PseudoVFADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16_MASK)
  .value("PseudoVFADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32)
  .value("PseudoVFADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32_MASK)
  .value("PseudoVFADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64)
  .value("PseudoVFADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64_MASK)
  .value("PseudoVFADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16)
  .value("PseudoVFADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16_MASK)
  .value("PseudoVFADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32)
  .value("PseudoVFADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32_MASK)
  .value("PseudoVFADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64)
  .value("PseudoVFADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64_MASK)
  .value("PseudoVFADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16)
  .value("PseudoVFADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16_MASK)
  .value("PseudoVFADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32)
  .value("PseudoVFADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32_MASK)
  .value("PseudoVFADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16)
  .value("PseudoVFADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16_MASK)
  .value("PseudoVFCLASS_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1)
  .value("PseudoVFCLASS_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1_MASK)
  .value("PseudoVFCLASS_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2)
  .value("PseudoVFCLASS_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2_MASK)
  .value("PseudoVFCLASS_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4)
  .value("PseudoVFCLASS_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4_MASK)
  .value("PseudoVFCLASS_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8)
  .value("PseudoVFCLASS_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8_MASK)
  .value("PseudoVFCLASS_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2)
  .value("PseudoVFCLASS_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2_MASK)
  .value("PseudoVFCLASS_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4)
  .value("PseudoVFCLASS_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4_MASK)
  .value("PseudoVFCVT_F_XU_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16)
  .value("PseudoVFCVT_F_XU_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16_MASK)
  .value("PseudoVFCVT_F_XU_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32)
  .value("PseudoVFCVT_F_XU_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32_MASK)
  .value("PseudoVFCVT_F_XU_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64)
  .value("PseudoVFCVT_F_XU_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64_MASK)
  .value("PseudoVFCVT_F_XU_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16)
  .value("PseudoVFCVT_F_XU_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16_MASK)
  .value("PseudoVFCVT_F_XU_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32)
  .value("PseudoVFCVT_F_XU_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32_MASK)
  .value("PseudoVFCVT_F_XU_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64)
  .value("PseudoVFCVT_F_XU_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64_MASK)
  .value("PseudoVFCVT_F_XU_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16)
  .value("PseudoVFCVT_F_XU_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16_MASK)
  .value("PseudoVFCVT_F_XU_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32)
  .value("PseudoVFCVT_F_XU_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32_MASK)
  .value("PseudoVFCVT_F_XU_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64)
  .value("PseudoVFCVT_F_XU_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64_MASK)
  .value("PseudoVFCVT_F_XU_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16)
  .value("PseudoVFCVT_F_XU_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16_MASK)
  .value("PseudoVFCVT_F_XU_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32)
  .value("PseudoVFCVT_F_XU_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32_MASK)
  .value("PseudoVFCVT_F_XU_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64)
  .value("PseudoVFCVT_F_XU_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64_MASK)
  .value("PseudoVFCVT_F_XU_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16)
  .value("PseudoVFCVT_F_XU_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16_MASK)
  .value("PseudoVFCVT_F_XU_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32)
  .value("PseudoVFCVT_F_XU_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32_MASK)
  .value("PseudoVFCVT_F_XU_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16)
  .value("PseudoVFCVT_F_XU_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16_MASK)
  .value("PseudoVFCVT_F_X_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16)
  .value("PseudoVFCVT_F_X_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16_MASK)
  .value("PseudoVFCVT_F_X_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32)
  .value("PseudoVFCVT_F_X_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32_MASK)
  .value("PseudoVFCVT_F_X_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64)
  .value("PseudoVFCVT_F_X_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64_MASK)
  .value("PseudoVFCVT_F_X_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16)
  .value("PseudoVFCVT_F_X_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16_MASK)
  .value("PseudoVFCVT_F_X_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32)
  .value("PseudoVFCVT_F_X_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32_MASK)
  .value("PseudoVFCVT_F_X_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64)
  .value("PseudoVFCVT_F_X_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64_MASK)
  .value("PseudoVFCVT_F_X_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16)
  .value("PseudoVFCVT_F_X_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16_MASK)
  .value("PseudoVFCVT_F_X_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32)
  .value("PseudoVFCVT_F_X_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32_MASK)
  .value("PseudoVFCVT_F_X_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64)
  .value("PseudoVFCVT_F_X_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64_MASK)
  .value("PseudoVFCVT_F_X_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16)
  .value("PseudoVFCVT_F_X_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16_MASK)
  .value("PseudoVFCVT_F_X_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32)
  .value("PseudoVFCVT_F_X_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32_MASK)
  .value("PseudoVFCVT_F_X_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64)
  .value("PseudoVFCVT_F_X_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64_MASK)
  .value("PseudoVFCVT_F_X_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16)
  .value("PseudoVFCVT_F_X_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16_MASK)
  .value("PseudoVFCVT_F_X_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32)
  .value("PseudoVFCVT_F_X_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32_MASK)
  .value("PseudoVFCVT_F_X_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16)
  .value("PseudoVFCVT_F_X_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E16)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E32)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E32_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E64)
  .value("PseudoVFCVT_RM_F_XU_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E64_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E16)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E32)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E32_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E64)
  .value("PseudoVFCVT_RM_F_XU_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E64_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E16)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E32)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E32_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E64)
  .value("PseudoVFCVT_RM_F_XU_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E64_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E16)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E32)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E32_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E64)
  .value("PseudoVFCVT_RM_F_XU_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E64_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E16)
  .value("PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E32)
  .value("PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK)
  .value("PseudoVFCVT_RM_F_XU_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF4_E16)
  .value("PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E16)
  .value("PseudoVFCVT_RM_F_X_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E32)
  .value("PseudoVFCVT_RM_F_X_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E32_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E64)
  .value("PseudoVFCVT_RM_F_X_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E64_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E16)
  .value("PseudoVFCVT_RM_F_X_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E32)
  .value("PseudoVFCVT_RM_F_X_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E32_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E64)
  .value("PseudoVFCVT_RM_F_X_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E64_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E16)
  .value("PseudoVFCVT_RM_F_X_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E32)
  .value("PseudoVFCVT_RM_F_X_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E32_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E64)
  .value("PseudoVFCVT_RM_F_X_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E64_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E16)
  .value("PseudoVFCVT_RM_F_X_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E32)
  .value("PseudoVFCVT_RM_F_X_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E32_MASK)
  .value("PseudoVFCVT_RM_F_X_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E64)
  .value("PseudoVFCVT_RM_F_X_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E64_MASK)
  .value("PseudoVFCVT_RM_F_X_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E16)
  .value("PseudoVFCVT_RM_F_X_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E16_MASK)
  .value("PseudoVFCVT_RM_F_X_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E32)
  .value("PseudoVFCVT_RM_F_X_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E32_MASK)
  .value("PseudoVFCVT_RM_F_X_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF4_E16)
  .value("PseudoVFCVT_RM_F_X_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF4_E16_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M1)
  .value("PseudoVFCVT_RM_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M1_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M2)
  .value("PseudoVFCVT_RM_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M2_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M4)
  .value("PseudoVFCVT_RM_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M4_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M8)
  .value("PseudoVFCVT_RM_XU_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M8_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF2)
  .value("PseudoVFCVT_RM_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF2_MASK)
  .value("PseudoVFCVT_RM_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF4)
  .value("PseudoVFCVT_RM_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF4_MASK)
  .value("PseudoVFCVT_RM_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M1)
  .value("PseudoVFCVT_RM_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M1_MASK)
  .value("PseudoVFCVT_RM_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M2)
  .value("PseudoVFCVT_RM_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M2_MASK)
  .value("PseudoVFCVT_RM_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M4)
  .value("PseudoVFCVT_RM_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M4_MASK)
  .value("PseudoVFCVT_RM_X_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M8)
  .value("PseudoVFCVT_RM_X_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M8_MASK)
  .value("PseudoVFCVT_RM_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF2)
  .value("PseudoVFCVT_RM_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF2_MASK)
  .value("PseudoVFCVT_RM_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF4)
  .value("PseudoVFCVT_RM_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF4_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1)
  .value("PseudoVFCVT_RTZ_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2)
  .value("PseudoVFCVT_RTZ_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4)
  .value("PseudoVFCVT_RTZ_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8)
  .value("PseudoVFCVT_RTZ_XU_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2);
  opcodes.value("PseudoVFCVT_RTZ_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK)
  .value("PseudoVFCVT_RTZ_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4)
  .value("PseudoVFCVT_RTZ_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1)
  .value("PseudoVFCVT_RTZ_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2)
  .value("PseudoVFCVT_RTZ_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4)
  .value("PseudoVFCVT_RTZ_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8)
  .value("PseudoVFCVT_RTZ_X_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2)
  .value("PseudoVFCVT_RTZ_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2_MASK)
  .value("PseudoVFCVT_RTZ_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4)
  .value("PseudoVFCVT_RTZ_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4_MASK)
  .value("PseudoVFCVT_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1)
  .value("PseudoVFCVT_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1_MASK)
  .value("PseudoVFCVT_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2)
  .value("PseudoVFCVT_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2_MASK)
  .value("PseudoVFCVT_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4)
  .value("PseudoVFCVT_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4_MASK)
  .value("PseudoVFCVT_XU_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8)
  .value("PseudoVFCVT_XU_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8_MASK)
  .value("PseudoVFCVT_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2)
  .value("PseudoVFCVT_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2_MASK)
  .value("PseudoVFCVT_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4)
  .value("PseudoVFCVT_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4_MASK)
  .value("PseudoVFCVT_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1)
  .value("PseudoVFCVT_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1_MASK)
  .value("PseudoVFCVT_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2)
  .value("PseudoVFCVT_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2_MASK)
  .value("PseudoVFCVT_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4)
  .value("PseudoVFCVT_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4_MASK)
  .value("PseudoVFCVT_X_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8)
  .value("PseudoVFCVT_X_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8_MASK)
  .value("PseudoVFCVT_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2)
  .value("PseudoVFCVT_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2_MASK)
  .value("PseudoVFCVT_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4)
  .value("PseudoVFCVT_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4_MASK)
  .value("PseudoVFDIV_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16)
  .value("PseudoVFDIV_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16_MASK)
  .value("PseudoVFDIV_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16)
  .value("PseudoVFDIV_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16_MASK)
  .value("PseudoVFDIV_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16)
  .value("PseudoVFDIV_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16_MASK)
  .value("PseudoVFDIV_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16)
  .value("PseudoVFDIV_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16_MASK)
  .value("PseudoVFDIV_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16)
  .value("PseudoVFDIV_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16_MASK)
  .value("PseudoVFDIV_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16)
  .value("PseudoVFDIV_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16_MASK)
  .value("PseudoVFDIV_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32)
  .value("PseudoVFDIV_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32_MASK)
  .value("PseudoVFDIV_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32)
  .value("PseudoVFDIV_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32_MASK)
  .value("PseudoVFDIV_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32)
  .value("PseudoVFDIV_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32_MASK)
  .value("PseudoVFDIV_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32)
  .value("PseudoVFDIV_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32_MASK)
  .value("PseudoVFDIV_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32)
  .value("PseudoVFDIV_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32_MASK)
  .value("PseudoVFDIV_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64)
  .value("PseudoVFDIV_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64_MASK)
  .value("PseudoVFDIV_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64)
  .value("PseudoVFDIV_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64_MASK)
  .value("PseudoVFDIV_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64)
  .value("PseudoVFDIV_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64_MASK)
  .value("PseudoVFDIV_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64)
  .value("PseudoVFDIV_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64_MASK)
  .value("PseudoVFDIV_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16)
  .value("PseudoVFDIV_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16_MASK)
  .value("PseudoVFDIV_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32)
  .value("PseudoVFDIV_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32_MASK)
  .value("PseudoVFDIV_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64)
  .value("PseudoVFDIV_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64_MASK)
  .value("PseudoVFDIV_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16)
  .value("PseudoVFDIV_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16_MASK)
  .value("PseudoVFDIV_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32)
  .value("PseudoVFDIV_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32_MASK)
  .value("PseudoVFDIV_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64)
  .value("PseudoVFDIV_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64_MASK)
  .value("PseudoVFDIV_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16)
  .value("PseudoVFDIV_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16_MASK)
  .value("PseudoVFDIV_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32)
  .value("PseudoVFDIV_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32_MASK)
  .value("PseudoVFDIV_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64)
  .value("PseudoVFDIV_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64_MASK)
  .value("PseudoVFDIV_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16)
  .value("PseudoVFDIV_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16_MASK)
  .value("PseudoVFDIV_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32)
  .value("PseudoVFDIV_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32_MASK)
  .value("PseudoVFDIV_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64)
  .value("PseudoVFDIV_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64_MASK)
  .value("PseudoVFDIV_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16)
  .value("PseudoVFDIV_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16_MASK)
  .value("PseudoVFDIV_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32)
  .value("PseudoVFDIV_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32_MASK)
  .value("PseudoVFDIV_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16)
  .value("PseudoVFDIV_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16_MASK)
  .value("PseudoVFIRST_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1)
  .value("PseudoVFIRST_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16)
  .value("PseudoVFIRST_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16_MASK)
  .value("PseudoVFIRST_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1_MASK)
  .value("PseudoVFIRST_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2)
  .value("PseudoVFIRST_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2_MASK)
  .value("PseudoVFIRST_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32)
  .value("PseudoVFIRST_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32_MASK)
  .value("PseudoVFIRST_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4)
  .value("PseudoVFIRST_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4_MASK)
  .value("PseudoVFIRST_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64)
  .value("PseudoVFIRST_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64_MASK)
  .value("PseudoVFIRST_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8)
  .value("PseudoVFIRST_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8_MASK)
  .value("PseudoVFMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16)
  .value("PseudoVFMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16_MASK)
  .value("PseudoVFMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16)
  .value("PseudoVFMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16_MASK)
  .value("PseudoVFMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16)
  .value("PseudoVFMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16_MASK)
  .value("PseudoVFMACC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16)
  .value("PseudoVFMACC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16_MASK)
  .value("PseudoVFMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16)
  .value("PseudoVFMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16)
  .value("PseudoVFMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32)
  .value("PseudoVFMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32_MASK)
  .value("PseudoVFMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32)
  .value("PseudoVFMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32_MASK)
  .value("PseudoVFMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32)
  .value("PseudoVFMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32_MASK)
  .value("PseudoVFMACC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32)
  .value("PseudoVFMACC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32_MASK)
  .value("PseudoVFMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32)
  .value("PseudoVFMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMACC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64)
  .value("PseudoVFMACC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64_MASK)
  .value("PseudoVFMACC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64)
  .value("PseudoVFMACC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64_MASK)
  .value("PseudoVFMACC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64)
  .value("PseudoVFMACC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64_MASK)
  .value("PseudoVFMACC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64)
  .value("PseudoVFMACC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64_MASK)
  .value("PseudoVFMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16)
  .value("PseudoVFMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16_MASK)
  .value("PseudoVFMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32)
  .value("PseudoVFMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32_MASK)
  .value("PseudoVFMACC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64)
  .value("PseudoVFMACC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64_MASK)
  .value("PseudoVFMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16)
  .value("PseudoVFMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16_MASK)
  .value("PseudoVFMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32)
  .value("PseudoVFMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32_MASK)
  .value("PseudoVFMACC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64)
  .value("PseudoVFMACC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64_MASK)
  .value("PseudoVFMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16)
  .value("PseudoVFMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16_MASK)
  .value("PseudoVFMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32)
  .value("PseudoVFMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32_MASK)
  .value("PseudoVFMACC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64)
  .value("PseudoVFMACC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64_MASK)
  .value("PseudoVFMACC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16)
  .value("PseudoVFMACC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16_MASK)
  .value("PseudoVFMACC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32)
  .value("PseudoVFMACC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32_MASK)
  .value("PseudoVFMACC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64)
  .value("PseudoVFMACC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64_MASK)
  .value("PseudoVFMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16)
  .value("PseudoVFMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16_MASK)
  .value("PseudoVFMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32)
  .value("PseudoVFMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32_MASK)
  .value("PseudoVFMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16)
  .value("PseudoVFMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16_MASK)
  .value("PseudoVFMADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16)
  .value("PseudoVFMADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16_MASK)
  .value("PseudoVFMADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16)
  .value("PseudoVFMADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16_MASK)
  .value("PseudoVFMADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16)
  .value("PseudoVFMADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16_MASK)
  .value("PseudoVFMADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16)
  .value("PseudoVFMADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16_MASK)
  .value("PseudoVFMADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16)
  .value("PseudoVFMADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16)
  .value("PseudoVFMADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32)
  .value("PseudoVFMADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32_MASK)
  .value("PseudoVFMADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32)
  .value("PseudoVFMADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32_MASK)
  .value("PseudoVFMADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32)
  .value("PseudoVFMADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32_MASK)
  .value("PseudoVFMADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32)
  .value("PseudoVFMADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32_MASK)
  .value("PseudoVFMADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32)
  .value("PseudoVFMADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64)
  .value("PseudoVFMADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64_MASK)
  .value("PseudoVFMADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64)
  .value("PseudoVFMADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64_MASK)
  .value("PseudoVFMADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64)
  .value("PseudoVFMADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64_MASK)
  .value("PseudoVFMADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64)
  .value("PseudoVFMADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64_MASK)
  .value("PseudoVFMADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16)
  .value("PseudoVFMADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16_MASK)
  .value("PseudoVFMADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32)
  .value("PseudoVFMADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32_MASK)
  .value("PseudoVFMADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64)
  .value("PseudoVFMADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64_MASK)
  .value("PseudoVFMADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16)
  .value("PseudoVFMADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16_MASK)
  .value("PseudoVFMADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32)
  .value("PseudoVFMADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32_MASK)
  .value("PseudoVFMADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64)
  .value("PseudoVFMADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64_MASK)
  .value("PseudoVFMADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16)
  .value("PseudoVFMADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16_MASK)
  .value("PseudoVFMADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32)
  .value("PseudoVFMADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32_MASK)
  .value("PseudoVFMADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64)
  .value("PseudoVFMADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64_MASK)
  .value("PseudoVFMADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16)
  .value("PseudoVFMADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16_MASK)
  .value("PseudoVFMADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32)
  .value("PseudoVFMADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32_MASK)
  .value("PseudoVFMADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64)
  .value("PseudoVFMADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64_MASK)
  .value("PseudoVFMADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16)
  .value("PseudoVFMADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16_MASK)
  .value("PseudoVFMADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32)
  .value("PseudoVFMADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32_MASK)
  .value("PseudoVFMADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16)
  .value("PseudoVFMADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16_MASK)
  .value("PseudoVFMAX_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16)
  .value("PseudoVFMAX_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16_MASK)
  .value("PseudoVFMAX_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16)
  .value("PseudoVFMAX_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16_MASK)
  .value("PseudoVFMAX_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16)
  .value("PseudoVFMAX_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16_MASK)
  .value("PseudoVFMAX_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16)
  .value("PseudoVFMAX_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16_MASK)
  .value("PseudoVFMAX_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16)
  .value("PseudoVFMAX_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMAX_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16)
  .value("PseudoVFMAX_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMAX_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32)
  .value("PseudoVFMAX_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32_MASK)
  .value("PseudoVFMAX_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32)
  .value("PseudoVFMAX_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32_MASK)
  .value("PseudoVFMAX_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32)
  .value("PseudoVFMAX_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32_MASK)
  .value("PseudoVFMAX_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32)
  .value("PseudoVFMAX_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32_MASK)
  .value("PseudoVFMAX_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32)
  .value("PseudoVFMAX_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMAX_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64)
  .value("PseudoVFMAX_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64_MASK)
  .value("PseudoVFMAX_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64)
  .value("PseudoVFMAX_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64_MASK)
  .value("PseudoVFMAX_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64)
  .value("PseudoVFMAX_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64_MASK)
  .value("PseudoVFMAX_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64)
  .value("PseudoVFMAX_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64_MASK)
  .value("PseudoVFMAX_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16)
  .value("PseudoVFMAX_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16_MASK)
  .value("PseudoVFMAX_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32)
  .value("PseudoVFMAX_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32_MASK)
  .value("PseudoVFMAX_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64)
  .value("PseudoVFMAX_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64_MASK)
  .value("PseudoVFMAX_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16)
  .value("PseudoVFMAX_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16_MASK)
  .value("PseudoVFMAX_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32)
  .value("PseudoVFMAX_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32_MASK)
  .value("PseudoVFMAX_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64)
  .value("PseudoVFMAX_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64_MASK)
  .value("PseudoVFMAX_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16)
  .value("PseudoVFMAX_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16_MASK)
  .value("PseudoVFMAX_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32)
  .value("PseudoVFMAX_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32_MASK)
  .value("PseudoVFMAX_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64)
  .value("PseudoVFMAX_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64_MASK)
  .value("PseudoVFMAX_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16)
  .value("PseudoVFMAX_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16_MASK)
  .value("PseudoVFMAX_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32)
  .value("PseudoVFMAX_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32_MASK)
  .value("PseudoVFMAX_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64)
  .value("PseudoVFMAX_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64_MASK)
  .value("PseudoVFMAX_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16)
  .value("PseudoVFMAX_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16_MASK)
  .value("PseudoVFMAX_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32)
  .value("PseudoVFMAX_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32_MASK)
  .value("PseudoVFMAX_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16)
  .value("PseudoVFMAX_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16_MASK)
  .value("PseudoVFMERGE_VFPR16M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M1)
  .value("PseudoVFMERGE_VFPR16M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M2)
  .value("PseudoVFMERGE_VFPR16M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M4)
  .value("PseudoVFMERGE_VFPR16M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M8)
  .value("PseudoVFMERGE_VFPR16M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF2)
  .value("PseudoVFMERGE_VFPR16M_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF4)
  .value("PseudoVFMERGE_VFPR32M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M1);
  opcodes.value("PseudoVFMERGE_VFPR32M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M2)
  .value("PseudoVFMERGE_VFPR32M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M4)
  .value("PseudoVFMERGE_VFPR32M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M8)
  .value("PseudoVFMERGE_VFPR32M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_MF2)
  .value("PseudoVFMERGE_VFPR64M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M1)
  .value("PseudoVFMERGE_VFPR64M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M2)
  .value("PseudoVFMERGE_VFPR64M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M4)
  .value("PseudoVFMERGE_VFPR64M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M8)
  .value("PseudoVFMIN_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16)
  .value("PseudoVFMIN_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16_MASK)
  .value("PseudoVFMIN_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16)
  .value("PseudoVFMIN_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16_MASK)
  .value("PseudoVFMIN_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16)
  .value("PseudoVFMIN_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16_MASK)
  .value("PseudoVFMIN_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16)
  .value("PseudoVFMIN_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16_MASK)
  .value("PseudoVFMIN_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16)
  .value("PseudoVFMIN_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMIN_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16)
  .value("PseudoVFMIN_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMIN_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32)
  .value("PseudoVFMIN_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32_MASK)
  .value("PseudoVFMIN_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32)
  .value("PseudoVFMIN_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32_MASK)
  .value("PseudoVFMIN_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32)
  .value("PseudoVFMIN_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32_MASK)
  .value("PseudoVFMIN_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32)
  .value("PseudoVFMIN_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32_MASK)
  .value("PseudoVFMIN_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32)
  .value("PseudoVFMIN_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMIN_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64)
  .value("PseudoVFMIN_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64_MASK)
  .value("PseudoVFMIN_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64)
  .value("PseudoVFMIN_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64_MASK)
  .value("PseudoVFMIN_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64)
  .value("PseudoVFMIN_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64_MASK)
  .value("PseudoVFMIN_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64)
  .value("PseudoVFMIN_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64_MASK)
  .value("PseudoVFMIN_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16)
  .value("PseudoVFMIN_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16_MASK)
  .value("PseudoVFMIN_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32)
  .value("PseudoVFMIN_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32_MASK)
  .value("PseudoVFMIN_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64)
  .value("PseudoVFMIN_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64_MASK)
  .value("PseudoVFMIN_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16)
  .value("PseudoVFMIN_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16_MASK)
  .value("PseudoVFMIN_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32)
  .value("PseudoVFMIN_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32_MASK)
  .value("PseudoVFMIN_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64)
  .value("PseudoVFMIN_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64_MASK)
  .value("PseudoVFMIN_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16)
  .value("PseudoVFMIN_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16_MASK)
  .value("PseudoVFMIN_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32)
  .value("PseudoVFMIN_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32_MASK)
  .value("PseudoVFMIN_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64)
  .value("PseudoVFMIN_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64_MASK)
  .value("PseudoVFMIN_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16)
  .value("PseudoVFMIN_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16_MASK)
  .value("PseudoVFMIN_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32)
  .value("PseudoVFMIN_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32_MASK)
  .value("PseudoVFMIN_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64)
  .value("PseudoVFMIN_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64_MASK)
  .value("PseudoVFMIN_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16)
  .value("PseudoVFMIN_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16_MASK)
  .value("PseudoVFMIN_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32)
  .value("PseudoVFMIN_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32_MASK)
  .value("PseudoVFMIN_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16)
  .value("PseudoVFMIN_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16)
  .value("PseudoVFMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16)
  .value("PseudoVFMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16)
  .value("PseudoVFMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16)
  .value("PseudoVFMSAC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16)
  .value("PseudoVFMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16)
  .value("PseudoVFMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32)
  .value("PseudoVFMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32_MASK)
  .value("PseudoVFMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32)
  .value("PseudoVFMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32_MASK)
  .value("PseudoVFMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32)
  .value("PseudoVFMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32_MASK)
  .value("PseudoVFMSAC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32)
  .value("PseudoVFMSAC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32_MASK)
  .value("PseudoVFMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32)
  .value("PseudoVFMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMSAC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64)
  .value("PseudoVFMSAC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64_MASK)
  .value("PseudoVFMSAC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64)
  .value("PseudoVFMSAC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64_MASK)
  .value("PseudoVFMSAC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64)
  .value("PseudoVFMSAC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64_MASK)
  .value("PseudoVFMSAC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64)
  .value("PseudoVFMSAC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64_MASK)
  .value("PseudoVFMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16)
  .value("PseudoVFMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16_MASK)
  .value("PseudoVFMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32)
  .value("PseudoVFMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32_MASK)
  .value("PseudoVFMSAC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64)
  .value("PseudoVFMSAC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64_MASK)
  .value("PseudoVFMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16)
  .value("PseudoVFMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16_MASK)
  .value("PseudoVFMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32)
  .value("PseudoVFMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32_MASK)
  .value("PseudoVFMSAC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64)
  .value("PseudoVFMSAC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64_MASK)
  .value("PseudoVFMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16)
  .value("PseudoVFMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16_MASK)
  .value("PseudoVFMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32)
  .value("PseudoVFMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32_MASK)
  .value("PseudoVFMSAC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64)
  .value("PseudoVFMSAC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64_MASK)
  .value("PseudoVFMSAC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16)
  .value("PseudoVFMSAC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16_MASK)
  .value("PseudoVFMSAC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32)
  .value("PseudoVFMSAC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32_MASK)
  .value("PseudoVFMSAC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64)
  .value("PseudoVFMSAC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64_MASK)
  .value("PseudoVFMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16)
  .value("PseudoVFMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16_MASK)
  .value("PseudoVFMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32)
  .value("PseudoVFMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32_MASK)
  .value("PseudoVFMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16)
  .value("PseudoVFMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16)
  .value("PseudoVFMSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16)
  .value("PseudoVFMSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16)
  .value("PseudoVFMSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16)
  .value("PseudoVFMSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16)
  .value("PseudoVFMSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16)
  .value("PseudoVFMSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32)
  .value("PseudoVFMSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32_MASK)
  .value("PseudoVFMSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32)
  .value("PseudoVFMSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32_MASK)
  .value("PseudoVFMSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32)
  .value("PseudoVFMSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32_MASK)
  .value("PseudoVFMSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32)
  .value("PseudoVFMSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32_MASK)
  .value("PseudoVFMSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32)
  .value("PseudoVFMSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64)
  .value("PseudoVFMSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64_MASK)
  .value("PseudoVFMSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64)
  .value("PseudoVFMSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64_MASK)
  .value("PseudoVFMSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64)
  .value("PseudoVFMSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64_MASK)
  .value("PseudoVFMSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64)
  .value("PseudoVFMSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64_MASK)
  .value("PseudoVFMSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16)
  .value("PseudoVFMSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16_MASK)
  .value("PseudoVFMSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32)
  .value("PseudoVFMSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32_MASK)
  .value("PseudoVFMSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64)
  .value("PseudoVFMSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64_MASK)
  .value("PseudoVFMSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16)
  .value("PseudoVFMSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16_MASK)
  .value("PseudoVFMSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32)
  .value("PseudoVFMSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32_MASK)
  .value("PseudoVFMSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64)
  .value("PseudoVFMSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64_MASK)
  .value("PseudoVFMSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16)
  .value("PseudoVFMSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16_MASK)
  .value("PseudoVFMSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32)
  .value("PseudoVFMSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32_MASK)
  .value("PseudoVFMSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64)
  .value("PseudoVFMSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64_MASK)
  .value("PseudoVFMSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16)
  .value("PseudoVFMSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16_MASK)
  .value("PseudoVFMSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32)
  .value("PseudoVFMSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32_MASK)
  .value("PseudoVFMSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64)
  .value("PseudoVFMSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64_MASK)
  .value("PseudoVFMSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16)
  .value("PseudoVFMSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16_MASK)
  .value("PseudoVFMSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32)
  .value("PseudoVFMSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32_MASK)
  .value("PseudoVFMSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16)
  .value("PseudoVFMSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16_MASK)
  .value("PseudoVFMUL_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16)
  .value("PseudoVFMUL_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16_MASK)
  .value("PseudoVFMUL_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16)
  .value("PseudoVFMUL_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16_MASK)
  .value("PseudoVFMUL_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16)
  .value("PseudoVFMUL_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16_MASK)
  .value("PseudoVFMUL_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16)
  .value("PseudoVFMUL_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16_MASK)
  .value("PseudoVFMUL_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16)
  .value("PseudoVFMUL_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16_MASK)
  .value("PseudoVFMUL_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16)
  .value("PseudoVFMUL_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16_MASK)
  .value("PseudoVFMUL_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32)
  .value("PseudoVFMUL_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32_MASK)
  .value("PseudoVFMUL_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32)
  .value("PseudoVFMUL_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32_MASK)
  .value("PseudoVFMUL_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32)
  .value("PseudoVFMUL_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32_MASK)
  .value("PseudoVFMUL_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32)
  .value("PseudoVFMUL_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32_MASK)
  .value("PseudoVFMUL_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32)
  .value("PseudoVFMUL_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32_MASK)
  .value("PseudoVFMUL_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64)
  .value("PseudoVFMUL_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64_MASK)
  .value("PseudoVFMUL_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64)
  .value("PseudoVFMUL_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64_MASK)
  .value("PseudoVFMUL_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64)
  .value("PseudoVFMUL_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64_MASK)
  .value("PseudoVFMUL_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64)
  .value("PseudoVFMUL_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64_MASK)
  .value("PseudoVFMUL_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16)
  .value("PseudoVFMUL_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16_MASK)
  .value("PseudoVFMUL_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32)
  .value("PseudoVFMUL_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32_MASK)
  .value("PseudoVFMUL_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64)
  .value("PseudoVFMUL_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64_MASK)
  .value("PseudoVFMUL_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16)
  .value("PseudoVFMUL_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16_MASK)
  .value("PseudoVFMUL_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32)
  .value("PseudoVFMUL_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32_MASK)
  .value("PseudoVFMUL_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64)
  .value("PseudoVFMUL_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64_MASK)
  .value("PseudoVFMUL_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16)
  .value("PseudoVFMUL_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16_MASK)
  .value("PseudoVFMUL_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32)
  .value("PseudoVFMUL_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32_MASK)
  .value("PseudoVFMUL_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64)
  .value("PseudoVFMUL_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64_MASK)
  .value("PseudoVFMUL_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16)
  .value("PseudoVFMUL_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16_MASK)
  .value("PseudoVFMUL_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32)
  .value("PseudoVFMUL_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32_MASK)
  .value("PseudoVFMUL_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64)
  .value("PseudoVFMUL_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64_MASK)
  .value("PseudoVFMUL_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16)
  .value("PseudoVFMUL_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16_MASK)
  .value("PseudoVFMUL_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32)
  .value("PseudoVFMUL_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32_MASK)
  .value("PseudoVFMUL_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16)
  .value("PseudoVFMUL_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16_MASK)
  .value("PseudoVFMV_FPR16_S_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M1)
  .value("PseudoVFMV_FPR16_S_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M2)
  .value("PseudoVFMV_FPR16_S_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M4)
  .value("PseudoVFMV_FPR16_S_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M8)
  .value("PseudoVFMV_FPR16_S_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_MF2)
  .value("PseudoVFMV_FPR16_S_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_MF4)
  .value("PseudoVFMV_FPR32_S_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M1)
  .value("PseudoVFMV_FPR32_S_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M2)
  .value("PseudoVFMV_FPR32_S_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M4)
  .value("PseudoVFMV_FPR32_S_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M8)
  .value("PseudoVFMV_FPR32_S_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_MF2)
  .value("PseudoVFMV_FPR64_S_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M1)
  .value("PseudoVFMV_FPR64_S_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M2)
  .value("PseudoVFMV_FPR64_S_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M4)
  .value("PseudoVFMV_FPR64_S_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M8)
  .value("PseudoVFMV_S_FPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M1)
  .value("PseudoVFMV_S_FPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M2)
  .value("PseudoVFMV_S_FPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M4)
  .value("PseudoVFMV_S_FPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M8)
  .value("PseudoVFMV_S_FPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_MF2)
  .value("PseudoVFMV_S_FPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_MF4)
  .value("PseudoVFMV_S_FPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M1)
  .value("PseudoVFMV_S_FPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M2)
  .value("PseudoVFMV_S_FPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M4)
  .value("PseudoVFMV_S_FPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M8)
  .value("PseudoVFMV_S_FPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_MF2)
  .value("PseudoVFMV_S_FPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M1)
  .value("PseudoVFMV_S_FPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M2)
  .value("PseudoVFMV_S_FPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M4)
  .value("PseudoVFMV_S_FPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M8)
  .value("PseudoVFMV_V_FPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M1)
  .value("PseudoVFMV_V_FPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M2)
  .value("PseudoVFMV_V_FPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M4)
  .value("PseudoVFMV_V_FPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M8)
  .value("PseudoVFMV_V_FPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF2)
  .value("PseudoVFMV_V_FPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF4)
  .value("PseudoVFMV_V_FPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M1)
  .value("PseudoVFMV_V_FPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M2)
  .value("PseudoVFMV_V_FPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M4)
  .value("PseudoVFMV_V_FPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M8)
  .value("PseudoVFMV_V_FPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_MF2)
  .value("PseudoVFMV_V_FPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M1)
  .value("PseudoVFMV_V_FPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M2)
  .value("PseudoVFMV_V_FPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M4)
  .value("PseudoVFMV_V_FPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M8)
  .value("PseudoVFNCVTBF16_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16)
  .value("PseudoVFNCVTBF16_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32)
  .value("PseudoVFNCVTBF16_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16)
  .value("PseudoVFNCVTBF16_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32);
  opcodes.value("PseudoVFNCVTBF16_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16)
  .value("PseudoVFNCVTBF16_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32)
  .value("PseudoVFNCVTBF16_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16)
  .value("PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32)
  .value("PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK)
  .value("PseudoVFNCVTBF16_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16)
  .value("PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16)
  .value("PseudoVFNCVT_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16_MASK)
  .value("PseudoVFNCVT_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32)
  .value("PseudoVFNCVT_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32_MASK)
  .value("PseudoVFNCVT_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16)
  .value("PseudoVFNCVT_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16_MASK)
  .value("PseudoVFNCVT_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32)
  .value("PseudoVFNCVT_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32_MASK)
  .value("PseudoVFNCVT_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16)
  .value("PseudoVFNCVT_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16_MASK)
  .value("PseudoVFNCVT_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32)
  .value("PseudoVFNCVT_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32_MASK)
  .value("PseudoVFNCVT_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16)
  .value("PseudoVFNCVT_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32)
  .value("PseudoVFNCVT_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16)
  .value("PseudoVFNCVT_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_F_XU_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16)
  .value("PseudoVFNCVT_F_XU_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16_MASK)
  .value("PseudoVFNCVT_F_XU_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32)
  .value("PseudoVFNCVT_F_XU_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32_MASK)
  .value("PseudoVFNCVT_F_XU_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16)
  .value("PseudoVFNCVT_F_XU_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16_MASK)
  .value("PseudoVFNCVT_F_XU_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32)
  .value("PseudoVFNCVT_F_XU_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32_MASK)
  .value("PseudoVFNCVT_F_XU_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16)
  .value("PseudoVFNCVT_F_XU_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16_MASK)
  .value("PseudoVFNCVT_F_XU_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32)
  .value("PseudoVFNCVT_F_XU_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32_MASK)
  .value("PseudoVFNCVT_F_XU_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16)
  .value("PseudoVFNCVT_F_XU_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_F_XU_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32)
  .value("PseudoVFNCVT_F_XU_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_F_XU_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16)
  .value("PseudoVFNCVT_F_XU_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_F_X_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16)
  .value("PseudoVFNCVT_F_X_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16_MASK)
  .value("PseudoVFNCVT_F_X_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32)
  .value("PseudoVFNCVT_F_X_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32_MASK)
  .value("PseudoVFNCVT_F_X_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16)
  .value("PseudoVFNCVT_F_X_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16_MASK)
  .value("PseudoVFNCVT_F_X_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32)
  .value("PseudoVFNCVT_F_X_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32_MASK)
  .value("PseudoVFNCVT_F_X_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16)
  .value("PseudoVFNCVT_F_X_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16_MASK)
  .value("PseudoVFNCVT_F_X_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32)
  .value("PseudoVFNCVT_F_X_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32_MASK)
  .value("PseudoVFNCVT_F_X_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16)
  .value("PseudoVFNCVT_F_X_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_F_X_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32)
  .value("PseudoVFNCVT_F_X_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_F_X_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16)
  .value("PseudoVFNCVT_F_X_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E16)
  .value("PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E32)
  .value("PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E16)
  .value("PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E32)
  .value("PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E16)
  .value("PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E32)
  .value("PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E16)
  .value("PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E32)
  .value("PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_RM_F_XU_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF4_E16)
  .value("PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E16)
  .value("PseudoVFNCVT_RM_F_X_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E16_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E32)
  .value("PseudoVFNCVT_RM_F_X_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E32_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E16)
  .value("PseudoVFNCVT_RM_F_X_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E16_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E32)
  .value("PseudoVFNCVT_RM_F_X_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E32_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E16)
  .value("PseudoVFNCVT_RM_F_X_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E16_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E32)
  .value("PseudoVFNCVT_RM_F_X_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E32_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E16)
  .value("PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E32)
  .value("PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_RM_F_X_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF4_E16)
  .value("PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M1)
  .value("PseudoVFNCVT_RM_XU_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M1_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M2)
  .value("PseudoVFNCVT_RM_XU_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M2_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M4)
  .value("PseudoVFNCVT_RM_XU_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M4_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF2)
  .value("PseudoVFNCVT_RM_XU_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF2_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF4)
  .value("PseudoVFNCVT_RM_XU_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF4_MASK)
  .value("PseudoVFNCVT_RM_XU_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF8)
  .value("PseudoVFNCVT_RM_XU_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF8_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M1)
  .value("PseudoVFNCVT_RM_X_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M1_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M2)
  .value("PseudoVFNCVT_RM_X_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M2_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M4)
  .value("PseudoVFNCVT_RM_X_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M4_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF2)
  .value("PseudoVFNCVT_RM_X_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF2_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF4)
  .value("PseudoVFNCVT_RM_X_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF4_MASK)
  .value("PseudoVFNCVT_RM_X_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF8)
  .value("PseudoVFNCVT_RM_X_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF8_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16)
  .value("PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32)
  .value("PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16)
  .value("PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32)
  .value("PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16)
  .value("PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32)
  .value("PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16)
  .value("PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32)
  .value("PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK)
  .value("PseudoVFNCVT_ROD_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16)
  .value("PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4)
  .value("PseudoVFNCVT_RTZ_XU_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8)
  .value("PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1)
  .value("PseudoVFNCVT_RTZ_X_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2)
  .value("PseudoVFNCVT_RTZ_X_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4)
  .value("PseudoVFNCVT_RTZ_X_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8)
  .value("PseudoVFNCVT_RTZ_X_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK)
  .value("PseudoVFNCVT_XU_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1)
  .value("PseudoVFNCVT_XU_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1_MASK)
  .value("PseudoVFNCVT_XU_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2)
  .value("PseudoVFNCVT_XU_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2_MASK)
  .value("PseudoVFNCVT_XU_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4)
  .value("PseudoVFNCVT_XU_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4_MASK)
  .value("PseudoVFNCVT_XU_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2)
  .value("PseudoVFNCVT_XU_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2_MASK)
  .value("PseudoVFNCVT_XU_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4)
  .value("PseudoVFNCVT_XU_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4_MASK)
  .value("PseudoVFNCVT_XU_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8)
  .value("PseudoVFNCVT_XU_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8_MASK)
  .value("PseudoVFNCVT_X_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1)
  .value("PseudoVFNCVT_X_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1_MASK)
  .value("PseudoVFNCVT_X_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2)
  .value("PseudoVFNCVT_X_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2_MASK)
  .value("PseudoVFNCVT_X_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4)
  .value("PseudoVFNCVT_X_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4_MASK)
  .value("PseudoVFNCVT_X_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2)
  .value("PseudoVFNCVT_X_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2_MASK)
  .value("PseudoVFNCVT_X_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4)
  .value("PseudoVFNCVT_X_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4_MASK)
  .value("PseudoVFNCVT_X_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8)
  .value("PseudoVFNCVT_X_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8_MASK)
  .value("PseudoVFNMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16)
  .value("PseudoVFNMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16_MASK)
  .value("PseudoVFNMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16)
  .value("PseudoVFNMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16_MASK)
  .value("PseudoVFNMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16)
  .value("PseudoVFNMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16_MASK)
  .value("PseudoVFNMACC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16)
  .value("PseudoVFNMACC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16_MASK)
  .value("PseudoVFNMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16)
  .value("PseudoVFNMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFNMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16)
  .value("PseudoVFNMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFNMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32)
  .value("PseudoVFNMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32_MASK)
  .value("PseudoVFNMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32)
  .value("PseudoVFNMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32_MASK)
  .value("PseudoVFNMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32)
  .value("PseudoVFNMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32_MASK)
  .value("PseudoVFNMACC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32)
  .value("PseudoVFNMACC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32_MASK)
  .value("PseudoVFNMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32)
  .value("PseudoVFNMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFNMACC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64)
  .value("PseudoVFNMACC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64_MASK)
  .value("PseudoVFNMACC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64)
  .value("PseudoVFNMACC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64_MASK)
  .value("PseudoVFNMACC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64)
  .value("PseudoVFNMACC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64_MASK)
  .value("PseudoVFNMACC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64)
  .value("PseudoVFNMACC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64_MASK)
  .value("PseudoVFNMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16)
  .value("PseudoVFNMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16_MASK)
  .value("PseudoVFNMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32)
  .value("PseudoVFNMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32_MASK)
  .value("PseudoVFNMACC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64)
  .value("PseudoVFNMACC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64_MASK)
  .value("PseudoVFNMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16)
  .value("PseudoVFNMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16_MASK)
  .value("PseudoVFNMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32)
  .value("PseudoVFNMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32_MASK)
  .value("PseudoVFNMACC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64)
  .value("PseudoVFNMACC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64_MASK)
  .value("PseudoVFNMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16)
  .value("PseudoVFNMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16_MASK)
  .value("PseudoVFNMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32)
  .value("PseudoVFNMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32_MASK)
  .value("PseudoVFNMACC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64)
  .value("PseudoVFNMACC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64_MASK)
  .value("PseudoVFNMACC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16)
  .value("PseudoVFNMACC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16_MASK)
  .value("PseudoVFNMACC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32)
  .value("PseudoVFNMACC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32_MASK)
  .value("PseudoVFNMACC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64)
  .value("PseudoVFNMACC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64_MASK)
  .value("PseudoVFNMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16)
  .value("PseudoVFNMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16_MASK)
  .value("PseudoVFNMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32)
  .value("PseudoVFNMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32_MASK)
  .value("PseudoVFNMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16)
  .value("PseudoVFNMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16)
  .value("PseudoVFNMADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16)
  .value("PseudoVFNMADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16)
  .value("PseudoVFNMADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16)
  .value("PseudoVFNMADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16)
  .value("PseudoVFNMADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16_MASK)
  .value("PseudoVFNMADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16)
  .value("PseudoVFNMADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16_MASK)
  .value("PseudoVFNMADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32)
  .value("PseudoVFNMADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32_MASK)
  .value("PseudoVFNMADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32)
  .value("PseudoVFNMADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32_MASK)
  .value("PseudoVFNMADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32)
  .value("PseudoVFNMADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32_MASK)
  .value("PseudoVFNMADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32)
  .value("PseudoVFNMADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32_MASK)
  .value("PseudoVFNMADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32)
  .value("PseudoVFNMADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32_MASK)
  .value("PseudoVFNMADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64)
  .value("PseudoVFNMADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64_MASK)
  .value("PseudoVFNMADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64)
  .value("PseudoVFNMADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64_MASK)
  .value("PseudoVFNMADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64)
  .value("PseudoVFNMADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64_MASK)
  .value("PseudoVFNMADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64)
  .value("PseudoVFNMADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64_MASK)
  .value("PseudoVFNMADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16)
  .value("PseudoVFNMADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16_MASK)
  .value("PseudoVFNMADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32)
  .value("PseudoVFNMADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32_MASK)
  .value("PseudoVFNMADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64)
  .value("PseudoVFNMADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64_MASK)
  .value("PseudoVFNMADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16)
  .value("PseudoVFNMADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16_MASK)
  .value("PseudoVFNMADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32)
  .value("PseudoVFNMADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32_MASK)
  .value("PseudoVFNMADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64)
  .value("PseudoVFNMADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64_MASK)
  .value("PseudoVFNMADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16)
  .value("PseudoVFNMADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16_MASK)
  .value("PseudoVFNMADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32)
  .value("PseudoVFNMADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32_MASK)
  .value("PseudoVFNMADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64)
  .value("PseudoVFNMADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64_MASK)
  .value("PseudoVFNMADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16);
  opcodes.value("PseudoVFNMADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16_MASK)
  .value("PseudoVFNMADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32)
  .value("PseudoVFNMADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32_MASK)
  .value("PseudoVFNMADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64)
  .value("PseudoVFNMADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64_MASK)
  .value("PseudoVFNMADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16)
  .value("PseudoVFNMADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16_MASK)
  .value("PseudoVFNMADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32)
  .value("PseudoVFNMADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32_MASK)
  .value("PseudoVFNMADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16)
  .value("PseudoVFNMADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16)
  .value("PseudoVFNMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16)
  .value("PseudoVFNMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16)
  .value("PseudoVFNMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16)
  .value("PseudoVFNMSAC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16)
  .value("PseudoVFNMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFNMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16)
  .value("PseudoVFNMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFNMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32)
  .value("PseudoVFNMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32_MASK)
  .value("PseudoVFNMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32)
  .value("PseudoVFNMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32_MASK)
  .value("PseudoVFNMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32)
  .value("PseudoVFNMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32_MASK)
  .value("PseudoVFNMSAC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32)
  .value("PseudoVFNMSAC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32_MASK)
  .value("PseudoVFNMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32)
  .value("PseudoVFNMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFNMSAC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64)
  .value("PseudoVFNMSAC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64_MASK)
  .value("PseudoVFNMSAC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64)
  .value("PseudoVFNMSAC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64_MASK)
  .value("PseudoVFNMSAC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64)
  .value("PseudoVFNMSAC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64_MASK)
  .value("PseudoVFNMSAC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64)
  .value("PseudoVFNMSAC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64_MASK)
  .value("PseudoVFNMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16)
  .value("PseudoVFNMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16_MASK)
  .value("PseudoVFNMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32)
  .value("PseudoVFNMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32_MASK)
  .value("PseudoVFNMSAC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64)
  .value("PseudoVFNMSAC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64_MASK)
  .value("PseudoVFNMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16)
  .value("PseudoVFNMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16_MASK)
  .value("PseudoVFNMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32)
  .value("PseudoVFNMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32_MASK)
  .value("PseudoVFNMSAC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64)
  .value("PseudoVFNMSAC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64_MASK)
  .value("PseudoVFNMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16)
  .value("PseudoVFNMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16_MASK)
  .value("PseudoVFNMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32)
  .value("PseudoVFNMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32_MASK)
  .value("PseudoVFNMSAC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64)
  .value("PseudoVFNMSAC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64_MASK)
  .value("PseudoVFNMSAC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16)
  .value("PseudoVFNMSAC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16_MASK)
  .value("PseudoVFNMSAC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32)
  .value("PseudoVFNMSAC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32_MASK)
  .value("PseudoVFNMSAC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64)
  .value("PseudoVFNMSAC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64_MASK)
  .value("PseudoVFNMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16)
  .value("PseudoVFNMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16_MASK)
  .value("PseudoVFNMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32)
  .value("PseudoVFNMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32_MASK)
  .value("PseudoVFNMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16)
  .value("PseudoVFNMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16)
  .value("PseudoVFNMSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16)
  .value("PseudoVFNMSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16)
  .value("PseudoVFNMSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16)
  .value("PseudoVFNMSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16)
  .value("PseudoVFNMSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16_MASK)
  .value("PseudoVFNMSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16)
  .value("PseudoVFNMSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16_MASK)
  .value("PseudoVFNMSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32)
  .value("PseudoVFNMSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32_MASK)
  .value("PseudoVFNMSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32)
  .value("PseudoVFNMSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32_MASK)
  .value("PseudoVFNMSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32)
  .value("PseudoVFNMSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32_MASK)
  .value("PseudoVFNMSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32)
  .value("PseudoVFNMSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32_MASK)
  .value("PseudoVFNMSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32)
  .value("PseudoVFNMSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32_MASK)
  .value("PseudoVFNMSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64)
  .value("PseudoVFNMSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64_MASK)
  .value("PseudoVFNMSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64)
  .value("PseudoVFNMSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64_MASK)
  .value("PseudoVFNMSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64)
  .value("PseudoVFNMSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64_MASK)
  .value("PseudoVFNMSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64)
  .value("PseudoVFNMSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64_MASK)
  .value("PseudoVFNMSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16)
  .value("PseudoVFNMSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16_MASK)
  .value("PseudoVFNMSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32)
  .value("PseudoVFNMSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32_MASK)
  .value("PseudoVFNMSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64)
  .value("PseudoVFNMSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64_MASK)
  .value("PseudoVFNMSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16)
  .value("PseudoVFNMSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16_MASK)
  .value("PseudoVFNMSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32)
  .value("PseudoVFNMSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32_MASK)
  .value("PseudoVFNMSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64)
  .value("PseudoVFNMSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64_MASK)
  .value("PseudoVFNMSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16)
  .value("PseudoVFNMSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16_MASK)
  .value("PseudoVFNMSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32)
  .value("PseudoVFNMSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32_MASK)
  .value("PseudoVFNMSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64)
  .value("PseudoVFNMSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64_MASK)
  .value("PseudoVFNMSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16)
  .value("PseudoVFNMSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16_MASK)
  .value("PseudoVFNMSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32)
  .value("PseudoVFNMSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32_MASK)
  .value("PseudoVFNMSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64)
  .value("PseudoVFNMSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64_MASK)
  .value("PseudoVFNMSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16)
  .value("PseudoVFNMSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16_MASK)
  .value("PseudoVFNMSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32)
  .value("PseudoVFNMSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32_MASK)
  .value("PseudoVFNMSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16)
  .value("PseudoVFNMSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16_MASK)
  .value("PseudoVFNRCLIP_XU_F_QF_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M1)
  .value("PseudoVFNRCLIP_XU_F_QF_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M1_MASK)
  .value("PseudoVFNRCLIP_XU_F_QF_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M2)
  .value("PseudoVFNRCLIP_XU_F_QF_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M2_MASK)
  .value("PseudoVFNRCLIP_XU_F_QF_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF2)
  .value("PseudoVFNRCLIP_XU_F_QF_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF2_MASK)
  .value("PseudoVFNRCLIP_XU_F_QF_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF4)
  .value("PseudoVFNRCLIP_XU_F_QF_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF4_MASK)
  .value("PseudoVFNRCLIP_XU_F_QF_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF8)
  .value("PseudoVFNRCLIP_XU_F_QF_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF8_MASK)
  .value("PseudoVFNRCLIP_X_F_QF_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M1)
  .value("PseudoVFNRCLIP_X_F_QF_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M1_MASK)
  .value("PseudoVFNRCLIP_X_F_QF_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M2)
  .value("PseudoVFNRCLIP_X_F_QF_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M2_MASK)
  .value("PseudoVFNRCLIP_X_F_QF_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF2)
  .value("PseudoVFNRCLIP_X_F_QF_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF2_MASK)
  .value("PseudoVFNRCLIP_X_F_QF_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF4)
  .value("PseudoVFNRCLIP_X_F_QF_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF4_MASK)
  .value("PseudoVFNRCLIP_X_F_QF_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF8)
  .value("PseudoVFNRCLIP_X_F_QF_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF8_MASK)
  .value("PseudoVFRDIV_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16)
  .value("PseudoVFRDIV_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16_MASK)
  .value("PseudoVFRDIV_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16)
  .value("PseudoVFRDIV_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16_MASK)
  .value("PseudoVFRDIV_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16)
  .value("PseudoVFRDIV_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16_MASK)
  .value("PseudoVFRDIV_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16)
  .value("PseudoVFRDIV_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16_MASK)
  .value("PseudoVFRDIV_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16)
  .value("PseudoVFRDIV_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16_MASK)
  .value("PseudoVFRDIV_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16)
  .value("PseudoVFRDIV_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16_MASK)
  .value("PseudoVFRDIV_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32)
  .value("PseudoVFRDIV_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32_MASK)
  .value("PseudoVFRDIV_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32)
  .value("PseudoVFRDIV_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32_MASK)
  .value("PseudoVFRDIV_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32)
  .value("PseudoVFRDIV_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32_MASK)
  .value("PseudoVFRDIV_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32)
  .value("PseudoVFRDIV_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32_MASK)
  .value("PseudoVFRDIV_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32)
  .value("PseudoVFRDIV_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32_MASK)
  .value("PseudoVFRDIV_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64)
  .value("PseudoVFRDIV_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64_MASK)
  .value("PseudoVFRDIV_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64)
  .value("PseudoVFRDIV_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64_MASK)
  .value("PseudoVFRDIV_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64)
  .value("PseudoVFRDIV_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64_MASK)
  .value("PseudoVFRDIV_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64)
  .value("PseudoVFRDIV_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64_MASK)
  .value("PseudoVFREC7_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16)
  .value("PseudoVFREC7_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16_MASK)
  .value("PseudoVFREC7_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32)
  .value("PseudoVFREC7_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32_MASK)
  .value("PseudoVFREC7_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64)
  .value("PseudoVFREC7_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64_MASK)
  .value("PseudoVFREC7_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16)
  .value("PseudoVFREC7_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16_MASK)
  .value("PseudoVFREC7_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32)
  .value("PseudoVFREC7_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32_MASK)
  .value("PseudoVFREC7_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64)
  .value("PseudoVFREC7_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64_MASK)
  .value("PseudoVFREC7_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16)
  .value("PseudoVFREC7_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16_MASK)
  .value("PseudoVFREC7_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32)
  .value("PseudoVFREC7_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32_MASK)
  .value("PseudoVFREC7_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64)
  .value("PseudoVFREC7_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64_MASK)
  .value("PseudoVFREC7_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16)
  .value("PseudoVFREC7_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16_MASK)
  .value("PseudoVFREC7_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32)
  .value("PseudoVFREC7_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32_MASK)
  .value("PseudoVFREC7_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64)
  .value("PseudoVFREC7_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64_MASK)
  .value("PseudoVFREC7_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16)
  .value("PseudoVFREC7_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16_MASK)
  .value("PseudoVFREC7_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32)
  .value("PseudoVFREC7_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32_MASK)
  .value("PseudoVFREC7_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16)
  .value("PseudoVFREC7_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16_MASK)
  .value("PseudoVFREDMAX_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16)
  .value("PseudoVFREDMAX_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16_MASK)
  .value("PseudoVFREDMAX_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32)
  .value("PseudoVFREDMAX_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32_MASK)
  .value("PseudoVFREDMAX_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64)
  .value("PseudoVFREDMAX_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64_MASK)
  .value("PseudoVFREDMAX_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16)
  .value("PseudoVFREDMAX_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16_MASK)
  .value("PseudoVFREDMAX_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32)
  .value("PseudoVFREDMAX_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32_MASK)
  .value("PseudoVFREDMAX_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64)
  .value("PseudoVFREDMAX_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64_MASK)
  .value("PseudoVFREDMAX_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16)
  .value("PseudoVFREDMAX_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16_MASK)
  .value("PseudoVFREDMAX_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32)
  .value("PseudoVFREDMAX_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32_MASK)
  .value("PseudoVFREDMAX_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64)
  .value("PseudoVFREDMAX_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64_MASK)
  .value("PseudoVFREDMAX_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16)
  .value("PseudoVFREDMAX_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16_MASK)
  .value("PseudoVFREDMAX_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32)
  .value("PseudoVFREDMAX_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32_MASK)
  .value("PseudoVFREDMAX_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64)
  .value("PseudoVFREDMAX_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64_MASK)
  .value("PseudoVFREDMAX_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16)
  .value("PseudoVFREDMAX_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16_MASK)
  .value("PseudoVFREDMAX_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32)
  .value("PseudoVFREDMAX_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32_MASK)
  .value("PseudoVFREDMAX_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16)
  .value("PseudoVFREDMAX_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16_MASK)
  .value("PseudoVFREDMIN_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16)
  .value("PseudoVFREDMIN_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16_MASK)
  .value("PseudoVFREDMIN_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32)
  .value("PseudoVFREDMIN_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32_MASK)
  .value("PseudoVFREDMIN_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64)
  .value("PseudoVFREDMIN_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64_MASK)
  .value("PseudoVFREDMIN_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16)
  .value("PseudoVFREDMIN_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16_MASK)
  .value("PseudoVFREDMIN_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32)
  .value("PseudoVFREDMIN_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32_MASK)
  .value("PseudoVFREDMIN_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64)
  .value("PseudoVFREDMIN_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64_MASK)
  .value("PseudoVFREDMIN_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16)
  .value("PseudoVFREDMIN_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16_MASK)
  .value("PseudoVFREDMIN_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32)
  .value("PseudoVFREDMIN_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32_MASK)
  .value("PseudoVFREDMIN_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64)
  .value("PseudoVFREDMIN_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64_MASK)
  .value("PseudoVFREDMIN_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16)
  .value("PseudoVFREDMIN_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16_MASK)
  .value("PseudoVFREDMIN_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32)
  .value("PseudoVFREDMIN_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32_MASK)
  .value("PseudoVFREDMIN_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64)
  .value("PseudoVFREDMIN_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64_MASK)
  .value("PseudoVFREDMIN_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16)
  .value("PseudoVFREDMIN_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16_MASK)
  .value("PseudoVFREDMIN_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32)
  .value("PseudoVFREDMIN_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32_MASK)
  .value("PseudoVFREDMIN_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16)
  .value("PseudoVFREDMIN_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16_MASK)
  .value("PseudoVFREDOSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16)
  .value("PseudoVFREDOSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16_MASK)
  .value("PseudoVFREDOSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32)
  .value("PseudoVFREDOSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32_MASK)
  .value("PseudoVFREDOSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64)
  .value("PseudoVFREDOSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64_MASK)
  .value("PseudoVFREDOSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16)
  .value("PseudoVFREDOSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16_MASK)
  .value("PseudoVFREDOSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32)
  .value("PseudoVFREDOSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32_MASK)
  .value("PseudoVFREDOSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64)
  .value("PseudoVFREDOSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64_MASK)
  .value("PseudoVFREDOSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16)
  .value("PseudoVFREDOSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16_MASK)
  .value("PseudoVFREDOSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32)
  .value("PseudoVFREDOSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32_MASK)
  .value("PseudoVFREDOSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64)
  .value("PseudoVFREDOSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64_MASK)
  .value("PseudoVFREDOSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16)
  .value("PseudoVFREDOSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16_MASK)
  .value("PseudoVFREDOSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32)
  .value("PseudoVFREDOSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32_MASK)
  .value("PseudoVFREDOSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64)
  .value("PseudoVFREDOSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64_MASK)
  .value("PseudoVFREDOSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16)
  .value("PseudoVFREDOSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16_MASK)
  .value("PseudoVFREDOSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32)
  .value("PseudoVFREDOSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32_MASK)
  .value("PseudoVFREDOSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16);
  opcodes.value("PseudoVFREDOSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16_MASK)
  .value("PseudoVFREDUSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16)
  .value("PseudoVFREDUSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16_MASK)
  .value("PseudoVFREDUSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32)
  .value("PseudoVFREDUSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32_MASK)
  .value("PseudoVFREDUSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64)
  .value("PseudoVFREDUSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64_MASK)
  .value("PseudoVFREDUSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16)
  .value("PseudoVFREDUSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16_MASK)
  .value("PseudoVFREDUSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32)
  .value("PseudoVFREDUSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32_MASK)
  .value("PseudoVFREDUSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64)
  .value("PseudoVFREDUSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64_MASK)
  .value("PseudoVFREDUSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16)
  .value("PseudoVFREDUSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16_MASK)
  .value("PseudoVFREDUSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32)
  .value("PseudoVFREDUSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32_MASK)
  .value("PseudoVFREDUSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64)
  .value("PseudoVFREDUSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64_MASK)
  .value("PseudoVFREDUSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16)
  .value("PseudoVFREDUSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16_MASK)
  .value("PseudoVFREDUSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32)
  .value("PseudoVFREDUSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32_MASK)
  .value("PseudoVFREDUSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64)
  .value("PseudoVFREDUSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64_MASK)
  .value("PseudoVFREDUSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16)
  .value("PseudoVFREDUSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16_MASK)
  .value("PseudoVFREDUSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32)
  .value("PseudoVFREDUSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32_MASK)
  .value("PseudoVFREDUSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16)
  .value("PseudoVFREDUSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M1_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M2_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M4_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M8_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF2_MASK)
  .value("PseudoVFROUND_NOEXCEPT_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF4_MASK)
  .value("PseudoVFRSQRT7_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16)
  .value("PseudoVFRSQRT7_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16_MASK)
  .value("PseudoVFRSQRT7_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32)
  .value("PseudoVFRSQRT7_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32_MASK)
  .value("PseudoVFRSQRT7_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64)
  .value("PseudoVFRSQRT7_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64_MASK)
  .value("PseudoVFRSQRT7_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16)
  .value("PseudoVFRSQRT7_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16_MASK)
  .value("PseudoVFRSQRT7_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32)
  .value("PseudoVFRSQRT7_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32_MASK)
  .value("PseudoVFRSQRT7_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64)
  .value("PseudoVFRSQRT7_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64_MASK)
  .value("PseudoVFRSQRT7_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16)
  .value("PseudoVFRSQRT7_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16_MASK)
  .value("PseudoVFRSQRT7_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32)
  .value("PseudoVFRSQRT7_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32_MASK)
  .value("PseudoVFRSQRT7_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64)
  .value("PseudoVFRSQRT7_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64_MASK)
  .value("PseudoVFRSQRT7_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16)
  .value("PseudoVFRSQRT7_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16_MASK)
  .value("PseudoVFRSQRT7_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32)
  .value("PseudoVFRSQRT7_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32_MASK)
  .value("PseudoVFRSQRT7_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64)
  .value("PseudoVFRSQRT7_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64_MASK)
  .value("PseudoVFRSQRT7_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16)
  .value("PseudoVFRSQRT7_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16_MASK)
  .value("PseudoVFRSQRT7_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32)
  .value("PseudoVFRSQRT7_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32_MASK)
  .value("PseudoVFRSQRT7_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16)
  .value("PseudoVFRSQRT7_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16)
  .value("PseudoVFRSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16)
  .value("PseudoVFRSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16)
  .value("PseudoVFRSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16)
  .value("PseudoVFRSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16)
  .value("PseudoVFRSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16_MASK)
  .value("PseudoVFRSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16)
  .value("PseudoVFRSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16_MASK)
  .value("PseudoVFRSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32)
  .value("PseudoVFRSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32_MASK)
  .value("PseudoVFRSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32)
  .value("PseudoVFRSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32_MASK)
  .value("PseudoVFRSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32)
  .value("PseudoVFRSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32_MASK)
  .value("PseudoVFRSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32)
  .value("PseudoVFRSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32_MASK)
  .value("PseudoVFRSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32)
  .value("PseudoVFRSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32_MASK)
  .value("PseudoVFRSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64)
  .value("PseudoVFRSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64_MASK)
  .value("PseudoVFRSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64)
  .value("PseudoVFRSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64_MASK)
  .value("PseudoVFRSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64)
  .value("PseudoVFRSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64_MASK)
  .value("PseudoVFRSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64)
  .value("PseudoVFRSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64_MASK)
  .value("PseudoVFSGNJN_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16)
  .value("PseudoVFSGNJN_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16_MASK)
  .value("PseudoVFSGNJN_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16)
  .value("PseudoVFSGNJN_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16_MASK)
  .value("PseudoVFSGNJN_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16)
  .value("PseudoVFSGNJN_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16_MASK)
  .value("PseudoVFSGNJN_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16)
  .value("PseudoVFSGNJN_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16_MASK)
  .value("PseudoVFSGNJN_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16)
  .value("PseudoVFSGNJN_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16_MASK)
  .value("PseudoVFSGNJN_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16)
  .value("PseudoVFSGNJN_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16_MASK)
  .value("PseudoVFSGNJN_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32)
  .value("PseudoVFSGNJN_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32_MASK)
  .value("PseudoVFSGNJN_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32)
  .value("PseudoVFSGNJN_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32_MASK)
  .value("PseudoVFSGNJN_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32)
  .value("PseudoVFSGNJN_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32_MASK)
  .value("PseudoVFSGNJN_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32)
  .value("PseudoVFSGNJN_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32_MASK)
  .value("PseudoVFSGNJN_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32)
  .value("PseudoVFSGNJN_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32_MASK)
  .value("PseudoVFSGNJN_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64)
  .value("PseudoVFSGNJN_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64_MASK)
  .value("PseudoVFSGNJN_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64)
  .value("PseudoVFSGNJN_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64_MASK)
  .value("PseudoVFSGNJN_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64)
  .value("PseudoVFSGNJN_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64_MASK)
  .value("PseudoVFSGNJN_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64)
  .value("PseudoVFSGNJN_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64_MASK)
  .value("PseudoVFSGNJN_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16)
  .value("PseudoVFSGNJN_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16_MASK)
  .value("PseudoVFSGNJN_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32)
  .value("PseudoVFSGNJN_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32_MASK)
  .value("PseudoVFSGNJN_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64)
  .value("PseudoVFSGNJN_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64_MASK)
  .value("PseudoVFSGNJN_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16)
  .value("PseudoVFSGNJN_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16_MASK)
  .value("PseudoVFSGNJN_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32)
  .value("PseudoVFSGNJN_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32_MASK)
  .value("PseudoVFSGNJN_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64)
  .value("PseudoVFSGNJN_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64_MASK)
  .value("PseudoVFSGNJN_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16)
  .value("PseudoVFSGNJN_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16_MASK)
  .value("PseudoVFSGNJN_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32)
  .value("PseudoVFSGNJN_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32_MASK)
  .value("PseudoVFSGNJN_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64)
  .value("PseudoVFSGNJN_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64_MASK)
  .value("PseudoVFSGNJN_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16)
  .value("PseudoVFSGNJN_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16_MASK)
  .value("PseudoVFSGNJN_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32)
  .value("PseudoVFSGNJN_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32_MASK)
  .value("PseudoVFSGNJN_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64)
  .value("PseudoVFSGNJN_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64_MASK)
  .value("PseudoVFSGNJN_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16)
  .value("PseudoVFSGNJN_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16_MASK)
  .value("PseudoVFSGNJN_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32)
  .value("PseudoVFSGNJN_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32_MASK)
  .value("PseudoVFSGNJN_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16)
  .value("PseudoVFSGNJN_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16)
  .value("PseudoVFSGNJX_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16)
  .value("PseudoVFSGNJX_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16)
  .value("PseudoVFSGNJX_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16)
  .value("PseudoVFSGNJX_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16)
  .value("PseudoVFSGNJX_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16_MASK)
  .value("PseudoVFSGNJX_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16)
  .value("PseudoVFSGNJX_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16_MASK)
  .value("PseudoVFSGNJX_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32)
  .value("PseudoVFSGNJX_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32_MASK)
  .value("PseudoVFSGNJX_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32)
  .value("PseudoVFSGNJX_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32_MASK)
  .value("PseudoVFSGNJX_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32)
  .value("PseudoVFSGNJX_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32_MASK)
  .value("PseudoVFSGNJX_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32)
  .value("PseudoVFSGNJX_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32_MASK)
  .value("PseudoVFSGNJX_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32)
  .value("PseudoVFSGNJX_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32_MASK)
  .value("PseudoVFSGNJX_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64)
  .value("PseudoVFSGNJX_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64_MASK)
  .value("PseudoVFSGNJX_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64)
  .value("PseudoVFSGNJX_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64_MASK)
  .value("PseudoVFSGNJX_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64)
  .value("PseudoVFSGNJX_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64_MASK)
  .value("PseudoVFSGNJX_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64)
  .value("PseudoVFSGNJX_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64_MASK)
  .value("PseudoVFSGNJX_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16)
  .value("PseudoVFSGNJX_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16_MASK)
  .value("PseudoVFSGNJX_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32)
  .value("PseudoVFSGNJX_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32_MASK)
  .value("PseudoVFSGNJX_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64)
  .value("PseudoVFSGNJX_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64_MASK)
  .value("PseudoVFSGNJX_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16)
  .value("PseudoVFSGNJX_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16_MASK)
  .value("PseudoVFSGNJX_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32)
  .value("PseudoVFSGNJX_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32_MASK)
  .value("PseudoVFSGNJX_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64)
  .value("PseudoVFSGNJX_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64_MASK)
  .value("PseudoVFSGNJX_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16)
  .value("PseudoVFSGNJX_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16_MASK)
  .value("PseudoVFSGNJX_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32)
  .value("PseudoVFSGNJX_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32_MASK)
  .value("PseudoVFSGNJX_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64)
  .value("PseudoVFSGNJX_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64_MASK)
  .value("PseudoVFSGNJX_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16)
  .value("PseudoVFSGNJX_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16_MASK)
  .value("PseudoVFSGNJX_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32)
  .value("PseudoVFSGNJX_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32_MASK)
  .value("PseudoVFSGNJX_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64)
  .value("PseudoVFSGNJX_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64_MASK)
  .value("PseudoVFSGNJX_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16)
  .value("PseudoVFSGNJX_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16_MASK)
  .value("PseudoVFSGNJX_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32)
  .value("PseudoVFSGNJX_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32_MASK)
  .value("PseudoVFSGNJX_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16)
  .value("PseudoVFSGNJX_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16)
  .value("PseudoVFSGNJ_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16)
  .value("PseudoVFSGNJ_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16)
  .value("PseudoVFSGNJ_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16)
  .value("PseudoVFSGNJ_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16)
  .value("PseudoVFSGNJ_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16_MASK)
  .value("PseudoVFSGNJ_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16)
  .value("PseudoVFSGNJ_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16_MASK)
  .value("PseudoVFSGNJ_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32)
  .value("PseudoVFSGNJ_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32_MASK)
  .value("PseudoVFSGNJ_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32)
  .value("PseudoVFSGNJ_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32_MASK)
  .value("PseudoVFSGNJ_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32)
  .value("PseudoVFSGNJ_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32_MASK)
  .value("PseudoVFSGNJ_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32)
  .value("PseudoVFSGNJ_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32_MASK)
  .value("PseudoVFSGNJ_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32)
  .value("PseudoVFSGNJ_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32_MASK)
  .value("PseudoVFSGNJ_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64)
  .value("PseudoVFSGNJ_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64_MASK)
  .value("PseudoVFSGNJ_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64)
  .value("PseudoVFSGNJ_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64_MASK)
  .value("PseudoVFSGNJ_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64)
  .value("PseudoVFSGNJ_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64_MASK)
  .value("PseudoVFSGNJ_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64)
  .value("PseudoVFSGNJ_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64_MASK)
  .value("PseudoVFSGNJ_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16)
  .value("PseudoVFSGNJ_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16_MASK)
  .value("PseudoVFSGNJ_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32)
  .value("PseudoVFSGNJ_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32_MASK)
  .value("PseudoVFSGNJ_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64)
  .value("PseudoVFSGNJ_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64_MASK)
  .value("PseudoVFSGNJ_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16)
  .value("PseudoVFSGNJ_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16_MASK)
  .value("PseudoVFSGNJ_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32)
  .value("PseudoVFSGNJ_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32_MASK)
  .value("PseudoVFSGNJ_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64)
  .value("PseudoVFSGNJ_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64_MASK)
  .value("PseudoVFSGNJ_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16)
  .value("PseudoVFSGNJ_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16_MASK)
  .value("PseudoVFSGNJ_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32)
  .value("PseudoVFSGNJ_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32_MASK)
  .value("PseudoVFSGNJ_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64)
  .value("PseudoVFSGNJ_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64_MASK)
  .value("PseudoVFSGNJ_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16)
  .value("PseudoVFSGNJ_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16_MASK)
  .value("PseudoVFSGNJ_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32)
  .value("PseudoVFSGNJ_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32_MASK)
  .value("PseudoVFSGNJ_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64)
  .value("PseudoVFSGNJ_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64_MASK)
  .value("PseudoVFSGNJ_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16)
  .value("PseudoVFSGNJ_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16_MASK)
  .value("PseudoVFSGNJ_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32)
  .value("PseudoVFSGNJ_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32_MASK)
  .value("PseudoVFSGNJ_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16)
  .value("PseudoVFSGNJ_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8)
  .value("PseudoVFSLIDE1DOWN_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2)
  .value("PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4)
  .value("PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8)
  .value("PseudoVFSLIDE1DOWN_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2)
  .value("PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1);
  opcodes.value("PseudoVFSLIDE1DOWN_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8)
  .value("PseudoVFSLIDE1DOWN_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1)
  .value("PseudoVFSLIDE1UP_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2)
  .value("PseudoVFSLIDE1UP_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4)
  .value("PseudoVFSLIDE1UP_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8)
  .value("PseudoVFSLIDE1UP_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2)
  .value("PseudoVFSLIDE1UP_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2_MASK)
  .value("PseudoVFSLIDE1UP_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4)
  .value("PseudoVFSLIDE1UP_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4_MASK)
  .value("PseudoVFSLIDE1UP_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1)
  .value("PseudoVFSLIDE1UP_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1_MASK)
  .value("PseudoVFSLIDE1UP_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2)
  .value("PseudoVFSLIDE1UP_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2_MASK)
  .value("PseudoVFSLIDE1UP_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4)
  .value("PseudoVFSLIDE1UP_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4_MASK)
  .value("PseudoVFSLIDE1UP_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8)
  .value("PseudoVFSLIDE1UP_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8_MASK)
  .value("PseudoVFSLIDE1UP_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2)
  .value("PseudoVFSLIDE1UP_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2_MASK)
  .value("PseudoVFSLIDE1UP_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1)
  .value("PseudoVFSLIDE1UP_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1_MASK)
  .value("PseudoVFSLIDE1UP_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2)
  .value("PseudoVFSLIDE1UP_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2_MASK)
  .value("PseudoVFSLIDE1UP_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4)
  .value("PseudoVFSLIDE1UP_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4_MASK)
  .value("PseudoVFSLIDE1UP_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8)
  .value("PseudoVFSLIDE1UP_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8_MASK)
  .value("PseudoVFSQRT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16)
  .value("PseudoVFSQRT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16_MASK)
  .value("PseudoVFSQRT_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32)
  .value("PseudoVFSQRT_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32_MASK)
  .value("PseudoVFSQRT_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64)
  .value("PseudoVFSQRT_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64_MASK)
  .value("PseudoVFSQRT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16)
  .value("PseudoVFSQRT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16_MASK)
  .value("PseudoVFSQRT_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32)
  .value("PseudoVFSQRT_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32_MASK)
  .value("PseudoVFSQRT_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64)
  .value("PseudoVFSQRT_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64_MASK)
  .value("PseudoVFSQRT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16)
  .value("PseudoVFSQRT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16_MASK)
  .value("PseudoVFSQRT_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32)
  .value("PseudoVFSQRT_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32_MASK)
  .value("PseudoVFSQRT_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64)
  .value("PseudoVFSQRT_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64_MASK)
  .value("PseudoVFSQRT_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16)
  .value("PseudoVFSQRT_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16_MASK)
  .value("PseudoVFSQRT_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32)
  .value("PseudoVFSQRT_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32_MASK)
  .value("PseudoVFSQRT_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64)
  .value("PseudoVFSQRT_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64_MASK)
  .value("PseudoVFSQRT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16)
  .value("PseudoVFSQRT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16_MASK)
  .value("PseudoVFSQRT_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32)
  .value("PseudoVFSQRT_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32_MASK)
  .value("PseudoVFSQRT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16)
  .value("PseudoVFSQRT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16_MASK)
  .value("PseudoVFSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16)
  .value("PseudoVFSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16_MASK)
  .value("PseudoVFSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16)
  .value("PseudoVFSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16_MASK)
  .value("PseudoVFSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16)
  .value("PseudoVFSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16_MASK)
  .value("PseudoVFSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16)
  .value("PseudoVFSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16_MASK)
  .value("PseudoVFSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16)
  .value("PseudoVFSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16_MASK)
  .value("PseudoVFSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16)
  .value("PseudoVFSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16_MASK)
  .value("PseudoVFSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32)
  .value("PseudoVFSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32_MASK)
  .value("PseudoVFSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32)
  .value("PseudoVFSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32_MASK)
  .value("PseudoVFSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32)
  .value("PseudoVFSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32_MASK)
  .value("PseudoVFSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32)
  .value("PseudoVFSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32_MASK)
  .value("PseudoVFSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32)
  .value("PseudoVFSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32_MASK)
  .value("PseudoVFSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64)
  .value("PseudoVFSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64_MASK)
  .value("PseudoVFSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64)
  .value("PseudoVFSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64_MASK)
  .value("PseudoVFSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64)
  .value("PseudoVFSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64_MASK)
  .value("PseudoVFSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64)
  .value("PseudoVFSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64_MASK)
  .value("PseudoVFSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16)
  .value("PseudoVFSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16_MASK)
  .value("PseudoVFSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32)
  .value("PseudoVFSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32_MASK)
  .value("PseudoVFSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64)
  .value("PseudoVFSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64_MASK)
  .value("PseudoVFSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16)
  .value("PseudoVFSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16_MASK)
  .value("PseudoVFSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32)
  .value("PseudoVFSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32_MASK)
  .value("PseudoVFSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64)
  .value("PseudoVFSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64_MASK)
  .value("PseudoVFSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16)
  .value("PseudoVFSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16_MASK)
  .value("PseudoVFSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32)
  .value("PseudoVFSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32_MASK)
  .value("PseudoVFSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64)
  .value("PseudoVFSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64_MASK)
  .value("PseudoVFSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16)
  .value("PseudoVFSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16_MASK)
  .value("PseudoVFSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32)
  .value("PseudoVFSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32_MASK)
  .value("PseudoVFSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64)
  .value("PseudoVFSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64_MASK)
  .value("PseudoVFSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16)
  .value("PseudoVFSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16_MASK)
  .value("PseudoVFSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32)
  .value("PseudoVFSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32_MASK)
  .value("PseudoVFSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16)
  .value("PseudoVFSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16_MASK)
  .value("PseudoVFWADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16)
  .value("PseudoVFWADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16_MASK)
  .value("PseudoVFWADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16)
  .value("PseudoVFWADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16_MASK)
  .value("PseudoVFWADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16)
  .value("PseudoVFWADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16_MASK)
  .value("PseudoVFWADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16)
  .value("PseudoVFWADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16)
  .value("PseudoVFWADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32)
  .value("PseudoVFWADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32_MASK)
  .value("PseudoVFWADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32)
  .value("PseudoVFWADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32_MASK)
  .value("PseudoVFWADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32)
  .value("PseudoVFWADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32_MASK)
  .value("PseudoVFWADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32)
  .value("PseudoVFWADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16)
  .value("PseudoVFWADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16_MASK)
  .value("PseudoVFWADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32)
  .value("PseudoVFWADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32_MASK)
  .value("PseudoVFWADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16)
  .value("PseudoVFWADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16_MASK)
  .value("PseudoVFWADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32)
  .value("PseudoVFWADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32_MASK)
  .value("PseudoVFWADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16)
  .value("PseudoVFWADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16_MASK)
  .value("PseudoVFWADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32)
  .value("PseudoVFWADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32_MASK)
  .value("PseudoVFWADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16)
  .value("PseudoVFWADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16_MASK)
  .value("PseudoVFWADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32)
  .value("PseudoVFWADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32_MASK)
  .value("PseudoVFWADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16)
  .value("PseudoVFWADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16_MASK)
  .value("PseudoVFWADD_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16)
  .value("PseudoVFWADD_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16_MASK)
  .value("PseudoVFWADD_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16)
  .value("PseudoVFWADD_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16_MASK)
  .value("PseudoVFWADD_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16)
  .value("PseudoVFWADD_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16_MASK)
  .value("PseudoVFWADD_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16)
  .value("PseudoVFWADD_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16_MASK)
  .value("PseudoVFWADD_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16)
  .value("PseudoVFWADD_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16_MASK)
  .value("PseudoVFWADD_WFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32)
  .value("PseudoVFWADD_WFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32_MASK)
  .value("PseudoVFWADD_WFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32)
  .value("PseudoVFWADD_WFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32_MASK)
  .value("PseudoVFWADD_WFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32)
  .value("PseudoVFWADD_WFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32_MASK)
  .value("PseudoVFWADD_WFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32)
  .value("PseudoVFWADD_WFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32_MASK)
  .value("PseudoVFWADD_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16)
  .value("PseudoVFWADD_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK)
  .value("PseudoVFWADD_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK_TIED)
  .value("PseudoVFWADD_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_TIED)
  .value("PseudoVFWADD_WV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32)
  .value("PseudoVFWADD_WV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK)
  .value("PseudoVFWADD_WV_M1_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK_TIED)
  .value("PseudoVFWADD_WV_M1_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_TIED)
  .value("PseudoVFWADD_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16)
  .value("PseudoVFWADD_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK)
  .value("PseudoVFWADD_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK_TIED)
  .value("PseudoVFWADD_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_TIED)
  .value("PseudoVFWADD_WV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32)
  .value("PseudoVFWADD_WV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK)
  .value("PseudoVFWADD_WV_M2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK_TIED)
  .value("PseudoVFWADD_WV_M2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_TIED)
  .value("PseudoVFWADD_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16)
  .value("PseudoVFWADD_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK)
  .value("PseudoVFWADD_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK_TIED)
  .value("PseudoVFWADD_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_TIED)
  .value("PseudoVFWADD_WV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32)
  .value("PseudoVFWADD_WV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK)
  .value("PseudoVFWADD_WV_M4_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK_TIED)
  .value("PseudoVFWADD_WV_M4_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_TIED)
  .value("PseudoVFWADD_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16)
  .value("PseudoVFWADD_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK)
  .value("PseudoVFWADD_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK_TIED)
  .value("PseudoVFWADD_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_TIED)
  .value("PseudoVFWADD_WV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32)
  .value("PseudoVFWADD_WV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK)
  .value("PseudoVFWADD_WV_MF2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK_TIED)
  .value("PseudoVFWADD_WV_MF2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_TIED)
  .value("PseudoVFWADD_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16)
  .value("PseudoVFWADD_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK)
  .value("PseudoVFWADD_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK_TIED)
  .value("PseudoVFWADD_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_TIED)
  .value("PseudoVFWCVTBF16_F_F_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16)
  .value("PseudoVFWCVTBF16_F_F_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32)
  .value("PseudoVFWCVTBF16_F_F_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16)
  .value("PseudoVFWCVTBF16_F_F_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32)
  .value("PseudoVFWCVTBF16_F_F_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16)
  .value("PseudoVFWCVTBF16_F_F_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32)
  .value("PseudoVFWCVTBF16_F_F_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16)
  .value("PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32)
  .value("PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK)
  .value("PseudoVFWCVTBF16_F_F_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16)
  .value("PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK)
  .value("PseudoVFWCVT_F_F_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16)
  .value("PseudoVFWCVT_F_F_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16_MASK)
  .value("PseudoVFWCVT_F_F_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32)
  .value("PseudoVFWCVT_F_F_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32_MASK)
  .value("PseudoVFWCVT_F_F_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16)
  .value("PseudoVFWCVT_F_F_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16_MASK)
  .value("PseudoVFWCVT_F_F_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32)
  .value("PseudoVFWCVT_F_F_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32_MASK)
  .value("PseudoVFWCVT_F_F_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16)
  .value("PseudoVFWCVT_F_F_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16_MASK)
  .value("PseudoVFWCVT_F_F_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32)
  .value("PseudoVFWCVT_F_F_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32_MASK)
  .value("PseudoVFWCVT_F_F_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16)
  .value("PseudoVFWCVT_F_F_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16_MASK)
  .value("PseudoVFWCVT_F_F_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32)
  .value("PseudoVFWCVT_F_F_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32_MASK)
  .value("PseudoVFWCVT_F_F_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16)
  .value("PseudoVFWCVT_F_F_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16)
  .value("PseudoVFWCVT_F_XU_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32)
  .value("PseudoVFWCVT_F_XU_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32_MASK)
  .value("PseudoVFWCVT_F_XU_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8)
  .value("PseudoVFWCVT_F_XU_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8_MASK)
  .value("PseudoVFWCVT_F_XU_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16)
  .value("PseudoVFWCVT_F_XU_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32)
  .value("PseudoVFWCVT_F_XU_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32_MASK)
  .value("PseudoVFWCVT_F_XU_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8)
  .value("PseudoVFWCVT_F_XU_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8_MASK)
  .value("PseudoVFWCVT_F_XU_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16)
  .value("PseudoVFWCVT_F_XU_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32)
  .value("PseudoVFWCVT_F_XU_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32_MASK)
  .value("PseudoVFWCVT_F_XU_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8)
  .value("PseudoVFWCVT_F_XU_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16)
  .value("PseudoVFWCVT_F_XU_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32)
  .value("PseudoVFWCVT_F_XU_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8)
  .value("PseudoVFWCVT_F_XU_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16)
  .value("PseudoVFWCVT_F_XU_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8)
  .value("PseudoVFWCVT_F_XU_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8_MASK)
  .value("PseudoVFWCVT_F_XU_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8)
  .value("PseudoVFWCVT_F_XU_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16)
  .value("PseudoVFWCVT_F_X_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16_MASK)
  .value("PseudoVFWCVT_F_X_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32)
  .value("PseudoVFWCVT_F_X_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32_MASK)
  .value("PseudoVFWCVT_F_X_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8)
  .value("PseudoVFWCVT_F_X_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16)
  .value("PseudoVFWCVT_F_X_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16_MASK)
  .value("PseudoVFWCVT_F_X_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32)
  .value("PseudoVFWCVT_F_X_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32_MASK)
  .value("PseudoVFWCVT_F_X_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8)
  .value("PseudoVFWCVT_F_X_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16)
  .value("PseudoVFWCVT_F_X_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16_MASK)
  .value("PseudoVFWCVT_F_X_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32)
  .value("PseudoVFWCVT_F_X_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32_MASK)
  .value("PseudoVFWCVT_F_X_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8);
  opcodes.value("PseudoVFWCVT_F_X_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16)
  .value("PseudoVFWCVT_F_X_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16_MASK)
  .value("PseudoVFWCVT_F_X_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32)
  .value("PseudoVFWCVT_F_X_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32_MASK)
  .value("PseudoVFWCVT_F_X_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8)
  .value("PseudoVFWCVT_F_X_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16)
  .value("PseudoVFWCVT_F_X_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16_MASK)
  .value("PseudoVFWCVT_F_X_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8)
  .value("PseudoVFWCVT_F_X_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8_MASK)
  .value("PseudoVFWCVT_F_X_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8)
  .value("PseudoVFWCVT_F_X_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8_MASK)
  .value("PseudoVFWCVT_RM_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M1)
  .value("PseudoVFWCVT_RM_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M1_MASK)
  .value("PseudoVFWCVT_RM_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M2)
  .value("PseudoVFWCVT_RM_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M2_MASK)
  .value("PseudoVFWCVT_RM_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M4)
  .value("PseudoVFWCVT_RM_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M4_MASK)
  .value("PseudoVFWCVT_RM_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF2)
  .value("PseudoVFWCVT_RM_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF2_MASK)
  .value("PseudoVFWCVT_RM_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF4)
  .value("PseudoVFWCVT_RM_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF4_MASK)
  .value("PseudoVFWCVT_RM_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M1)
  .value("PseudoVFWCVT_RM_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M1_MASK)
  .value("PseudoVFWCVT_RM_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M2)
  .value("PseudoVFWCVT_RM_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M2_MASK)
  .value("PseudoVFWCVT_RM_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M4)
  .value("PseudoVFWCVT_RM_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M4_MASK)
  .value("PseudoVFWCVT_RM_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF2)
  .value("PseudoVFWCVT_RM_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF2_MASK)
  .value("PseudoVFWCVT_RM_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF4)
  .value("PseudoVFWCVT_RM_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF4_MASK)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4)
  .value("PseudoVFWCVT_RTZ_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK)
  .value("PseudoVFWCVT_RTZ_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2)
  .value("PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK)
  .value("PseudoVFWCVT_RTZ_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4)
  .value("PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK)
  .value("PseudoVFWCVT_RTZ_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1)
  .value("PseudoVFWCVT_RTZ_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1_MASK)
  .value("PseudoVFWCVT_RTZ_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2)
  .value("PseudoVFWCVT_RTZ_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2_MASK)
  .value("PseudoVFWCVT_RTZ_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4)
  .value("PseudoVFWCVT_RTZ_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4_MASK)
  .value("PseudoVFWCVT_RTZ_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2)
  .value("PseudoVFWCVT_RTZ_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK)
  .value("PseudoVFWCVT_RTZ_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4)
  .value("PseudoVFWCVT_RTZ_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK)
  .value("PseudoVFWCVT_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1)
  .value("PseudoVFWCVT_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1_MASK)
  .value("PseudoVFWCVT_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2)
  .value("PseudoVFWCVT_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2_MASK)
  .value("PseudoVFWCVT_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4)
  .value("PseudoVFWCVT_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4_MASK)
  .value("PseudoVFWCVT_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2)
  .value("PseudoVFWCVT_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2_MASK)
  .value("PseudoVFWCVT_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4)
  .value("PseudoVFWCVT_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4_MASK)
  .value("PseudoVFWCVT_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1)
  .value("PseudoVFWCVT_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1_MASK)
  .value("PseudoVFWCVT_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2)
  .value("PseudoVFWCVT_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2_MASK)
  .value("PseudoVFWCVT_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4)
  .value("PseudoVFWCVT_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4_MASK)
  .value("PseudoVFWCVT_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2)
  .value("PseudoVFWCVT_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2_MASK)
  .value("PseudoVFWCVT_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4)
  .value("PseudoVFWCVT_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4_MASK)
  .value("PseudoVFWMACCBF16_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16)
  .value("PseudoVFWMACCBF16_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK)
  .value("PseudoVFWMACCBF16_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16)
  .value("PseudoVFWMACCBF16_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK)
  .value("PseudoVFWMACCBF16_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16)
  .value("PseudoVFWMACCBF16_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK)
  .value("PseudoVFWMACCBF16_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16)
  .value("PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWMACCBF16_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16)
  .value("PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWMACCBF16_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16)
  .value("PseudoVFWMACCBF16_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16_MASK)
  .value("PseudoVFWMACCBF16_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32)
  .value("PseudoVFWMACCBF16_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32_MASK)
  .value("PseudoVFWMACCBF16_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16)
  .value("PseudoVFWMACCBF16_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16_MASK)
  .value("PseudoVFWMACCBF16_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32)
  .value("PseudoVFWMACCBF16_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32_MASK)
  .value("PseudoVFWMACCBF16_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16)
  .value("PseudoVFWMACCBF16_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16_MASK)
  .value("PseudoVFWMACCBF16_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32)
  .value("PseudoVFWMACCBF16_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32_MASK)
  .value("PseudoVFWMACCBF16_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16)
  .value("PseudoVFWMACCBF16_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16_MASK)
  .value("PseudoVFWMACCBF16_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32)
  .value("PseudoVFWMACCBF16_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32_MASK)
  .value("PseudoVFWMACCBF16_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16)
  .value("PseudoVFWMACCBF16_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16_MASK)
  .value("PseudoVFWMACC_4x4x4_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M1)
  .value("PseudoVFWMACC_4x4x4_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M2)
  .value("PseudoVFWMACC_4x4x4_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M4)
  .value("PseudoVFWMACC_4x4x4_M8", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M8)
  .value("PseudoVFWMACC_4x4x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_MF2)
  .value("PseudoVFWMACC_4x4x4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_MF4)
  .value("PseudoVFWMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16)
  .value("PseudoVFWMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16_MASK)
  .value("PseudoVFWMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16)
  .value("PseudoVFWMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16_MASK)
  .value("PseudoVFWMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16)
  .value("PseudoVFWMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16_MASK)
  .value("PseudoVFWMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16)
  .value("PseudoVFWMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16)
  .value("PseudoVFWMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32)
  .value("PseudoVFWMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32_MASK)
  .value("PseudoVFWMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32)
  .value("PseudoVFWMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32_MASK)
  .value("PseudoVFWMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32)
  .value("PseudoVFWMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32_MASK)
  .value("PseudoVFWMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32)
  .value("PseudoVFWMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16)
  .value("PseudoVFWMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16_MASK)
  .value("PseudoVFWMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32)
  .value("PseudoVFWMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32_MASK)
  .value("PseudoVFWMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16)
  .value("PseudoVFWMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16_MASK)
  .value("PseudoVFWMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32)
  .value("PseudoVFWMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32_MASK)
  .value("PseudoVFWMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16)
  .value("PseudoVFWMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16_MASK)
  .value("PseudoVFWMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32)
  .value("PseudoVFWMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32_MASK)
  .value("PseudoVFWMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16)
  .value("PseudoVFWMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16_MASK)
  .value("PseudoVFWMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32)
  .value("PseudoVFWMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32_MASK)
  .value("PseudoVFWMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16)
  .value("PseudoVFWMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16_MASK)
  .value("PseudoVFWMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16)
  .value("PseudoVFWMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16_MASK)
  .value("PseudoVFWMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16)
  .value("PseudoVFWMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16_MASK)
  .value("PseudoVFWMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16)
  .value("PseudoVFWMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16_MASK)
  .value("PseudoVFWMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16)
  .value("PseudoVFWMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16)
  .value("PseudoVFWMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32)
  .value("PseudoVFWMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32_MASK)
  .value("PseudoVFWMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32)
  .value("PseudoVFWMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32_MASK)
  .value("PseudoVFWMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32)
  .value("PseudoVFWMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32_MASK)
  .value("PseudoVFWMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32)
  .value("PseudoVFWMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16)
  .value("PseudoVFWMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16_MASK)
  .value("PseudoVFWMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32)
  .value("PseudoVFWMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32_MASK)
  .value("PseudoVFWMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16)
  .value("PseudoVFWMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16_MASK)
  .value("PseudoVFWMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32)
  .value("PseudoVFWMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32_MASK)
  .value("PseudoVFWMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16)
  .value("PseudoVFWMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16_MASK)
  .value("PseudoVFWMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32)
  .value("PseudoVFWMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32_MASK)
  .value("PseudoVFWMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16)
  .value("PseudoVFWMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16_MASK)
  .value("PseudoVFWMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32)
  .value("PseudoVFWMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32_MASK)
  .value("PseudoVFWMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16)
  .value("PseudoVFWMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16_MASK)
  .value("PseudoVFWMUL_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16)
  .value("PseudoVFWMUL_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16_MASK)
  .value("PseudoVFWMUL_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16)
  .value("PseudoVFWMUL_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16_MASK)
  .value("PseudoVFWMUL_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16)
  .value("PseudoVFWMUL_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16_MASK)
  .value("PseudoVFWMUL_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16)
  .value("PseudoVFWMUL_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWMUL_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16)
  .value("PseudoVFWMUL_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWMUL_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32)
  .value("PseudoVFWMUL_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32_MASK)
  .value("PseudoVFWMUL_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32)
  .value("PseudoVFWMUL_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32_MASK)
  .value("PseudoVFWMUL_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32)
  .value("PseudoVFWMUL_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32_MASK)
  .value("PseudoVFWMUL_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32)
  .value("PseudoVFWMUL_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWMUL_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16)
  .value("PseudoVFWMUL_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16_MASK)
  .value("PseudoVFWMUL_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32)
  .value("PseudoVFWMUL_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32_MASK)
  .value("PseudoVFWMUL_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16)
  .value("PseudoVFWMUL_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16_MASK)
  .value("PseudoVFWMUL_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32)
  .value("PseudoVFWMUL_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32_MASK)
  .value("PseudoVFWMUL_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16)
  .value("PseudoVFWMUL_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16_MASK)
  .value("PseudoVFWMUL_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32)
  .value("PseudoVFWMUL_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32_MASK)
  .value("PseudoVFWMUL_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16)
  .value("PseudoVFWMUL_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16_MASK)
  .value("PseudoVFWMUL_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32)
  .value("PseudoVFWMUL_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32_MASK)
  .value("PseudoVFWMUL_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16)
  .value("PseudoVFWMUL_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16_MASK)
  .value("PseudoVFWNMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16)
  .value("PseudoVFWNMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16_MASK)
  .value("PseudoVFWNMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16)
  .value("PseudoVFWNMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16_MASK)
  .value("PseudoVFWNMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16)
  .value("PseudoVFWNMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16_MASK)
  .value("PseudoVFWNMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16)
  .value("PseudoVFWNMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWNMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16)
  .value("PseudoVFWNMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWNMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32)
  .value("PseudoVFWNMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32_MASK)
  .value("PseudoVFWNMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32)
  .value("PseudoVFWNMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32_MASK)
  .value("PseudoVFWNMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32)
  .value("PseudoVFWNMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32_MASK)
  .value("PseudoVFWNMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32)
  .value("PseudoVFWNMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWNMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16)
  .value("PseudoVFWNMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16_MASK)
  .value("PseudoVFWNMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32)
  .value("PseudoVFWNMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32_MASK)
  .value("PseudoVFWNMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16)
  .value("PseudoVFWNMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16_MASK)
  .value("PseudoVFWNMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32)
  .value("PseudoVFWNMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32_MASK)
  .value("PseudoVFWNMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16)
  .value("PseudoVFWNMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16_MASK)
  .value("PseudoVFWNMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32)
  .value("PseudoVFWNMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32_MASK)
  .value("PseudoVFWNMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16)
  .value("PseudoVFWNMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16_MASK)
  .value("PseudoVFWNMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32)
  .value("PseudoVFWNMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32_MASK)
  .value("PseudoVFWNMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16)
  .value("PseudoVFWNMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16)
  .value("PseudoVFWNMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16)
  .value("PseudoVFWNMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16)
  .value("PseudoVFWNMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16)
  .value("PseudoVFWNMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16)
  .value("PseudoVFWNMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWNMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32)
  .value("PseudoVFWNMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32_MASK)
  .value("PseudoVFWNMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32)
  .value("PseudoVFWNMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32_MASK)
  .value("PseudoVFWNMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32)
  .value("PseudoVFWNMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32_MASK)
  .value("PseudoVFWNMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32)
  .value("PseudoVFWNMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWNMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16)
  .value("PseudoVFWNMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16_MASK)
  .value("PseudoVFWNMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32)
  .value("PseudoVFWNMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32_MASK)
  .value("PseudoVFWNMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16)
  .value("PseudoVFWNMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16_MASK)
  .value("PseudoVFWNMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32)
  .value("PseudoVFWNMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32_MASK)
  .value("PseudoVFWNMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16)
  .value("PseudoVFWNMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16_MASK)
  .value("PseudoVFWNMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32)
  .value("PseudoVFWNMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32_MASK)
  .value("PseudoVFWNMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16)
  .value("PseudoVFWNMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16_MASK)
  .value("PseudoVFWNMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32)
  .value("PseudoVFWNMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32_MASK)
  .value("PseudoVFWNMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16)
  .value("PseudoVFWNMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16)
  .value("PseudoVFWREDOSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32)
  .value("PseudoVFWREDOSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32_MASK)
  .value("PseudoVFWREDOSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16)
  .value("PseudoVFWREDOSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32)
  .value("PseudoVFWREDOSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32_MASK)
  .value("PseudoVFWREDOSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16)
  .value("PseudoVFWREDOSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32)
  .value("PseudoVFWREDOSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32_MASK)
  .value("PseudoVFWREDOSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16);
  opcodes.value("PseudoVFWREDOSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32)
  .value("PseudoVFWREDOSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32_MASK)
  .value("PseudoVFWREDOSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16)
  .value("PseudoVFWREDOSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16_MASK)
  .value("PseudoVFWREDOSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32)
  .value("PseudoVFWREDOSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32_MASK)
  .value("PseudoVFWREDOSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16)
  .value("PseudoVFWREDOSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16)
  .value("PseudoVFWREDUSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32)
  .value("PseudoVFWREDUSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32_MASK)
  .value("PseudoVFWREDUSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16)
  .value("PseudoVFWREDUSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32)
  .value("PseudoVFWREDUSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32_MASK)
  .value("PseudoVFWREDUSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16)
  .value("PseudoVFWREDUSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32)
  .value("PseudoVFWREDUSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32_MASK)
  .value("PseudoVFWREDUSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16)
  .value("PseudoVFWREDUSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32)
  .value("PseudoVFWREDUSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32_MASK)
  .value("PseudoVFWREDUSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16)
  .value("PseudoVFWREDUSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16_MASK)
  .value("PseudoVFWREDUSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32)
  .value("PseudoVFWREDUSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32_MASK)
  .value("PseudoVFWREDUSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16)
  .value("PseudoVFWREDUSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16_MASK)
  .value("PseudoVFWSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16)
  .value("PseudoVFWSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16_MASK)
  .value("PseudoVFWSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16)
  .value("PseudoVFWSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16_MASK)
  .value("PseudoVFWSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16)
  .value("PseudoVFWSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16_MASK)
  .value("PseudoVFWSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16)
  .value("PseudoVFWSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16_MASK)
  .value("PseudoVFWSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16)
  .value("PseudoVFWSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16_MASK)
  .value("PseudoVFWSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32)
  .value("PseudoVFWSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32_MASK)
  .value("PseudoVFWSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32)
  .value("PseudoVFWSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32_MASK)
  .value("PseudoVFWSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32)
  .value("PseudoVFWSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32_MASK)
  .value("PseudoVFWSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32)
  .value("PseudoVFWSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32_MASK)
  .value("PseudoVFWSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16)
  .value("PseudoVFWSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16_MASK)
  .value("PseudoVFWSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32)
  .value("PseudoVFWSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32_MASK)
  .value("PseudoVFWSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16)
  .value("PseudoVFWSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16_MASK)
  .value("PseudoVFWSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32)
  .value("PseudoVFWSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32_MASK)
  .value("PseudoVFWSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16)
  .value("PseudoVFWSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16_MASK)
  .value("PseudoVFWSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32)
  .value("PseudoVFWSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32_MASK)
  .value("PseudoVFWSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16)
  .value("PseudoVFWSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16_MASK)
  .value("PseudoVFWSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32)
  .value("PseudoVFWSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32_MASK)
  .value("PseudoVFWSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16)
  .value("PseudoVFWSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16_MASK)
  .value("PseudoVFWSUB_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16)
  .value("PseudoVFWSUB_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16_MASK)
  .value("PseudoVFWSUB_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16)
  .value("PseudoVFWSUB_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16_MASK)
  .value("PseudoVFWSUB_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16)
  .value("PseudoVFWSUB_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16_MASK)
  .value("PseudoVFWSUB_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16)
  .value("PseudoVFWSUB_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16_MASK)
  .value("PseudoVFWSUB_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16)
  .value("PseudoVFWSUB_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16_MASK)
  .value("PseudoVFWSUB_WFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32)
  .value("PseudoVFWSUB_WFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32_MASK)
  .value("PseudoVFWSUB_WFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32)
  .value("PseudoVFWSUB_WFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32_MASK)
  .value("PseudoVFWSUB_WFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32)
  .value("PseudoVFWSUB_WFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32_MASK)
  .value("PseudoVFWSUB_WFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32)
  .value("PseudoVFWSUB_WFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32_MASK)
  .value("PseudoVFWSUB_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16)
  .value("PseudoVFWSUB_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK)
  .value("PseudoVFWSUB_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK_TIED)
  .value("PseudoVFWSUB_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_TIED)
  .value("PseudoVFWSUB_WV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32)
  .value("PseudoVFWSUB_WV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK)
  .value("PseudoVFWSUB_WV_M1_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK_TIED)
  .value("PseudoVFWSUB_WV_M1_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_TIED)
  .value("PseudoVFWSUB_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16)
  .value("PseudoVFWSUB_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK)
  .value("PseudoVFWSUB_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK_TIED)
  .value("PseudoVFWSUB_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_TIED)
  .value("PseudoVFWSUB_WV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32)
  .value("PseudoVFWSUB_WV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK)
  .value("PseudoVFWSUB_WV_M2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK_TIED)
  .value("PseudoVFWSUB_WV_M2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_TIED)
  .value("PseudoVFWSUB_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16)
  .value("PseudoVFWSUB_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK)
  .value("PseudoVFWSUB_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK_TIED)
  .value("PseudoVFWSUB_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_TIED)
  .value("PseudoVFWSUB_WV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32)
  .value("PseudoVFWSUB_WV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK)
  .value("PseudoVFWSUB_WV_M4_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK_TIED)
  .value("PseudoVFWSUB_WV_M4_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_TIED)
  .value("PseudoVFWSUB_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16)
  .value("PseudoVFWSUB_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK)
  .value("PseudoVFWSUB_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK_TIED)
  .value("PseudoVFWSUB_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_TIED)
  .value("PseudoVFWSUB_WV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32)
  .value("PseudoVFWSUB_WV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK)
  .value("PseudoVFWSUB_WV_MF2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK_TIED)
  .value("PseudoVFWSUB_WV_MF2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_TIED)
  .value("PseudoVFWSUB_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16)
  .value("PseudoVFWSUB_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK)
  .value("PseudoVFWSUB_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK_TIED)
  .value("PseudoVFWSUB_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_TIED)
  .value("PseudoVGHSH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M1)
  .value("PseudoVGHSH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M2)
  .value("PseudoVGHSH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M4)
  .value("PseudoVGHSH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M8)
  .value("PseudoVGHSH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_MF2)
  .value("PseudoVGMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M1)
  .value("PseudoVGMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M2)
  .value("PseudoVGMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M4)
  .value("PseudoVGMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M8)
  .value("PseudoVGMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_MF2)
  .value("PseudoVID_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1)
  .value("PseudoVID_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1_MASK)
  .value("PseudoVID_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2)
  .value("PseudoVID_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2_MASK)
  .value("PseudoVID_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4)
  .value("PseudoVID_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4_MASK)
  .value("PseudoVID_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8)
  .value("PseudoVID_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8_MASK)
  .value("PseudoVID_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2)
  .value("PseudoVID_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2_MASK)
  .value("PseudoVID_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4)
  .value("PseudoVID_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4_MASK)
  .value("PseudoVID_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8)
  .value("PseudoVID_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8_MASK)
  .value("PseudoVIOTA_M_M1", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1)
  .value("PseudoVIOTA_M_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1_MASK)
  .value("PseudoVIOTA_M_M2", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2)
  .value("PseudoVIOTA_M_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2_MASK)
  .value("PseudoVIOTA_M_M4", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4)
  .value("PseudoVIOTA_M_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4_MASK)
  .value("PseudoVIOTA_M_M8", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8)
  .value("PseudoVIOTA_M_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8_MASK)
  .value("PseudoVIOTA_M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2)
  .value("PseudoVIOTA_M_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2_MASK)
  .value("PseudoVIOTA_M_MF4", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4)
  .value("PseudoVIOTA_M_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4_MASK)
  .value("PseudoVIOTA_M_MF8", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8)
  .value("PseudoVIOTA_M_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8_MASK)
  .value("PseudoVLE16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1)
  .value("PseudoVLE16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1_MASK)
  .value("PseudoVLE16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2)
  .value("PseudoVLE16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2_MASK)
  .value("PseudoVLE16FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4)
  .value("PseudoVLE16FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4_MASK)
  .value("PseudoVLE16FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8)
  .value("PseudoVLE16FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8_MASK)
  .value("PseudoVLE16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2)
  .value("PseudoVLE16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2_MASK)
  .value("PseudoVLE16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4)
  .value("PseudoVLE16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4_MASK)
  .value("PseudoVLE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1)
  .value("PseudoVLE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1_MASK)
  .value("PseudoVLE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2)
  .value("PseudoVLE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2_MASK)
  .value("PseudoVLE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4)
  .value("PseudoVLE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4_MASK)
  .value("PseudoVLE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8)
  .value("PseudoVLE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8_MASK)
  .value("PseudoVLE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2)
  .value("PseudoVLE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2_MASK)
  .value("PseudoVLE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4)
  .value("PseudoVLE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4_MASK)
  .value("PseudoVLE32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1)
  .value("PseudoVLE32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1_MASK)
  .value("PseudoVLE32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2)
  .value("PseudoVLE32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2_MASK)
  .value("PseudoVLE32FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4)
  .value("PseudoVLE32FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4_MASK)
  .value("PseudoVLE32FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8)
  .value("PseudoVLE32FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8_MASK)
  .value("PseudoVLE32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2)
  .value("PseudoVLE32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2_MASK)
  .value("PseudoVLE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1)
  .value("PseudoVLE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1_MASK)
  .value("PseudoVLE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2)
  .value("PseudoVLE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2_MASK)
  .value("PseudoVLE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4)
  .value("PseudoVLE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4_MASK)
  .value("PseudoVLE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8)
  .value("PseudoVLE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8_MASK)
  .value("PseudoVLE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2)
  .value("PseudoVLE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2_MASK)
  .value("PseudoVLE64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1)
  .value("PseudoVLE64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1_MASK)
  .value("PseudoVLE64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2)
  .value("PseudoVLE64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2_MASK)
  .value("PseudoVLE64FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4)
  .value("PseudoVLE64FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4_MASK)
  .value("PseudoVLE64FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8)
  .value("PseudoVLE64FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8_MASK)
  .value("PseudoVLE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1)
  .value("PseudoVLE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1_MASK)
  .value("PseudoVLE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2)
  .value("PseudoVLE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2_MASK)
  .value("PseudoVLE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4)
  .value("PseudoVLE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4_MASK)
  .value("PseudoVLE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8)
  .value("PseudoVLE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8_MASK)
  .value("PseudoVLE8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1)
  .value("PseudoVLE8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1_MASK)
  .value("PseudoVLE8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2)
  .value("PseudoVLE8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2_MASK)
  .value("PseudoVLE8FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4)
  .value("PseudoVLE8FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4_MASK)
  .value("PseudoVLE8FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8)
  .value("PseudoVLE8FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8_MASK)
  .value("PseudoVLE8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2)
  .value("PseudoVLE8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2_MASK)
  .value("PseudoVLE8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4)
  .value("PseudoVLE8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4_MASK)
  .value("PseudoVLE8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8)
  .value("PseudoVLE8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8_MASK)
  .value("PseudoVLE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1)
  .value("PseudoVLE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1_MASK)
  .value("PseudoVLE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2)
  .value("PseudoVLE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2_MASK)
  .value("PseudoVLE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4)
  .value("PseudoVLE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4_MASK)
  .value("PseudoVLE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8)
  .value("PseudoVLE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8_MASK)
  .value("PseudoVLE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2)
  .value("PseudoVLE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2_MASK)
  .value("PseudoVLE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4)
  .value("PseudoVLE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4_MASK)
  .value("PseudoVLE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8)
  .value("PseudoVLE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8_MASK)
  .value("PseudoVLM_V_B1", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B1)
  .value("PseudoVLM_V_B16", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B16)
  .value("PseudoVLM_V_B2", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B2)
  .value("PseudoVLM_V_B32", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B32)
  .value("PseudoVLM_V_B4", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B4)
  .value("PseudoVLM_V_B64", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B64)
  .value("PseudoVLM_V_B8", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B8)
  .value("PseudoVLOXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1)
  .value("PseudoVLOXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1_MASK)
  .value("PseudoVLOXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2)
  .value("PseudoVLOXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2_MASK)
  .value("PseudoVLOXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4)
  .value("PseudoVLOXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4_MASK)
  .value("PseudoVLOXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2)
  .value("PseudoVLOXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2_MASK)
  .value("PseudoVLOXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1)
  .value("PseudoVLOXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1_MASK)
  .value("PseudoVLOXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2)
  .value("PseudoVLOXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2_MASK)
  .value("PseudoVLOXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4)
  .value("PseudoVLOXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4_MASK)
  .value("PseudoVLOXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8)
  .value("PseudoVLOXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8_MASK)
  .value("PseudoVLOXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2)
  .value("PseudoVLOXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2_MASK)
  .value("PseudoVLOXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4)
  .value("PseudoVLOXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4_MASK)
  .value("PseudoVLOXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8)
  .value("PseudoVLOXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8_MASK)
  .value("PseudoVLOXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4)
  .value("PseudoVLOXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4_MASK)
  .value("PseudoVLOXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8)
  .value("PseudoVLOXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8_MASK)
  .value("PseudoVLOXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1)
  .value("PseudoVLOXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1_MASK)
  .value("PseudoVLOXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2)
  .value("PseudoVLOXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2_MASK)
  .value("PseudoVLOXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2)
  .value("PseudoVLOXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4)
  .value("PseudoVLOXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1)
  .value("PseudoVLOXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1_MASK)
  .value("PseudoVLOXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2)
  .value("PseudoVLOXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4)
  .value("PseudoVLOXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8)
  .value("PseudoVLOXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1)
  .value("PseudoVLOXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1_MASK)
  .value("PseudoVLOXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2)
  .value("PseudoVLOXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2_MASK);
  opcodes.value("PseudoVLOXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2)
  .value("PseudoVLOXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2_MASK)
  .value("PseudoVLOXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4)
  .value("PseudoVLOXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4_MASK)
  .value("PseudoVLOXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1)
  .value("PseudoVLOXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1_MASK)
  .value("PseudoVLOXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2)
  .value("PseudoVLOXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2_MASK)
  .value("PseudoVLOXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4)
  .value("PseudoVLOXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4_MASK)
  .value("PseudoVLOXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2)
  .value("PseudoVLOXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2_MASK)
  .value("PseudoVLOXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1)
  .value("PseudoVLOXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1_MASK)
  .value("PseudoVLOXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2)
  .value("PseudoVLOXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2_MASK)
  .value("PseudoVLOXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4)
  .value("PseudoVLOXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4_MASK)
  .value("PseudoVLOXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8)
  .value("PseudoVLOXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8_MASK)
  .value("PseudoVLOXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2)
  .value("PseudoVLOXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2_MASK)
  .value("PseudoVLOXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4)
  .value("PseudoVLOXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4_MASK)
  .value("PseudoVLOXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8)
  .value("PseudoVLOXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8_MASK)
  .value("PseudoVLOXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1)
  .value("PseudoVLOXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1_MASK)
  .value("PseudoVLOXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2)
  .value("PseudoVLOXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4)
  .value("PseudoVLOXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8)
  .value("PseudoVLOXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1)
  .value("PseudoVLOXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1_MASK)
  .value("PseudoVLOXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2)
  .value("PseudoVLOXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2_MASK)
  .value("PseudoVLOXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4)
  .value("PseudoVLOXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4_MASK)
  .value("PseudoVLOXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8)
  .value("PseudoVLOXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8_MASK)
  .value("PseudoVLOXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1)
  .value("PseudoVLOXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1_MASK)
  .value("PseudoVLOXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2)
  .value("PseudoVLOXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2_MASK)
  .value("PseudoVLOXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2)
  .value("PseudoVLOXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2_MASK)
  .value("PseudoVLOXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4)
  .value("PseudoVLOXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4_MASK)
  .value("PseudoVLOXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1)
  .value("PseudoVLOXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1_MASK)
  .value("PseudoVLOXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2)
  .value("PseudoVLOXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2_MASK)
  .value("PseudoVLOXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4)
  .value("PseudoVLOXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4_MASK)
  .value("PseudoVLOXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2)
  .value("PseudoVLOXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2_MASK)
  .value("PseudoVLOXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1)
  .value("PseudoVLOXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1_MASK)
  .value("PseudoVLOXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2)
  .value("PseudoVLOXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2_MASK)
  .value("PseudoVLOXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4)
  .value("PseudoVLOXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4_MASK)
  .value("PseudoVLOXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8)
  .value("PseudoVLOXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8_MASK)
  .value("PseudoVLOXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1)
  .value("PseudoVLOXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1_MASK)
  .value("PseudoVLOXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2)
  .value("PseudoVLOXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2_MASK)
  .value("PseudoVLOXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4)
  .value("PseudoVLOXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4_MASK)
  .value("PseudoVLOXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8)
  .value("PseudoVLOXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8_MASK)
  .value("PseudoVLOXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2)
  .value("PseudoVLOXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2_MASK)
  .value("PseudoVLOXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4)
  .value("PseudoVLOXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4_MASK)
  .value("PseudoVLOXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8)
  .value("PseudoVLOXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8_MASK)
  .value("PseudoVLOXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4)
  .value("PseudoVLOXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4_MASK)
  .value("PseudoVLOXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8)
  .value("PseudoVLOXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8_MASK)
  .value("PseudoVLOXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8)
  .value("PseudoVLOXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8_MASK)
  .value("PseudoVLOXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1)
  .value("PseudoVLOXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1_MASK)
  .value("PseudoVLOXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2)
  .value("PseudoVLOXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2_MASK)
  .value("PseudoVLOXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4)
  .value("PseudoVLOXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4_MASK)
  .value("PseudoVLOXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2)
  .value("PseudoVLOXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1)
  .value("PseudoVLOXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1_MASK)
  .value("PseudoVLOXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2)
  .value("PseudoVLOXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2_MASK)
  .value("PseudoVLOXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2)
  .value("PseudoVLOXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4)
  .value("PseudoVLOXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1)
  .value("PseudoVLOXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1_MASK)
  .value("PseudoVLOXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2)
  .value("PseudoVLOXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4)
  .value("PseudoVLOXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8)
  .value("PseudoVLOXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1)
  .value("PseudoVLOXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2)
  .value("PseudoVLOXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2_MASK)
  .value("PseudoVLOXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4)
  .value("PseudoVLOXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4_MASK)
  .value("PseudoVLOXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2)
  .value("PseudoVLOXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1)
  .value("PseudoVLOXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2)
  .value("PseudoVLOXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2_MASK)
  .value("PseudoVLOXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4)
  .value("PseudoVLOXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4_MASK)
  .value("PseudoVLOXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2)
  .value("PseudoVLOXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2_MASK)
  .value("PseudoVLOXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4)
  .value("PseudoVLOXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4_MASK)
  .value("PseudoVLOXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4)
  .value("PseudoVLOXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1)
  .value("PseudoVLOXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2)
  .value("PseudoVLOXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1)
  .value("PseudoVLOXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1)
  .value("PseudoVLOXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2)
  .value("PseudoVLOXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2)
  .value("PseudoVLOXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4)
  .value("PseudoVLOXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1)
  .value("PseudoVLOXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2)
  .value("PseudoVLOXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4)
  .value("PseudoVLOXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4_MASK)
  .value("PseudoVLOXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2)
  .value("PseudoVLOXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1)
  .value("PseudoVLOXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2)
  .value("PseudoVLOXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4)
  .value("PseudoVLOXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4_MASK)
  .value("PseudoVLOXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2)
  .value("PseudoVLOXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2_MASK)
  .value("PseudoVLOXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4)
  .value("PseudoVLOXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4_MASK)
  .value("PseudoVLOXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1)
  .value("PseudoVLOXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1)
  .value("PseudoVLOXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2)
  .value("PseudoVLOXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4)
  .value("PseudoVLOXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8)
  .value("PseudoVLOXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1)
  .value("PseudoVLOXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2)
  .value("PseudoVLOXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2)
  .value("PseudoVLOXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4)
  .value("PseudoVLOXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1)
  .value("PseudoVLOXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2)
  .value("PseudoVLOXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4)
  .value("PseudoVLOXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4_MASK)
  .value("PseudoVLOXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2)
  .value("PseudoVLOXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1)
  .value("PseudoVLOXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2)
  .value("PseudoVLOXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2_MASK)
  .value("PseudoVLOXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4)
  .value("PseudoVLOXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4_MASK)
  .value("PseudoVLOXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1)
  .value("PseudoVLOXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2)
  .value("PseudoVLOXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2_MASK)
  .value("PseudoVLOXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4)
  .value("PseudoVLOXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4_MASK)
  .value("PseudoVLOXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2)
  .value("PseudoVLOXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2_MASK)
  .value("PseudoVLOXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4)
  .value("PseudoVLOXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4_MASK)
  .value("PseudoVLOXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4)
  .value("PseudoVLOXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1)
  .value("PseudoVLOXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2)
  .value("PseudoVLOXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4)
  .value("PseudoVLOXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1)
  .value("PseudoVLOXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2)
  .value("PseudoVLOXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1)
  .value("PseudoVLOXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1)
  .value("PseudoVLOXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2)
  .value("PseudoVLOXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2_MASK)
  .value("PseudoVLOXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2)
  .value("PseudoVLOXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1)
  .value("PseudoVLOXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2)
  .value("PseudoVLOXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2_MASK)
  .value("PseudoVLOXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2)
  .value("PseudoVLOXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1)
  .value("PseudoVLOXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2)
  .value("PseudoVLOXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1)
  .value("PseudoVLOXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1)
  .value("PseudoVLOXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2)
  .value("PseudoVLOXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2_MASK)
  .value("PseudoVLOXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2)
  .value("PseudoVLOXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4)
  .value("PseudoVLOXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1)
  .value("PseudoVLOXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2)
  .value("PseudoVLOXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2_MASK)
  .value("PseudoVLOXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2)
  .value("PseudoVLOXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1)
  .value("PseudoVLOXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2)
  .value("PseudoVLOXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2_MASK)
  .value("PseudoVLOXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2)
  .value("PseudoVLOXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2_MASK)
  .value("PseudoVLOXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1)
  .value("PseudoVLOXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK);
  opcodes.value("PseudoVLOXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1)
  .value("PseudoVLOXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2)
  .value("PseudoVLOXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4)
  .value("PseudoVLOXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8)
  .value("PseudoVLOXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1)
  .value("PseudoVLOXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2)
  .value("PseudoVLOXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2_MASK)
  .value("PseudoVLOXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2)
  .value("PseudoVLOXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4)
  .value("PseudoVLOXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1)
  .value("PseudoVLOXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2)
  .value("PseudoVLOXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2_MASK)
  .value("PseudoVLOXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2)
  .value("PseudoVLOXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1)
  .value("PseudoVLOXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2)
  .value("PseudoVLOXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2_MASK)
  .value("PseudoVLOXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1)
  .value("PseudoVLOXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2)
  .value("PseudoVLOXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2_MASK)
  .value("PseudoVLOXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2)
  .value("PseudoVLOXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1)
  .value("PseudoVLOXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2)
  .value("PseudoVLOXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1)
  .value("PseudoVLOXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2)
  .value("PseudoVLOXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1)
  .value("PseudoVLOXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1)
  .value("PseudoVLOXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2)
  .value("PseudoVLOXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2_MASK)
  .value("PseudoVLOXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2)
  .value("PseudoVLOXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1)
  .value("PseudoVLOXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2)
  .value("PseudoVLOXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2_MASK)
  .value("PseudoVLOXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2)
  .value("PseudoVLOXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1)
  .value("PseudoVLOXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2)
  .value("PseudoVLOXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1)
  .value("PseudoVLOXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1)
  .value("PseudoVLOXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2)
  .value("PseudoVLOXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2_MASK)
  .value("PseudoVLOXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2)
  .value("PseudoVLOXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4)
  .value("PseudoVLOXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1)
  .value("PseudoVLOXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2)
  .value("PseudoVLOXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2_MASK)
  .value("PseudoVLOXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2)
  .value("PseudoVLOXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1)
  .value("PseudoVLOXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2)
  .value("PseudoVLOXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2_MASK)
  .value("PseudoVLOXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2)
  .value("PseudoVLOXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2_MASK)
  .value("PseudoVLOXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1)
  .value("PseudoVLOXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1)
  .value("PseudoVLOXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2)
  .value("PseudoVLOXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4)
  .value("PseudoVLOXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8)
  .value("PseudoVLOXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1)
  .value("PseudoVLOXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2)
  .value("PseudoVLOXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2_MASK)
  .value("PseudoVLOXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2)
  .value("PseudoVLOXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4)
  .value("PseudoVLOXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1)
  .value("PseudoVLOXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2)
  .value("PseudoVLOXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2_MASK)
  .value("PseudoVLOXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2)
  .value("PseudoVLOXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1)
  .value("PseudoVLOXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2)
  .value("PseudoVLOXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2_MASK)
  .value("PseudoVLOXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1)
  .value("PseudoVLOXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2)
  .value("PseudoVLOXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2_MASK)
  .value("PseudoVLOXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2)
  .value("PseudoVLOXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1)
  .value("PseudoVLOXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2)
  .value("PseudoVLOXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1)
  .value("PseudoVLOXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2)
  .value("PseudoVLOXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1)
  .value("PseudoVLOXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1)
  .value("PseudoVLOXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2)
  .value("PseudoVLOXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1)
  .value("PseudoVLOXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1)
  .value("PseudoVLOXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1)
  .value("PseudoVLOXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1)
  .value("PseudoVLOXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2)
  .value("PseudoVLOXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4)
  .value("PseudoVLOXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1)
  .value("PseudoVLOXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2)
  .value("PseudoVLOXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1)
  .value("PseudoVLOXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1)
  .value("PseudoVLOXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1)
  .value("PseudoVLOXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2)
  .value("PseudoVLOXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4)
  .value("PseudoVLOXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8)
  .value("PseudoVLOXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1)
  .value("PseudoVLOXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2)
  .value("PseudoVLOXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4)
  .value("PseudoVLOXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1)
  .value("PseudoVLOXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2)
  .value("PseudoVLOXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1)
  .value("PseudoVLOXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1)
  .value("PseudoVLOXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1)
  .value("PseudoVLOXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1)
  .value("PseudoVLOXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1)
  .value("PseudoVLOXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1)
  .value("PseudoVLOXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2)
  .value("PseudoVLOXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1)
  .value("PseudoVLOXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1)
  .value("PseudoVLOXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1)
  .value("PseudoVLOXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1)
  .value("PseudoVLOXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2)
  .value("PseudoVLOXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4)
  .value("PseudoVLOXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1)
  .value("PseudoVLOXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2)
  .value("PseudoVLOXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1)
  .value("PseudoVLOXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1)
  .value("PseudoVLOXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1)
  .value("PseudoVLOXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2)
  .value("PseudoVLOXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4)
  .value("PseudoVLOXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8)
  .value("PseudoVLOXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1)
  .value("PseudoVLOXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2)
  .value("PseudoVLOXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4)
  .value("PseudoVLOXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4_MASK);
  opcodes.value("PseudoVLOXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1)
  .value("PseudoVLOXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2)
  .value("PseudoVLOXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1)
  .value("PseudoVLOXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1)
  .value("PseudoVLOXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1)
  .value("PseudoVLOXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1)
  .value("PseudoVLOXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1)
  .value("PseudoVLOXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1)
  .value("PseudoVLOXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2)
  .value("PseudoVLOXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1)
  .value("PseudoVLOXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1)
  .value("PseudoVLOXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1)
  .value("PseudoVLOXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1)
  .value("PseudoVLOXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2)
  .value("PseudoVLOXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4)
  .value("PseudoVLOXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1)
  .value("PseudoVLOXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2)
  .value("PseudoVLOXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1)
  .value("PseudoVLOXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1)
  .value("PseudoVLOXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1)
  .value("PseudoVLOXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2)
  .value("PseudoVLOXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4)
  .value("PseudoVLOXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8)
  .value("PseudoVLOXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1)
  .value("PseudoVLOXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2)
  .value("PseudoVLOXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4)
  .value("PseudoVLOXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1)
  .value("PseudoVLOXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2)
  .value("PseudoVLOXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1)
  .value("PseudoVLOXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1)
  .value("PseudoVLOXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1)
  .value("PseudoVLOXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1)
  .value("PseudoVLOXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1)
  .value("PseudoVLOXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK)
  .value("PseudoVLOXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1)
  .value("PseudoVLOXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1_MASK)
  .value("PseudoVLOXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2)
  .value("PseudoVLOXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1)
  .value("PseudoVLOXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1)
  .value("PseudoVLOXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2)
  .value("PseudoVLOXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4)
  .value("PseudoVLOXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1)
  .value("PseudoVLOXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8)
  .value("PseudoVLOXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK)
  .value("PseudoVLOXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1)
  .value("PseudoVLOXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1_MASK)
  .value("PseudoVLOXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2)
  .value("PseudoVLOXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4)
  .value("PseudoVLOXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1)
  .value("PseudoVLOXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1_MASK)
  .value("PseudoVLOXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2)
  .value("PseudoVLOXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1)
  .value("PseudoVLOXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1_MASK)
  .value("PseudoVLOXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1)
  .value("PseudoVLOXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8)
  .value("PseudoVLOXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK)
  .value("PseudoVLOXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1)
  .value("PseudoVLOXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1_MASK)
  .value("PseudoVLOXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2)
  .value("PseudoVLOXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2_MASK)
  .value("PseudoVLOXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4)
  .value("PseudoVLOXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4_MASK)
  .value("PseudoVLOXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8)
  .value("PseudoVLOXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8_MASK)
  .value("PseudoVLOXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1)
  .value("PseudoVLOXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1_MASK)
  .value("PseudoVLOXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2)
  .value("PseudoVLOXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2_MASK)
  .value("PseudoVLOXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4)
  .value("PseudoVLOXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4_MASK)
  .value("PseudoVLOXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1)
  .value("PseudoVLOXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1_MASK)
  .value("PseudoVLOXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2)
  .value("PseudoVLOXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2_MASK)
  .value("PseudoVLOXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1)
  .value("PseudoVLOXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1_MASK)
  .value("PseudoVLOXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1)
  .value("PseudoVLOXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1)
  .value("PseudoVLOXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2)
  .value("PseudoVLOXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1)
  .value("PseudoVLOXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2)
  .value("PseudoVLOXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4)
  .value("PseudoVLOXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1)
  .value("PseudoVLOXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8)
  .value("PseudoVLOXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK)
  .value("PseudoVLSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1)
  .value("PseudoVLSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1_MASK)
  .value("PseudoVLSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2)
  .value("PseudoVLSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2_MASK)
  .value("PseudoVLSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4)
  .value("PseudoVLSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4_MASK)
  .value("PseudoVLSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8)
  .value("PseudoVLSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8_MASK)
  .value("PseudoVLSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2)
  .value("PseudoVLSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2_MASK)
  .value("PseudoVLSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4)
  .value("PseudoVLSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4_MASK)
  .value("PseudoVLSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1)
  .value("PseudoVLSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1_MASK)
  .value("PseudoVLSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2)
  .value("PseudoVLSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2_MASK)
  .value("PseudoVLSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4)
  .value("PseudoVLSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4_MASK)
  .value("PseudoVLSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8)
  .value("PseudoVLSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8_MASK)
  .value("PseudoVLSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2)
  .value("PseudoVLSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2_MASK)
  .value("PseudoVLSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1)
  .value("PseudoVLSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1_MASK)
  .value("PseudoVLSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2)
  .value("PseudoVLSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2_MASK)
  .value("PseudoVLSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4)
  .value("PseudoVLSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4_MASK)
  .value("PseudoVLSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8)
  .value("PseudoVLSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8_MASK)
  .value("PseudoVLSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1)
  .value("PseudoVLSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1_MASK)
  .value("PseudoVLSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2)
  .value("PseudoVLSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2_MASK)
  .value("PseudoVLSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4)
  .value("PseudoVLSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4_MASK)
  .value("PseudoVLSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8)
  .value("PseudoVLSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8_MASK)
  .value("PseudoVLSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2)
  .value("PseudoVLSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2_MASK)
  .value("PseudoVLSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4)
  .value("PseudoVLSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4_MASK)
  .value("PseudoVLSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8)
  .value("PseudoVLSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8_MASK)
  .value("PseudoVLSEG2E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1)
  .value("PseudoVLSEG2E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1_MASK)
  .value("PseudoVLSEG2E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2)
  .value("PseudoVLSEG2E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2_MASK)
  .value("PseudoVLSEG2E16FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4)
  .value("PseudoVLSEG2E16FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4_MASK)
  .value("PseudoVLSEG2E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2)
  .value("PseudoVLSEG2E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2_MASK)
  .value("PseudoVLSEG2E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4)
  .value("PseudoVLSEG2E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4_MASK)
  .value("PseudoVLSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1)
  .value("PseudoVLSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1_MASK)
  .value("PseudoVLSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2)
  .value("PseudoVLSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2_MASK)
  .value("PseudoVLSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4)
  .value("PseudoVLSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4_MASK)
  .value("PseudoVLSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2)
  .value("PseudoVLSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2_MASK)
  .value("PseudoVLSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4)
  .value("PseudoVLSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4_MASK)
  .value("PseudoVLSEG2E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1)
  .value("PseudoVLSEG2E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1_MASK)
  .value("PseudoVLSEG2E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2)
  .value("PseudoVLSEG2E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2_MASK)
  .value("PseudoVLSEG2E32FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4)
  .value("PseudoVLSEG2E32FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4_MASK)
  .value("PseudoVLSEG2E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2)
  .value("PseudoVLSEG2E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2_MASK)
  .value("PseudoVLSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1)
  .value("PseudoVLSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1_MASK)
  .value("PseudoVLSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2)
  .value("PseudoVLSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2_MASK)
  .value("PseudoVLSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4)
  .value("PseudoVLSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4_MASK)
  .value("PseudoVLSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2)
  .value("PseudoVLSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2_MASK)
  .value("PseudoVLSEG2E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1)
  .value("PseudoVLSEG2E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1_MASK)
  .value("PseudoVLSEG2E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2)
  .value("PseudoVLSEG2E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2_MASK)
  .value("PseudoVLSEG2E64FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4)
  .value("PseudoVLSEG2E64FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4_MASK)
  .value("PseudoVLSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1)
  .value("PseudoVLSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1_MASK)
  .value("PseudoVLSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2)
  .value("PseudoVLSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2_MASK)
  .value("PseudoVLSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4)
  .value("PseudoVLSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4_MASK)
  .value("PseudoVLSEG2E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1)
  .value("PseudoVLSEG2E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1_MASK)
  .value("PseudoVLSEG2E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2)
  .value("PseudoVLSEG2E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2_MASK)
  .value("PseudoVLSEG2E8FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4)
  .value("PseudoVLSEG2E8FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4_MASK)
  .value("PseudoVLSEG2E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2)
  .value("PseudoVLSEG2E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2_MASK)
  .value("PseudoVLSEG2E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4)
  .value("PseudoVLSEG2E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4_MASK)
  .value("PseudoVLSEG2E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8)
  .value("PseudoVLSEG2E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8_MASK)
  .value("PseudoVLSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1)
  .value("PseudoVLSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1_MASK)
  .value("PseudoVLSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2)
  .value("PseudoVLSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2_MASK)
  .value("PseudoVLSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4)
  .value("PseudoVLSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4_MASK)
  .value("PseudoVLSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2)
  .value("PseudoVLSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2_MASK)
  .value("PseudoVLSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4)
  .value("PseudoVLSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4_MASK);
  opcodes.value("PseudoVLSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8)
  .value("PseudoVLSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8_MASK)
  .value("PseudoVLSEG3E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1)
  .value("PseudoVLSEG3E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1_MASK)
  .value("PseudoVLSEG3E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2)
  .value("PseudoVLSEG3E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2_MASK)
  .value("PseudoVLSEG3E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2)
  .value("PseudoVLSEG3E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2_MASK)
  .value("PseudoVLSEG3E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4)
  .value("PseudoVLSEG3E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4_MASK)
  .value("PseudoVLSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1)
  .value("PseudoVLSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1_MASK)
  .value("PseudoVLSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2)
  .value("PseudoVLSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2_MASK)
  .value("PseudoVLSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2)
  .value("PseudoVLSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2_MASK)
  .value("PseudoVLSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4)
  .value("PseudoVLSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4_MASK)
  .value("PseudoVLSEG3E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1)
  .value("PseudoVLSEG3E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1_MASK)
  .value("PseudoVLSEG3E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2)
  .value("PseudoVLSEG3E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2_MASK)
  .value("PseudoVLSEG3E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2)
  .value("PseudoVLSEG3E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2_MASK)
  .value("PseudoVLSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1)
  .value("PseudoVLSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1_MASK)
  .value("PseudoVLSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2)
  .value("PseudoVLSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2_MASK)
  .value("PseudoVLSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2)
  .value("PseudoVLSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2_MASK)
  .value("PseudoVLSEG3E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1)
  .value("PseudoVLSEG3E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1_MASK)
  .value("PseudoVLSEG3E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2)
  .value("PseudoVLSEG3E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2_MASK)
  .value("PseudoVLSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1)
  .value("PseudoVLSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1_MASK)
  .value("PseudoVLSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2)
  .value("PseudoVLSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2_MASK)
  .value("PseudoVLSEG3E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1)
  .value("PseudoVLSEG3E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1_MASK)
  .value("PseudoVLSEG3E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2)
  .value("PseudoVLSEG3E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2_MASK)
  .value("PseudoVLSEG3E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2)
  .value("PseudoVLSEG3E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2_MASK)
  .value("PseudoVLSEG3E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4)
  .value("PseudoVLSEG3E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4_MASK)
  .value("PseudoVLSEG3E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8)
  .value("PseudoVLSEG3E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8_MASK)
  .value("PseudoVLSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1)
  .value("PseudoVLSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1_MASK)
  .value("PseudoVLSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2)
  .value("PseudoVLSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2_MASK)
  .value("PseudoVLSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2)
  .value("PseudoVLSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2_MASK)
  .value("PseudoVLSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4)
  .value("PseudoVLSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4_MASK)
  .value("PseudoVLSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8)
  .value("PseudoVLSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8_MASK)
  .value("PseudoVLSEG4E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1)
  .value("PseudoVLSEG4E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1_MASK)
  .value("PseudoVLSEG4E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2)
  .value("PseudoVLSEG4E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2_MASK)
  .value("PseudoVLSEG4E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2)
  .value("PseudoVLSEG4E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2_MASK)
  .value("PseudoVLSEG4E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4)
  .value("PseudoVLSEG4E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4_MASK)
  .value("PseudoVLSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1)
  .value("PseudoVLSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1_MASK)
  .value("PseudoVLSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2)
  .value("PseudoVLSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2_MASK)
  .value("PseudoVLSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2)
  .value("PseudoVLSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2_MASK)
  .value("PseudoVLSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4)
  .value("PseudoVLSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4_MASK)
  .value("PseudoVLSEG4E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1)
  .value("PseudoVLSEG4E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1_MASK)
  .value("PseudoVLSEG4E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2)
  .value("PseudoVLSEG4E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2_MASK)
  .value("PseudoVLSEG4E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2)
  .value("PseudoVLSEG4E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2_MASK)
  .value("PseudoVLSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1)
  .value("PseudoVLSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1_MASK)
  .value("PseudoVLSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2)
  .value("PseudoVLSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2_MASK)
  .value("PseudoVLSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2)
  .value("PseudoVLSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2_MASK)
  .value("PseudoVLSEG4E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1)
  .value("PseudoVLSEG4E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1_MASK)
  .value("PseudoVLSEG4E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2)
  .value("PseudoVLSEG4E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2_MASK)
  .value("PseudoVLSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1)
  .value("PseudoVLSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1_MASK)
  .value("PseudoVLSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2)
  .value("PseudoVLSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2_MASK)
  .value("PseudoVLSEG4E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1)
  .value("PseudoVLSEG4E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1_MASK)
  .value("PseudoVLSEG4E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2)
  .value("PseudoVLSEG4E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2_MASK)
  .value("PseudoVLSEG4E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2)
  .value("PseudoVLSEG4E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2_MASK)
  .value("PseudoVLSEG4E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4)
  .value("PseudoVLSEG4E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4_MASK)
  .value("PseudoVLSEG4E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8)
  .value("PseudoVLSEG4E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8_MASK)
  .value("PseudoVLSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1)
  .value("PseudoVLSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1_MASK)
  .value("PseudoVLSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2)
  .value("PseudoVLSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2_MASK)
  .value("PseudoVLSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2)
  .value("PseudoVLSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2_MASK)
  .value("PseudoVLSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4)
  .value("PseudoVLSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4_MASK)
  .value("PseudoVLSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8)
  .value("PseudoVLSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8_MASK)
  .value("PseudoVLSEG5E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1)
  .value("PseudoVLSEG5E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1_MASK)
  .value("PseudoVLSEG5E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2)
  .value("PseudoVLSEG5E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2_MASK)
  .value("PseudoVLSEG5E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4)
  .value("PseudoVLSEG5E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4_MASK)
  .value("PseudoVLSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1)
  .value("PseudoVLSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1_MASK)
  .value("PseudoVLSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2)
  .value("PseudoVLSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2_MASK)
  .value("PseudoVLSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4)
  .value("PseudoVLSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4_MASK)
  .value("PseudoVLSEG5E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1)
  .value("PseudoVLSEG5E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1_MASK)
  .value("PseudoVLSEG5E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2)
  .value("PseudoVLSEG5E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2_MASK)
  .value("PseudoVLSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1)
  .value("PseudoVLSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1_MASK)
  .value("PseudoVLSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2)
  .value("PseudoVLSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2_MASK)
  .value("PseudoVLSEG5E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1)
  .value("PseudoVLSEG5E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1_MASK)
  .value("PseudoVLSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1)
  .value("PseudoVLSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1_MASK)
  .value("PseudoVLSEG5E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1)
  .value("PseudoVLSEG5E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1_MASK)
  .value("PseudoVLSEG5E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2)
  .value("PseudoVLSEG5E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2_MASK)
  .value("PseudoVLSEG5E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4)
  .value("PseudoVLSEG5E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4_MASK)
  .value("PseudoVLSEG5E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8)
  .value("PseudoVLSEG5E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8_MASK)
  .value("PseudoVLSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1)
  .value("PseudoVLSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1_MASK)
  .value("PseudoVLSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2)
  .value("PseudoVLSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2_MASK)
  .value("PseudoVLSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4)
  .value("PseudoVLSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4_MASK)
  .value("PseudoVLSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8)
  .value("PseudoVLSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8_MASK)
  .value("PseudoVLSEG6E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1)
  .value("PseudoVLSEG6E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1_MASK)
  .value("PseudoVLSEG6E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2)
  .value("PseudoVLSEG6E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2_MASK)
  .value("PseudoVLSEG6E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4)
  .value("PseudoVLSEG6E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4_MASK)
  .value("PseudoVLSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1)
  .value("PseudoVLSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1_MASK)
  .value("PseudoVLSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2)
  .value("PseudoVLSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2_MASK)
  .value("PseudoVLSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4)
  .value("PseudoVLSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4_MASK)
  .value("PseudoVLSEG6E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1)
  .value("PseudoVLSEG6E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1_MASK)
  .value("PseudoVLSEG6E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2)
  .value("PseudoVLSEG6E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2_MASK)
  .value("PseudoVLSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1)
  .value("PseudoVLSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1_MASK)
  .value("PseudoVLSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2)
  .value("PseudoVLSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2_MASK)
  .value("PseudoVLSEG6E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1)
  .value("PseudoVLSEG6E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1_MASK)
  .value("PseudoVLSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1)
  .value("PseudoVLSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1_MASK)
  .value("PseudoVLSEG6E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1)
  .value("PseudoVLSEG6E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1_MASK)
  .value("PseudoVLSEG6E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2)
  .value("PseudoVLSEG6E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2_MASK)
  .value("PseudoVLSEG6E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4)
  .value("PseudoVLSEG6E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4_MASK)
  .value("PseudoVLSEG6E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8)
  .value("PseudoVLSEG6E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8_MASK)
  .value("PseudoVLSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1)
  .value("PseudoVLSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1_MASK)
  .value("PseudoVLSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2)
  .value("PseudoVLSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2_MASK)
  .value("PseudoVLSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4)
  .value("PseudoVLSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4_MASK)
  .value("PseudoVLSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8)
  .value("PseudoVLSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8_MASK)
  .value("PseudoVLSEG7E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1)
  .value("PseudoVLSEG7E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1_MASK)
  .value("PseudoVLSEG7E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2)
  .value("PseudoVLSEG7E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2_MASK)
  .value("PseudoVLSEG7E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4)
  .value("PseudoVLSEG7E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4_MASK)
  .value("PseudoVLSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1)
  .value("PseudoVLSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1_MASK)
  .value("PseudoVLSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2)
  .value("PseudoVLSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2_MASK)
  .value("PseudoVLSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4)
  .value("PseudoVLSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4_MASK)
  .value("PseudoVLSEG7E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1)
  .value("PseudoVLSEG7E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1_MASK)
  .value("PseudoVLSEG7E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2)
  .value("PseudoVLSEG7E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2_MASK)
  .value("PseudoVLSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1)
  .value("PseudoVLSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1_MASK)
  .value("PseudoVLSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2)
  .value("PseudoVLSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2_MASK)
  .value("PseudoVLSEG7E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1)
  .value("PseudoVLSEG7E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1_MASK)
  .value("PseudoVLSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1)
  .value("PseudoVLSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1_MASK)
  .value("PseudoVLSEG7E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1)
  .value("PseudoVLSEG7E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1_MASK)
  .value("PseudoVLSEG7E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2)
  .value("PseudoVLSEG7E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2_MASK)
  .value("PseudoVLSEG7E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4)
  .value("PseudoVLSEG7E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4_MASK)
  .value("PseudoVLSEG7E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8)
  .value("PseudoVLSEG7E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8_MASK)
  .value("PseudoVLSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1)
  .value("PseudoVLSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1_MASK)
  .value("PseudoVLSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2)
  .value("PseudoVLSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2_MASK)
  .value("PseudoVLSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4)
  .value("PseudoVLSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4_MASK)
  .value("PseudoVLSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8)
  .value("PseudoVLSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8_MASK)
  .value("PseudoVLSEG8E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1)
  .value("PseudoVLSEG8E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1_MASK)
  .value("PseudoVLSEG8E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2)
  .value("PseudoVLSEG8E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2_MASK)
  .value("PseudoVLSEG8E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4)
  .value("PseudoVLSEG8E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4_MASK)
  .value("PseudoVLSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1)
  .value("PseudoVLSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1_MASK)
  .value("PseudoVLSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2)
  .value("PseudoVLSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2_MASK)
  .value("PseudoVLSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4)
  .value("PseudoVLSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4_MASK)
  .value("PseudoVLSEG8E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1)
  .value("PseudoVLSEG8E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1_MASK)
  .value("PseudoVLSEG8E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2)
  .value("PseudoVLSEG8E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2_MASK)
  .value("PseudoVLSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1)
  .value("PseudoVLSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1_MASK)
  .value("PseudoVLSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2)
  .value("PseudoVLSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2_MASK)
  .value("PseudoVLSEG8E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1)
  .value("PseudoVLSEG8E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1_MASK)
  .value("PseudoVLSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1)
  .value("PseudoVLSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1_MASK)
  .value("PseudoVLSEG8E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1)
  .value("PseudoVLSEG8E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1_MASK)
  .value("PseudoVLSEG8E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2)
  .value("PseudoVLSEG8E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2_MASK)
  .value("PseudoVLSEG8E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4)
  .value("PseudoVLSEG8E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4_MASK)
  .value("PseudoVLSEG8E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8)
  .value("PseudoVLSEG8E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8_MASK)
  .value("PseudoVLSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1)
  .value("PseudoVLSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1_MASK)
  .value("PseudoVLSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2)
  .value("PseudoVLSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2_MASK)
  .value("PseudoVLSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4)
  .value("PseudoVLSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4_MASK)
  .value("PseudoVLSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8)
  .value("PseudoVLSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8_MASK)
  .value("PseudoVLSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1)
  .value("PseudoVLSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1_MASK)
  .value("PseudoVLSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2)
  .value("PseudoVLSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2_MASK)
  .value("PseudoVLSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4)
  .value("PseudoVLSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4_MASK)
  .value("PseudoVLSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2)
  .value("PseudoVLSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2_MASK)
  .value("PseudoVLSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4)
  .value("PseudoVLSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4_MASK)
  .value("PseudoVLSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1)
  .value("PseudoVLSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1_MASK)
  .value("PseudoVLSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2)
  .value("PseudoVLSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2_MASK)
  .value("PseudoVLSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4)
  .value("PseudoVLSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4_MASK)
  .value("PseudoVLSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2)
  .value("PseudoVLSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2_MASK)
  .value("PseudoVLSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1)
  .value("PseudoVLSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1_MASK)
  .value("PseudoVLSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2)
  .value("PseudoVLSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2_MASK)
  .value("PseudoVLSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4)
  .value("PseudoVLSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4_MASK)
  .value("PseudoVLSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1)
  .value("PseudoVLSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1_MASK);
  opcodes.value("PseudoVLSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2)
  .value("PseudoVLSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2_MASK)
  .value("PseudoVLSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4)
  .value("PseudoVLSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4_MASK)
  .value("PseudoVLSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2)
  .value("PseudoVLSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2_MASK)
  .value("PseudoVLSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4)
  .value("PseudoVLSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4_MASK)
  .value("PseudoVLSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8)
  .value("PseudoVLSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8_MASK)
  .value("PseudoVLSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1)
  .value("PseudoVLSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1_MASK)
  .value("PseudoVLSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2)
  .value("PseudoVLSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2_MASK)
  .value("PseudoVLSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2)
  .value("PseudoVLSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2_MASK)
  .value("PseudoVLSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4)
  .value("PseudoVLSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4_MASK)
  .value("PseudoVLSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1)
  .value("PseudoVLSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1_MASK)
  .value("PseudoVLSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2)
  .value("PseudoVLSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2_MASK)
  .value("PseudoVLSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2)
  .value("PseudoVLSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2_MASK)
  .value("PseudoVLSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1)
  .value("PseudoVLSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1_MASK)
  .value("PseudoVLSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2)
  .value("PseudoVLSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2_MASK)
  .value("PseudoVLSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1)
  .value("PseudoVLSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1_MASK)
  .value("PseudoVLSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2)
  .value("PseudoVLSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2_MASK)
  .value("PseudoVLSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2)
  .value("PseudoVLSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2_MASK)
  .value("PseudoVLSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4)
  .value("PseudoVLSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4_MASK)
  .value("PseudoVLSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8)
  .value("PseudoVLSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8_MASK)
  .value("PseudoVLSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1)
  .value("PseudoVLSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1_MASK)
  .value("PseudoVLSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2)
  .value("PseudoVLSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2_MASK)
  .value("PseudoVLSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2)
  .value("PseudoVLSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2_MASK)
  .value("PseudoVLSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4)
  .value("PseudoVLSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4_MASK)
  .value("PseudoVLSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1)
  .value("PseudoVLSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1_MASK)
  .value("PseudoVLSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2)
  .value("PseudoVLSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2_MASK)
  .value("PseudoVLSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2)
  .value("PseudoVLSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2_MASK)
  .value("PseudoVLSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1)
  .value("PseudoVLSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1_MASK)
  .value("PseudoVLSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2)
  .value("PseudoVLSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2_MASK)
  .value("PseudoVLSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1)
  .value("PseudoVLSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1_MASK)
  .value("PseudoVLSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2)
  .value("PseudoVLSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2_MASK)
  .value("PseudoVLSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2)
  .value("PseudoVLSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2_MASK)
  .value("PseudoVLSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4)
  .value("PseudoVLSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4_MASK)
  .value("PseudoVLSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8)
  .value("PseudoVLSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8_MASK)
  .value("PseudoVLSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1)
  .value("PseudoVLSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1_MASK)
  .value("PseudoVLSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2)
  .value("PseudoVLSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2_MASK)
  .value("PseudoVLSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4)
  .value("PseudoVLSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4_MASK)
  .value("PseudoVLSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1)
  .value("PseudoVLSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1_MASK)
  .value("PseudoVLSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2)
  .value("PseudoVLSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2_MASK)
  .value("PseudoVLSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1)
  .value("PseudoVLSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1_MASK)
  .value("PseudoVLSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1)
  .value("PseudoVLSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1_MASK)
  .value("PseudoVLSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2)
  .value("PseudoVLSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2_MASK)
  .value("PseudoVLSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4)
  .value("PseudoVLSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4_MASK)
  .value("PseudoVLSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8)
  .value("PseudoVLSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8_MASK)
  .value("PseudoVLSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1)
  .value("PseudoVLSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1_MASK)
  .value("PseudoVLSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2)
  .value("PseudoVLSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2_MASK)
  .value("PseudoVLSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4)
  .value("PseudoVLSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4_MASK)
  .value("PseudoVLSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1)
  .value("PseudoVLSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1_MASK)
  .value("PseudoVLSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2)
  .value("PseudoVLSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2_MASK)
  .value("PseudoVLSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1)
  .value("PseudoVLSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1_MASK)
  .value("PseudoVLSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1)
  .value("PseudoVLSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1_MASK)
  .value("PseudoVLSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2)
  .value("PseudoVLSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2_MASK)
  .value("PseudoVLSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4)
  .value("PseudoVLSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4_MASK)
  .value("PseudoVLSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8)
  .value("PseudoVLSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8_MASK)
  .value("PseudoVLSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1)
  .value("PseudoVLSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1_MASK)
  .value("PseudoVLSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2)
  .value("PseudoVLSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2_MASK)
  .value("PseudoVLSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4)
  .value("PseudoVLSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4_MASK)
  .value("PseudoVLSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1)
  .value("PseudoVLSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1_MASK)
  .value("PseudoVLSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2)
  .value("PseudoVLSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2_MASK)
  .value("PseudoVLSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1)
  .value("PseudoVLSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1_MASK)
  .value("PseudoVLSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1)
  .value("PseudoVLSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1_MASK)
  .value("PseudoVLSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2)
  .value("PseudoVLSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2_MASK)
  .value("PseudoVLSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4)
  .value("PseudoVLSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4_MASK)
  .value("PseudoVLSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8)
  .value("PseudoVLSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8_MASK)
  .value("PseudoVLSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1)
  .value("PseudoVLSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1_MASK)
  .value("PseudoVLSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2)
  .value("PseudoVLSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2_MASK)
  .value("PseudoVLSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4)
  .value("PseudoVLSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4_MASK)
  .value("PseudoVLSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1)
  .value("PseudoVLSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1_MASK)
  .value("PseudoVLSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2)
  .value("PseudoVLSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2_MASK)
  .value("PseudoVLSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1)
  .value("PseudoVLSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1_MASK)
  .value("PseudoVLSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1)
  .value("PseudoVLSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1_MASK)
  .value("PseudoVLSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2)
  .value("PseudoVLSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2_MASK)
  .value("PseudoVLSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4)
  .value("PseudoVLSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4_MASK)
  .value("PseudoVLSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8)
  .value("PseudoVLSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8_MASK)
  .value("PseudoVLUXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1)
  .value("PseudoVLUXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1_MASK)
  .value("PseudoVLUXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2)
  .value("PseudoVLUXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2_MASK)
  .value("PseudoVLUXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4)
  .value("PseudoVLUXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4_MASK)
  .value("PseudoVLUXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2)
  .value("PseudoVLUXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2_MASK)
  .value("PseudoVLUXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1)
  .value("PseudoVLUXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1_MASK)
  .value("PseudoVLUXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2)
  .value("PseudoVLUXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2_MASK)
  .value("PseudoVLUXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4)
  .value("PseudoVLUXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4_MASK)
  .value("PseudoVLUXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8)
  .value("PseudoVLUXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8_MASK)
  .value("PseudoVLUXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2)
  .value("PseudoVLUXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2_MASK)
  .value("PseudoVLUXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4)
  .value("PseudoVLUXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4_MASK)
  .value("PseudoVLUXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8)
  .value("PseudoVLUXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8_MASK)
  .value("PseudoVLUXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4)
  .value("PseudoVLUXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4_MASK)
  .value("PseudoVLUXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8)
  .value("PseudoVLUXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8_MASK)
  .value("PseudoVLUXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1)
  .value("PseudoVLUXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1_MASK)
  .value("PseudoVLUXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2)
  .value("PseudoVLUXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2_MASK)
  .value("PseudoVLUXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2)
  .value("PseudoVLUXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4)
  .value("PseudoVLUXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1)
  .value("PseudoVLUXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1_MASK)
  .value("PseudoVLUXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2)
  .value("PseudoVLUXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4)
  .value("PseudoVLUXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8)
  .value("PseudoVLUXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1)
  .value("PseudoVLUXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1_MASK)
  .value("PseudoVLUXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2)
  .value("PseudoVLUXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2_MASK)
  .value("PseudoVLUXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2)
  .value("PseudoVLUXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2_MASK)
  .value("PseudoVLUXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4)
  .value("PseudoVLUXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4_MASK)
  .value("PseudoVLUXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1)
  .value("PseudoVLUXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1_MASK)
  .value("PseudoVLUXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2)
  .value("PseudoVLUXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2_MASK)
  .value("PseudoVLUXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4)
  .value("PseudoVLUXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4_MASK)
  .value("PseudoVLUXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2)
  .value("PseudoVLUXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2_MASK)
  .value("PseudoVLUXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1)
  .value("PseudoVLUXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1_MASK)
  .value("PseudoVLUXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2)
  .value("PseudoVLUXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2_MASK)
  .value("PseudoVLUXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4)
  .value("PseudoVLUXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4_MASK)
  .value("PseudoVLUXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8)
  .value("PseudoVLUXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8_MASK)
  .value("PseudoVLUXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2)
  .value("PseudoVLUXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2_MASK)
  .value("PseudoVLUXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4)
  .value("PseudoVLUXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4_MASK)
  .value("PseudoVLUXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8)
  .value("PseudoVLUXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8_MASK)
  .value("PseudoVLUXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1)
  .value("PseudoVLUXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1_MASK)
  .value("PseudoVLUXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2)
  .value("PseudoVLUXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4)
  .value("PseudoVLUXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8)
  .value("PseudoVLUXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1)
  .value("PseudoVLUXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1_MASK)
  .value("PseudoVLUXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2)
  .value("PseudoVLUXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2_MASK)
  .value("PseudoVLUXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4)
  .value("PseudoVLUXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4_MASK)
  .value("PseudoVLUXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8)
  .value("PseudoVLUXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8_MASK)
  .value("PseudoVLUXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1)
  .value("PseudoVLUXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1_MASK)
  .value("PseudoVLUXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2)
  .value("PseudoVLUXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2_MASK)
  .value("PseudoVLUXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2)
  .value("PseudoVLUXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2_MASK)
  .value("PseudoVLUXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4)
  .value("PseudoVLUXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4_MASK)
  .value("PseudoVLUXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1)
  .value("PseudoVLUXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1_MASK)
  .value("PseudoVLUXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2)
  .value("PseudoVLUXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2_MASK)
  .value("PseudoVLUXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4)
  .value("PseudoVLUXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4_MASK)
  .value("PseudoVLUXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2)
  .value("PseudoVLUXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2_MASK)
  .value("PseudoVLUXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1)
  .value("PseudoVLUXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1_MASK)
  .value("PseudoVLUXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2)
  .value("PseudoVLUXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2_MASK)
  .value("PseudoVLUXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4)
  .value("PseudoVLUXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4_MASK)
  .value("PseudoVLUXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8)
  .value("PseudoVLUXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8_MASK)
  .value("PseudoVLUXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1)
  .value("PseudoVLUXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1_MASK)
  .value("PseudoVLUXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2)
  .value("PseudoVLUXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2_MASK)
  .value("PseudoVLUXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4)
  .value("PseudoVLUXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4_MASK)
  .value("PseudoVLUXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8)
  .value("PseudoVLUXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8_MASK)
  .value("PseudoVLUXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2)
  .value("PseudoVLUXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2_MASK)
  .value("PseudoVLUXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4)
  .value("PseudoVLUXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4_MASK)
  .value("PseudoVLUXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8)
  .value("PseudoVLUXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8_MASK)
  .value("PseudoVLUXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4)
  .value("PseudoVLUXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4_MASK)
  .value("PseudoVLUXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8)
  .value("PseudoVLUXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8_MASK)
  .value("PseudoVLUXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8)
  .value("PseudoVLUXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8_MASK)
  .value("PseudoVLUXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1)
  .value("PseudoVLUXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1_MASK)
  .value("PseudoVLUXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2)
  .value("PseudoVLUXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2_MASK)
  .value("PseudoVLUXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4)
  .value("PseudoVLUXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4_MASK)
  .value("PseudoVLUXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2)
  .value("PseudoVLUXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1)
  .value("PseudoVLUXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1_MASK)
  .value("PseudoVLUXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2)
  .value("PseudoVLUXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2_MASK)
  .value("PseudoVLUXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2)
  .value("PseudoVLUXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4)
  .value("PseudoVLUXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1)
  .value("PseudoVLUXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1_MASK)
  .value("PseudoVLUXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2)
  .value("PseudoVLUXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4)
  .value("PseudoVLUXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4_MASK);
  opcodes.value("PseudoVLUXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8)
  .value("PseudoVLUXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1)
  .value("PseudoVLUXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2)
  .value("PseudoVLUXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2_MASK)
  .value("PseudoVLUXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4)
  .value("PseudoVLUXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4_MASK)
  .value("PseudoVLUXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2)
  .value("PseudoVLUXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1)
  .value("PseudoVLUXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2)
  .value("PseudoVLUXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2_MASK)
  .value("PseudoVLUXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4)
  .value("PseudoVLUXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4_MASK)
  .value("PseudoVLUXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2)
  .value("PseudoVLUXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2_MASK)
  .value("PseudoVLUXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4)
  .value("PseudoVLUXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4_MASK)
  .value("PseudoVLUXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4)
  .value("PseudoVLUXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1)
  .value("PseudoVLUXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2)
  .value("PseudoVLUXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1)
  .value("PseudoVLUXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1)
  .value("PseudoVLUXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2)
  .value("PseudoVLUXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2)
  .value("PseudoVLUXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4)
  .value("PseudoVLUXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1)
  .value("PseudoVLUXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2)
  .value("PseudoVLUXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4)
  .value("PseudoVLUXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4_MASK)
  .value("PseudoVLUXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2)
  .value("PseudoVLUXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1)
  .value("PseudoVLUXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2)
  .value("PseudoVLUXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4)
  .value("PseudoVLUXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4_MASK)
  .value("PseudoVLUXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2)
  .value("PseudoVLUXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2_MASK)
  .value("PseudoVLUXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4)
  .value("PseudoVLUXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4_MASK)
  .value("PseudoVLUXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1)
  .value("PseudoVLUXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1)
  .value("PseudoVLUXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2)
  .value("PseudoVLUXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4)
  .value("PseudoVLUXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8)
  .value("PseudoVLUXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1)
  .value("PseudoVLUXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2)
  .value("PseudoVLUXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2)
  .value("PseudoVLUXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4)
  .value("PseudoVLUXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1)
  .value("PseudoVLUXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2)
  .value("PseudoVLUXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4)
  .value("PseudoVLUXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4_MASK)
  .value("PseudoVLUXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2)
  .value("PseudoVLUXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1)
  .value("PseudoVLUXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2)
  .value("PseudoVLUXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2_MASK)
  .value("PseudoVLUXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4)
  .value("PseudoVLUXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4_MASK)
  .value("PseudoVLUXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1)
  .value("PseudoVLUXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2)
  .value("PseudoVLUXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2_MASK)
  .value("PseudoVLUXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4)
  .value("PseudoVLUXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4_MASK)
  .value("PseudoVLUXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2)
  .value("PseudoVLUXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2_MASK)
  .value("PseudoVLUXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4)
  .value("PseudoVLUXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4_MASK)
  .value("PseudoVLUXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4)
  .value("PseudoVLUXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1)
  .value("PseudoVLUXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2)
  .value("PseudoVLUXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4)
  .value("PseudoVLUXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1)
  .value("PseudoVLUXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2)
  .value("PseudoVLUXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1)
  .value("PseudoVLUXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1)
  .value("PseudoVLUXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2)
  .value("PseudoVLUXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2_MASK)
  .value("PseudoVLUXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2)
  .value("PseudoVLUXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1)
  .value("PseudoVLUXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2)
  .value("PseudoVLUXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2_MASK)
  .value("PseudoVLUXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2)
  .value("PseudoVLUXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1)
  .value("PseudoVLUXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2)
  .value("PseudoVLUXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1)
  .value("PseudoVLUXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1)
  .value("PseudoVLUXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2)
  .value("PseudoVLUXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2_MASK)
  .value("PseudoVLUXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2)
  .value("PseudoVLUXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4)
  .value("PseudoVLUXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1)
  .value("PseudoVLUXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2)
  .value("PseudoVLUXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2_MASK)
  .value("PseudoVLUXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2)
  .value("PseudoVLUXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1)
  .value("PseudoVLUXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2)
  .value("PseudoVLUXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2_MASK)
  .value("PseudoVLUXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2)
  .value("PseudoVLUXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2_MASK)
  .value("PseudoVLUXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1)
  .value("PseudoVLUXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1)
  .value("PseudoVLUXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2)
  .value("PseudoVLUXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4)
  .value("PseudoVLUXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8)
  .value("PseudoVLUXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1)
  .value("PseudoVLUXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2)
  .value("PseudoVLUXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2_MASK)
  .value("PseudoVLUXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2)
  .value("PseudoVLUXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4)
  .value("PseudoVLUXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1)
  .value("PseudoVLUXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2)
  .value("PseudoVLUXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2_MASK)
  .value("PseudoVLUXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2)
  .value("PseudoVLUXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1)
  .value("PseudoVLUXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2)
  .value("PseudoVLUXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2_MASK)
  .value("PseudoVLUXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1)
  .value("PseudoVLUXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2)
  .value("PseudoVLUXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2_MASK)
  .value("PseudoVLUXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2)
  .value("PseudoVLUXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1)
  .value("PseudoVLUXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2)
  .value("PseudoVLUXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1)
  .value("PseudoVLUXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2)
  .value("PseudoVLUXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1)
  .value("PseudoVLUXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1)
  .value("PseudoVLUXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2)
  .value("PseudoVLUXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2_MASK)
  .value("PseudoVLUXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2)
  .value("PseudoVLUXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1)
  .value("PseudoVLUXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2)
  .value("PseudoVLUXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2_MASK)
  .value("PseudoVLUXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2)
  .value("PseudoVLUXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1)
  .value("PseudoVLUXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2)
  .value("PseudoVLUXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1)
  .value("PseudoVLUXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1)
  .value("PseudoVLUXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2)
  .value("PseudoVLUXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2_MASK)
  .value("PseudoVLUXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2)
  .value("PseudoVLUXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4)
  .value("PseudoVLUXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1)
  .value("PseudoVLUXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2)
  .value("PseudoVLUXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2_MASK)
  .value("PseudoVLUXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2)
  .value("PseudoVLUXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1)
  .value("PseudoVLUXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2)
  .value("PseudoVLUXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2_MASK)
  .value("PseudoVLUXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2)
  .value("PseudoVLUXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2_MASK)
  .value("PseudoVLUXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1)
  .value("PseudoVLUXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK);
  opcodes.value("PseudoVLUXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1)
  .value("PseudoVLUXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2)
  .value("PseudoVLUXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4)
  .value("PseudoVLUXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8)
  .value("PseudoVLUXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1)
  .value("PseudoVLUXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2)
  .value("PseudoVLUXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2_MASK)
  .value("PseudoVLUXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2)
  .value("PseudoVLUXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4)
  .value("PseudoVLUXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1)
  .value("PseudoVLUXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2)
  .value("PseudoVLUXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2_MASK)
  .value("PseudoVLUXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2)
  .value("PseudoVLUXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1)
  .value("PseudoVLUXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2)
  .value("PseudoVLUXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2_MASK)
  .value("PseudoVLUXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1)
  .value("PseudoVLUXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2)
  .value("PseudoVLUXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2_MASK)
  .value("PseudoVLUXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2)
  .value("PseudoVLUXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1)
  .value("PseudoVLUXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2)
  .value("PseudoVLUXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1)
  .value("PseudoVLUXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2)
  .value("PseudoVLUXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1)
  .value("PseudoVLUXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1)
  .value("PseudoVLUXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2)
  .value("PseudoVLUXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1)
  .value("PseudoVLUXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1)
  .value("PseudoVLUXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1)
  .value("PseudoVLUXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1)
  .value("PseudoVLUXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2)
  .value("PseudoVLUXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4)
  .value("PseudoVLUXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1)
  .value("PseudoVLUXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2)
  .value("PseudoVLUXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1)
  .value("PseudoVLUXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1)
  .value("PseudoVLUXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1)
  .value("PseudoVLUXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2)
  .value("PseudoVLUXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4)
  .value("PseudoVLUXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8)
  .value("PseudoVLUXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1)
  .value("PseudoVLUXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2)
  .value("PseudoVLUXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4)
  .value("PseudoVLUXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1)
  .value("PseudoVLUXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2)
  .value("PseudoVLUXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1)
  .value("PseudoVLUXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1)
  .value("PseudoVLUXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1)
  .value("PseudoVLUXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1)
  .value("PseudoVLUXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1)
  .value("PseudoVLUXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1)
  .value("PseudoVLUXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2)
  .value("PseudoVLUXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1)
  .value("PseudoVLUXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1)
  .value("PseudoVLUXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1)
  .value("PseudoVLUXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1)
  .value("PseudoVLUXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2)
  .value("PseudoVLUXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4)
  .value("PseudoVLUXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1)
  .value("PseudoVLUXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2)
  .value("PseudoVLUXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1)
  .value("PseudoVLUXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1)
  .value("PseudoVLUXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1)
  .value("PseudoVLUXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2)
  .value("PseudoVLUXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4)
  .value("PseudoVLUXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8)
  .value("PseudoVLUXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1)
  .value("PseudoVLUXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2)
  .value("PseudoVLUXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4)
  .value("PseudoVLUXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1)
  .value("PseudoVLUXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2)
  .value("PseudoVLUXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1)
  .value("PseudoVLUXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1)
  .value("PseudoVLUXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1)
  .value("PseudoVLUXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1)
  .value("PseudoVLUXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1)
  .value("PseudoVLUXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1)
  .value("PseudoVLUXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1_MASK)
  .value("PseudoVLUXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2)
  .value("PseudoVLUXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1)
  .value("PseudoVLUXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1)
  .value("PseudoVLUXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1)
  .value("PseudoVLUXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1)
  .value("PseudoVLUXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2)
  .value("PseudoVLUXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4)
  .value("PseudoVLUXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1)
  .value("PseudoVLUXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2)
  .value("PseudoVLUXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1)
  .value("PseudoVLUXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1)
  .value("PseudoVLUXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1)
  .value("PseudoVLUXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2)
  .value("PseudoVLUXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4)
  .value("PseudoVLUXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8)
  .value("PseudoVLUXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1)
  .value("PseudoVLUXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2)
  .value("PseudoVLUXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4)
  .value("PseudoVLUXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1)
  .value("PseudoVLUXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2)
  .value("PseudoVLUXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1)
  .value("PseudoVLUXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1)
  .value("PseudoVLUXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1)
  .value("PseudoVLUXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1)
  .value("PseudoVLUXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1)
  .value("PseudoVLUXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK)
  .value("PseudoVLUXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1)
  .value("PseudoVLUXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1_MASK);
  opcodes.value("PseudoVLUXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2)
  .value("PseudoVLUXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1)
  .value("PseudoVLUXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1)
  .value("PseudoVLUXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2)
  .value("PseudoVLUXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4)
  .value("PseudoVLUXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1)
  .value("PseudoVLUXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8)
  .value("PseudoVLUXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK)
  .value("PseudoVLUXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1)
  .value("PseudoVLUXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1_MASK)
  .value("PseudoVLUXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2)
  .value("PseudoVLUXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4)
  .value("PseudoVLUXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1)
  .value("PseudoVLUXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1_MASK)
  .value("PseudoVLUXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2)
  .value("PseudoVLUXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1)
  .value("PseudoVLUXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1_MASK)
  .value("PseudoVLUXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1)
  .value("PseudoVLUXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8)
  .value("PseudoVLUXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK)
  .value("PseudoVLUXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1)
  .value("PseudoVLUXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1_MASK)
  .value("PseudoVLUXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2)
  .value("PseudoVLUXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2_MASK)
  .value("PseudoVLUXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4)
  .value("PseudoVLUXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4_MASK)
  .value("PseudoVLUXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8)
  .value("PseudoVLUXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8_MASK)
  .value("PseudoVLUXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1)
  .value("PseudoVLUXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1_MASK)
  .value("PseudoVLUXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2)
  .value("PseudoVLUXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2_MASK)
  .value("PseudoVLUXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4)
  .value("PseudoVLUXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4_MASK)
  .value("PseudoVLUXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1)
  .value("PseudoVLUXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1_MASK)
  .value("PseudoVLUXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2)
  .value("PseudoVLUXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2_MASK)
  .value("PseudoVLUXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1)
  .value("PseudoVLUXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1_MASK)
  .value("PseudoVLUXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1)
  .value("PseudoVLUXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1)
  .value("PseudoVLUXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2)
  .value("PseudoVLUXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1)
  .value("PseudoVLUXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2)
  .value("PseudoVLUXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4)
  .value("PseudoVLUXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1)
  .value("PseudoVLUXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8)
  .value("PseudoVLUXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK)
  .value("PseudoVMACC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1)
  .value("PseudoVMACC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1_MASK)
  .value("PseudoVMACC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2)
  .value("PseudoVMACC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2_MASK)
  .value("PseudoVMACC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4)
  .value("PseudoVMACC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4_MASK)
  .value("PseudoVMACC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8)
  .value("PseudoVMACC_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8_MASK)
  .value("PseudoVMACC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2)
  .value("PseudoVMACC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2_MASK)
  .value("PseudoVMACC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4)
  .value("PseudoVMACC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4_MASK)
  .value("PseudoVMACC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8)
  .value("PseudoVMACC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8_MASK)
  .value("PseudoVMACC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1)
  .value("PseudoVMACC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1_MASK)
  .value("PseudoVMACC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2)
  .value("PseudoVMACC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2_MASK)
  .value("PseudoVMACC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4)
  .value("PseudoVMACC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4_MASK)
  .value("PseudoVMACC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8)
  .value("PseudoVMACC_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8_MASK)
  .value("PseudoVMACC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2)
  .value("PseudoVMACC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2_MASK)
  .value("PseudoVMACC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4)
  .value("PseudoVMACC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4_MASK)
  .value("PseudoVMACC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8)
  .value("PseudoVMACC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8_MASK)
  .value("PseudoVMADC_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M1)
  .value("PseudoVMADC_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M2)
  .value("PseudoVMADC_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M4)
  .value("PseudoVMADC_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M8)
  .value("PseudoVMADC_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF2)
  .value("PseudoVMADC_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF4)
  .value("PseudoVMADC_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF8)
  .value("PseudoVMADC_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M1)
  .value("PseudoVMADC_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M2)
  .value("PseudoVMADC_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M4)
  .value("PseudoVMADC_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M8)
  .value("PseudoVMADC_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF2)
  .value("PseudoVMADC_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF4)
  .value("PseudoVMADC_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF8)
  .value("PseudoVMADC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M1)
  .value("PseudoVMADC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M2)
  .value("PseudoVMADC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M4)
  .value("PseudoVMADC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M8)
  .value("PseudoVMADC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF2)
  .value("PseudoVMADC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF4)
  .value("PseudoVMADC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF8)
  .value("PseudoVMADC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M1)
  .value("PseudoVMADC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M2)
  .value("PseudoVMADC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M4)
  .value("PseudoVMADC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M8)
  .value("PseudoVMADC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF2)
  .value("PseudoVMADC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF4)
  .value("PseudoVMADC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF8)
  .value("PseudoVMADC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M1)
  .value("PseudoVMADC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M2)
  .value("PseudoVMADC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M4)
  .value("PseudoVMADC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M8)
  .value("PseudoVMADC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF2)
  .value("PseudoVMADC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF4)
  .value("PseudoVMADC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF8)
  .value("PseudoVMADC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M1)
  .value("PseudoVMADC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M2)
  .value("PseudoVMADC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M4)
  .value("PseudoVMADC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M8)
  .value("PseudoVMADC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF2)
  .value("PseudoVMADC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF4)
  .value("PseudoVMADC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF8)
  .value("PseudoVMADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1)
  .value("PseudoVMADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1_MASK)
  .value("PseudoVMADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2)
  .value("PseudoVMADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2_MASK)
  .value("PseudoVMADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4)
  .value("PseudoVMADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4_MASK)
  .value("PseudoVMADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8)
  .value("PseudoVMADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8_MASK)
  .value("PseudoVMADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2)
  .value("PseudoVMADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2_MASK)
  .value("PseudoVMADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4)
  .value("PseudoVMADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4_MASK)
  .value("PseudoVMADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8)
  .value("PseudoVMADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8_MASK)
  .value("PseudoVMADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1)
  .value("PseudoVMADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1_MASK)
  .value("PseudoVMADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2)
  .value("PseudoVMADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2_MASK)
  .value("PseudoVMADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4)
  .value("PseudoVMADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4_MASK)
  .value("PseudoVMADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8)
  .value("PseudoVMADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8_MASK)
  .value("PseudoVMADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2)
  .value("PseudoVMADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2_MASK)
  .value("PseudoVMADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4)
  .value("PseudoVMADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4_MASK)
  .value("PseudoVMADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8)
  .value("PseudoVMADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8_MASK)
  .value("PseudoVMANDN_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M1)
  .value("PseudoVMANDN_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M2)
  .value("PseudoVMANDN_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M4)
  .value("PseudoVMANDN_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M8)
  .value("PseudoVMANDN_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF2)
  .value("PseudoVMANDN_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF4)
  .value("PseudoVMANDN_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF8)
  .value("PseudoVMAND_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M1)
  .value("PseudoVMAND_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M2)
  .value("PseudoVMAND_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M4)
  .value("PseudoVMAND_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M8)
  .value("PseudoVMAND_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF2)
  .value("PseudoVMAND_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF4)
  .value("PseudoVMAND_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF8)
  .value("PseudoVMAXU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1)
  .value("PseudoVMAXU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1_MASK)
  .value("PseudoVMAXU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2)
  .value("PseudoVMAXU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2_MASK)
  .value("PseudoVMAXU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4)
  .value("PseudoVMAXU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4_MASK)
  .value("PseudoVMAXU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8)
  .value("PseudoVMAXU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8_MASK)
  .value("PseudoVMAXU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2)
  .value("PseudoVMAXU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2_MASK)
  .value("PseudoVMAXU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4)
  .value("PseudoVMAXU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4_MASK)
  .value("PseudoVMAXU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8)
  .value("PseudoVMAXU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8_MASK)
  .value("PseudoVMAXU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1)
  .value("PseudoVMAXU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1_MASK)
  .value("PseudoVMAXU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2)
  .value("PseudoVMAXU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2_MASK)
  .value("PseudoVMAXU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4)
  .value("PseudoVMAXU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4_MASK)
  .value("PseudoVMAXU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8)
  .value("PseudoVMAXU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8_MASK)
  .value("PseudoVMAXU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2)
  .value("PseudoVMAXU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2_MASK)
  .value("PseudoVMAXU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4)
  .value("PseudoVMAXU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4_MASK)
  .value("PseudoVMAXU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8)
  .value("PseudoVMAXU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8_MASK)
  .value("PseudoVMAX_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1)
  .value("PseudoVMAX_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1_MASK)
  .value("PseudoVMAX_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2)
  .value("PseudoVMAX_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2_MASK)
  .value("PseudoVMAX_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4)
  .value("PseudoVMAX_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4_MASK)
  .value("PseudoVMAX_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8)
  .value("PseudoVMAX_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8_MASK)
  .value("PseudoVMAX_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2)
  .value("PseudoVMAX_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2_MASK)
  .value("PseudoVMAX_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4)
  .value("PseudoVMAX_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4_MASK)
  .value("PseudoVMAX_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8)
  .value("PseudoVMAX_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8_MASK)
  .value("PseudoVMAX_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1)
  .value("PseudoVMAX_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1_MASK)
  .value("PseudoVMAX_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2)
  .value("PseudoVMAX_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2_MASK)
  .value("PseudoVMAX_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4)
  .value("PseudoVMAX_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4_MASK)
  .value("PseudoVMAX_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8)
  .value("PseudoVMAX_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8_MASK)
  .value("PseudoVMAX_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2)
  .value("PseudoVMAX_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2_MASK)
  .value("PseudoVMAX_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4)
  .value("PseudoVMAX_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4_MASK)
  .value("PseudoVMAX_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8)
  .value("PseudoVMAX_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8_MASK)
  .value("PseudoVMCLR_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B1)
  .value("PseudoVMCLR_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B16)
  .value("PseudoVMCLR_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B2)
  .value("PseudoVMCLR_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B32)
  .value("PseudoVMCLR_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B4)
  .value("PseudoVMCLR_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B64)
  .value("PseudoVMCLR_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B8)
  .value("PseudoVMERGE_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M1)
  .value("PseudoVMERGE_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M2)
  .value("PseudoVMERGE_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M4)
  .value("PseudoVMERGE_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M8)
  .value("PseudoVMERGE_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF2)
  .value("PseudoVMERGE_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF4)
  .value("PseudoVMERGE_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF8)
  .value("PseudoVMERGE_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M1)
  .value("PseudoVMERGE_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M2)
  .value("PseudoVMERGE_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M4)
  .value("PseudoVMERGE_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M8)
  .value("PseudoVMERGE_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF2)
  .value("PseudoVMERGE_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF4)
  .value("PseudoVMERGE_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF8)
  .value("PseudoVMERGE_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M1)
  .value("PseudoVMERGE_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M2)
  .value("PseudoVMERGE_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M4)
  .value("PseudoVMERGE_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M8)
  .value("PseudoVMERGE_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF2)
  .value("PseudoVMERGE_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF4)
  .value("PseudoVMERGE_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF8)
  .value("PseudoVMFEQ_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1)
  .value("PseudoVMFEQ_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1_MASK)
  .value("PseudoVMFEQ_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2)
  .value("PseudoVMFEQ_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2_MASK)
  .value("PseudoVMFEQ_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4)
  .value("PseudoVMFEQ_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4_MASK)
  .value("PseudoVMFEQ_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8)
  .value("PseudoVMFEQ_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8_MASK)
  .value("PseudoVMFEQ_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2)
  .value("PseudoVMFEQ_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2_MASK)
  .value("PseudoVMFEQ_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4)
  .value("PseudoVMFEQ_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4_MASK)
  .value("PseudoVMFEQ_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1)
  .value("PseudoVMFEQ_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1_MASK)
  .value("PseudoVMFEQ_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2)
  .value("PseudoVMFEQ_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2_MASK)
  .value("PseudoVMFEQ_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4)
  .value("PseudoVMFEQ_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4_MASK)
  .value("PseudoVMFEQ_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8)
  .value("PseudoVMFEQ_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8_MASK)
  .value("PseudoVMFEQ_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2)
  .value("PseudoVMFEQ_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2_MASK)
  .value("PseudoVMFEQ_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1)
  .value("PseudoVMFEQ_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1_MASK)
  .value("PseudoVMFEQ_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2)
  .value("PseudoVMFEQ_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2_MASK);
  opcodes.value("PseudoVMFEQ_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4)
  .value("PseudoVMFEQ_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4_MASK)
  .value("PseudoVMFEQ_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8)
  .value("PseudoVMFEQ_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8_MASK)
  .value("PseudoVMFEQ_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1)
  .value("PseudoVMFEQ_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1_MASK)
  .value("PseudoVMFEQ_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2)
  .value("PseudoVMFEQ_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2_MASK)
  .value("PseudoVMFEQ_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4)
  .value("PseudoVMFEQ_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4_MASK)
  .value("PseudoVMFEQ_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8)
  .value("PseudoVMFEQ_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8_MASK)
  .value("PseudoVMFEQ_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2)
  .value("PseudoVMFEQ_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2_MASK)
  .value("PseudoVMFEQ_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4)
  .value("PseudoVMFEQ_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4_MASK)
  .value("PseudoVMFGE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1)
  .value("PseudoVMFGE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1_MASK)
  .value("PseudoVMFGE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2)
  .value("PseudoVMFGE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2_MASK)
  .value("PseudoVMFGE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4)
  .value("PseudoVMFGE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4_MASK)
  .value("PseudoVMFGE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8)
  .value("PseudoVMFGE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8_MASK)
  .value("PseudoVMFGE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2)
  .value("PseudoVMFGE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2_MASK)
  .value("PseudoVMFGE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4)
  .value("PseudoVMFGE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4_MASK)
  .value("PseudoVMFGE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1)
  .value("PseudoVMFGE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1_MASK)
  .value("PseudoVMFGE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2)
  .value("PseudoVMFGE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2_MASK)
  .value("PseudoVMFGE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4)
  .value("PseudoVMFGE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4_MASK)
  .value("PseudoVMFGE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8)
  .value("PseudoVMFGE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8_MASK)
  .value("PseudoVMFGE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2)
  .value("PseudoVMFGE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2_MASK)
  .value("PseudoVMFGE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1)
  .value("PseudoVMFGE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1_MASK)
  .value("PseudoVMFGE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2)
  .value("PseudoVMFGE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2_MASK)
  .value("PseudoVMFGE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4)
  .value("PseudoVMFGE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4_MASK)
  .value("PseudoVMFGE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8)
  .value("PseudoVMFGE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8_MASK)
  .value("PseudoVMFGT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1)
  .value("PseudoVMFGT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1_MASK)
  .value("PseudoVMFGT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2)
  .value("PseudoVMFGT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2_MASK)
  .value("PseudoVMFGT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4)
  .value("PseudoVMFGT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4_MASK)
  .value("PseudoVMFGT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8)
  .value("PseudoVMFGT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8_MASK)
  .value("PseudoVMFGT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2)
  .value("PseudoVMFGT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2_MASK)
  .value("PseudoVMFGT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4)
  .value("PseudoVMFGT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4_MASK)
  .value("PseudoVMFGT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1)
  .value("PseudoVMFGT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1_MASK)
  .value("PseudoVMFGT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2)
  .value("PseudoVMFGT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2_MASK)
  .value("PseudoVMFGT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4)
  .value("PseudoVMFGT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4_MASK)
  .value("PseudoVMFGT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8)
  .value("PseudoVMFGT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8_MASK)
  .value("PseudoVMFGT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2)
  .value("PseudoVMFGT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2_MASK)
  .value("PseudoVMFGT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1)
  .value("PseudoVMFGT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1_MASK)
  .value("PseudoVMFGT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2)
  .value("PseudoVMFGT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2_MASK)
  .value("PseudoVMFGT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4)
  .value("PseudoVMFGT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4_MASK)
  .value("PseudoVMFGT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8)
  .value("PseudoVMFGT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8_MASK)
  .value("PseudoVMFLE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1)
  .value("PseudoVMFLE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1_MASK)
  .value("PseudoVMFLE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2)
  .value("PseudoVMFLE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2_MASK)
  .value("PseudoVMFLE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4)
  .value("PseudoVMFLE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4_MASK)
  .value("PseudoVMFLE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8)
  .value("PseudoVMFLE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8_MASK)
  .value("PseudoVMFLE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2)
  .value("PseudoVMFLE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2_MASK)
  .value("PseudoVMFLE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4)
  .value("PseudoVMFLE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4_MASK)
  .value("PseudoVMFLE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1)
  .value("PseudoVMFLE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1_MASK)
  .value("PseudoVMFLE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2)
  .value("PseudoVMFLE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2_MASK)
  .value("PseudoVMFLE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4)
  .value("PseudoVMFLE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4_MASK)
  .value("PseudoVMFLE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8)
  .value("PseudoVMFLE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8_MASK)
  .value("PseudoVMFLE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2)
  .value("PseudoVMFLE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2_MASK)
  .value("PseudoVMFLE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1)
  .value("PseudoVMFLE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1_MASK)
  .value("PseudoVMFLE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2)
  .value("PseudoVMFLE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2_MASK)
  .value("PseudoVMFLE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4)
  .value("PseudoVMFLE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4_MASK)
  .value("PseudoVMFLE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8)
  .value("PseudoVMFLE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8_MASK)
  .value("PseudoVMFLE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1)
  .value("PseudoVMFLE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1_MASK)
  .value("PseudoVMFLE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2)
  .value("PseudoVMFLE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2_MASK)
  .value("PseudoVMFLE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4)
  .value("PseudoVMFLE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4_MASK)
  .value("PseudoVMFLE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8)
  .value("PseudoVMFLE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8_MASK)
  .value("PseudoVMFLE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2)
  .value("PseudoVMFLE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2_MASK)
  .value("PseudoVMFLE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4)
  .value("PseudoVMFLE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4_MASK)
  .value("PseudoVMFLT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1)
  .value("PseudoVMFLT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1_MASK)
  .value("PseudoVMFLT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2)
  .value("PseudoVMFLT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2_MASK)
  .value("PseudoVMFLT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4)
  .value("PseudoVMFLT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4_MASK)
  .value("PseudoVMFLT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8)
  .value("PseudoVMFLT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8_MASK)
  .value("PseudoVMFLT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2)
  .value("PseudoVMFLT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2_MASK)
  .value("PseudoVMFLT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4)
  .value("PseudoVMFLT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4_MASK)
  .value("PseudoVMFLT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1)
  .value("PseudoVMFLT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1_MASK)
  .value("PseudoVMFLT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2)
  .value("PseudoVMFLT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2_MASK)
  .value("PseudoVMFLT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4)
  .value("PseudoVMFLT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4_MASK)
  .value("PseudoVMFLT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8)
  .value("PseudoVMFLT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8_MASK)
  .value("PseudoVMFLT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2)
  .value("PseudoVMFLT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2_MASK)
  .value("PseudoVMFLT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1)
  .value("PseudoVMFLT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1_MASK)
  .value("PseudoVMFLT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2)
  .value("PseudoVMFLT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2_MASK)
  .value("PseudoVMFLT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4)
  .value("PseudoVMFLT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4_MASK)
  .value("PseudoVMFLT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8)
  .value("PseudoVMFLT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8_MASK)
  .value("PseudoVMFLT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1)
  .value("PseudoVMFLT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1_MASK)
  .value("PseudoVMFLT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2)
  .value("PseudoVMFLT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2_MASK)
  .value("PseudoVMFLT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4)
  .value("PseudoVMFLT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4_MASK)
  .value("PseudoVMFLT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8)
  .value("PseudoVMFLT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8_MASK)
  .value("PseudoVMFLT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2)
  .value("PseudoVMFLT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2_MASK)
  .value("PseudoVMFLT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4)
  .value("PseudoVMFLT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4_MASK)
  .value("PseudoVMFNE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1)
  .value("PseudoVMFNE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1_MASK)
  .value("PseudoVMFNE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2)
  .value("PseudoVMFNE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2_MASK)
  .value("PseudoVMFNE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4)
  .value("PseudoVMFNE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4_MASK)
  .value("PseudoVMFNE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8)
  .value("PseudoVMFNE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8_MASK)
  .value("PseudoVMFNE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2)
  .value("PseudoVMFNE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2_MASK)
  .value("PseudoVMFNE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4)
  .value("PseudoVMFNE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4_MASK)
  .value("PseudoVMFNE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1)
  .value("PseudoVMFNE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1_MASK)
  .value("PseudoVMFNE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2)
  .value("PseudoVMFNE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2_MASK)
  .value("PseudoVMFNE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4)
  .value("PseudoVMFNE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4_MASK)
  .value("PseudoVMFNE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8)
  .value("PseudoVMFNE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8_MASK)
  .value("PseudoVMFNE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2)
  .value("PseudoVMFNE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2_MASK)
  .value("PseudoVMFNE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1)
  .value("PseudoVMFNE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1_MASK)
  .value("PseudoVMFNE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2)
  .value("PseudoVMFNE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2_MASK)
  .value("PseudoVMFNE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4)
  .value("PseudoVMFNE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4_MASK)
  .value("PseudoVMFNE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8)
  .value("PseudoVMFNE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8_MASK)
  .value("PseudoVMFNE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1)
  .value("PseudoVMFNE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1_MASK)
  .value("PseudoVMFNE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2)
  .value("PseudoVMFNE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2_MASK)
  .value("PseudoVMFNE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4)
  .value("PseudoVMFNE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4_MASK)
  .value("PseudoVMFNE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8)
  .value("PseudoVMFNE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8_MASK)
  .value("PseudoVMFNE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2)
  .value("PseudoVMFNE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2_MASK)
  .value("PseudoVMFNE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4)
  .value("PseudoVMFNE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4_MASK)
  .value("PseudoVMINU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1)
  .value("PseudoVMINU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1_MASK)
  .value("PseudoVMINU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2)
  .value("PseudoVMINU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2_MASK)
  .value("PseudoVMINU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4)
  .value("PseudoVMINU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4_MASK)
  .value("PseudoVMINU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8)
  .value("PseudoVMINU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8_MASK)
  .value("PseudoVMINU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2)
  .value("PseudoVMINU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2_MASK)
  .value("PseudoVMINU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4)
  .value("PseudoVMINU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4_MASK)
  .value("PseudoVMINU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8)
  .value("PseudoVMINU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8_MASK)
  .value("PseudoVMINU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1)
  .value("PseudoVMINU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1_MASK)
  .value("PseudoVMINU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2)
  .value("PseudoVMINU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2_MASK)
  .value("PseudoVMINU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4)
  .value("PseudoVMINU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4_MASK)
  .value("PseudoVMINU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8)
  .value("PseudoVMINU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8_MASK)
  .value("PseudoVMINU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2)
  .value("PseudoVMINU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2_MASK)
  .value("PseudoVMINU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4)
  .value("PseudoVMINU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4_MASK)
  .value("PseudoVMINU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8)
  .value("PseudoVMINU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8_MASK)
  .value("PseudoVMIN_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1)
  .value("PseudoVMIN_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1_MASK)
  .value("PseudoVMIN_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2)
  .value("PseudoVMIN_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2_MASK)
  .value("PseudoVMIN_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4)
  .value("PseudoVMIN_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4_MASK)
  .value("PseudoVMIN_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8)
  .value("PseudoVMIN_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8_MASK)
  .value("PseudoVMIN_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2)
  .value("PseudoVMIN_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2_MASK)
  .value("PseudoVMIN_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4)
  .value("PseudoVMIN_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4_MASK)
  .value("PseudoVMIN_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8)
  .value("PseudoVMIN_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8_MASK)
  .value("PseudoVMIN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1)
  .value("PseudoVMIN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1_MASK)
  .value("PseudoVMIN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2)
  .value("PseudoVMIN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2_MASK)
  .value("PseudoVMIN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4)
  .value("PseudoVMIN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4_MASK)
  .value("PseudoVMIN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8)
  .value("PseudoVMIN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8_MASK)
  .value("PseudoVMIN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2)
  .value("PseudoVMIN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2_MASK)
  .value("PseudoVMIN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4)
  .value("PseudoVMIN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4_MASK)
  .value("PseudoVMIN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8)
  .value("PseudoVMIN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8_MASK)
  .value("PseudoVMNAND_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M1)
  .value("PseudoVMNAND_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M2)
  .value("PseudoVMNAND_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M4)
  .value("PseudoVMNAND_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M8)
  .value("PseudoVMNAND_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF2)
  .value("PseudoVMNAND_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF4)
  .value("PseudoVMNAND_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF8)
  .value("PseudoVMNOR_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M1)
  .value("PseudoVMNOR_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M2)
  .value("PseudoVMNOR_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M4)
  .value("PseudoVMNOR_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M8)
  .value("PseudoVMNOR_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF2)
  .value("PseudoVMNOR_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF4)
  .value("PseudoVMNOR_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF8)
  .value("PseudoVMORN_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M1)
  .value("PseudoVMORN_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M2)
  .value("PseudoVMORN_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M4)
  .value("PseudoVMORN_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M8)
  .value("PseudoVMORN_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF2)
  .value("PseudoVMORN_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF4)
  .value("PseudoVMORN_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF8)
  .value("PseudoVMOR_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M1)
  .value("PseudoVMOR_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M2)
  .value("PseudoVMOR_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M4)
  .value("PseudoVMOR_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M8)
  .value("PseudoVMOR_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF2)
  .value("PseudoVMOR_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF4)
  .value("PseudoVMOR_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF8)
  .value("PseudoVMSBC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M1)
  .value("PseudoVMSBC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M2)
  .value("PseudoVMSBC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M4)
  .value("PseudoVMSBC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M8)
  .value("PseudoVMSBC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF2)
  .value("PseudoVMSBC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF4)
  .value("PseudoVMSBC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF8)
  .value("PseudoVMSBC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M1)
  .value("PseudoVMSBC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M2)
  .value("PseudoVMSBC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M4)
  .value("PseudoVMSBC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M8)
  .value("PseudoVMSBC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF2)
  .value("PseudoVMSBC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF4)
  .value("PseudoVMSBC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF8);
  opcodes.value("PseudoVMSBC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M1)
  .value("PseudoVMSBC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M2)
  .value("PseudoVMSBC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M4)
  .value("PseudoVMSBC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M8)
  .value("PseudoVMSBC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF2)
  .value("PseudoVMSBC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF4)
  .value("PseudoVMSBC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF8)
  .value("PseudoVMSBC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M1)
  .value("PseudoVMSBC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M2)
  .value("PseudoVMSBC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M4)
  .value("PseudoVMSBC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M8)
  .value("PseudoVMSBC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF2)
  .value("PseudoVMSBC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF4)
  .value("PseudoVMSBC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF8)
  .value("PseudoVMSBF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1)
  .value("PseudoVMSBF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16)
  .value("PseudoVMSBF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16_MASK)
  .value("PseudoVMSBF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1_MASK)
  .value("PseudoVMSBF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2)
  .value("PseudoVMSBF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2_MASK)
  .value("PseudoVMSBF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32)
  .value("PseudoVMSBF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32_MASK)
  .value("PseudoVMSBF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4)
  .value("PseudoVMSBF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4_MASK)
  .value("PseudoVMSBF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64)
  .value("PseudoVMSBF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64_MASK)
  .value("PseudoVMSBF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8)
  .value("PseudoVMSBF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8_MASK)
  .value("PseudoVMSEQ_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1)
  .value("PseudoVMSEQ_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1_MASK)
  .value("PseudoVMSEQ_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2)
  .value("PseudoVMSEQ_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2_MASK)
  .value("PseudoVMSEQ_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4)
  .value("PseudoVMSEQ_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4_MASK)
  .value("PseudoVMSEQ_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8)
  .value("PseudoVMSEQ_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8_MASK)
  .value("PseudoVMSEQ_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2)
  .value("PseudoVMSEQ_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2_MASK)
  .value("PseudoVMSEQ_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4)
  .value("PseudoVMSEQ_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4_MASK)
  .value("PseudoVMSEQ_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8)
  .value("PseudoVMSEQ_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8_MASK)
  .value("PseudoVMSEQ_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1)
  .value("PseudoVMSEQ_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1_MASK)
  .value("PseudoVMSEQ_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2)
  .value("PseudoVMSEQ_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2_MASK)
  .value("PseudoVMSEQ_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4)
  .value("PseudoVMSEQ_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4_MASK)
  .value("PseudoVMSEQ_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8)
  .value("PseudoVMSEQ_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8_MASK)
  .value("PseudoVMSEQ_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2)
  .value("PseudoVMSEQ_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2_MASK)
  .value("PseudoVMSEQ_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4)
  .value("PseudoVMSEQ_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4_MASK)
  .value("PseudoVMSEQ_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8)
  .value("PseudoVMSEQ_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8_MASK)
  .value("PseudoVMSEQ_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1)
  .value("PseudoVMSEQ_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1_MASK)
  .value("PseudoVMSEQ_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2)
  .value("PseudoVMSEQ_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2_MASK)
  .value("PseudoVMSEQ_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4)
  .value("PseudoVMSEQ_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4_MASK)
  .value("PseudoVMSEQ_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8)
  .value("PseudoVMSEQ_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8_MASK)
  .value("PseudoVMSEQ_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2)
  .value("PseudoVMSEQ_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2_MASK)
  .value("PseudoVMSEQ_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4)
  .value("PseudoVMSEQ_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4_MASK)
  .value("PseudoVMSEQ_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8)
  .value("PseudoVMSEQ_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8_MASK)
  .value("PseudoVMSET_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B1)
  .value("PseudoVMSET_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B16)
  .value("PseudoVMSET_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B2)
  .value("PseudoVMSET_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B32)
  .value("PseudoVMSET_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B4)
  .value("PseudoVMSET_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B64)
  .value("PseudoVMSET_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B8)
  .value("PseudoVMSGEU_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VI)
  .value("PseudoVMSGEU_VX", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX)
  .value("PseudoVMSGEU_VX_M", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M)
  .value("PseudoVMSGEU_VX_M_T", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M_T)
  .value("PseudoVMSGE_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VI)
  .value("PseudoVMSGE_VX", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX)
  .value("PseudoVMSGE_VX_M", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M)
  .value("PseudoVMSGE_VX_M_T", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M_T)
  .value("PseudoVMSGTU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1)
  .value("PseudoVMSGTU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1_MASK)
  .value("PseudoVMSGTU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2)
  .value("PseudoVMSGTU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2_MASK)
  .value("PseudoVMSGTU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4)
  .value("PseudoVMSGTU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4_MASK)
  .value("PseudoVMSGTU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8)
  .value("PseudoVMSGTU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8_MASK)
  .value("PseudoVMSGTU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2)
  .value("PseudoVMSGTU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2_MASK)
  .value("PseudoVMSGTU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4)
  .value("PseudoVMSGTU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4_MASK)
  .value("PseudoVMSGTU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8)
  .value("PseudoVMSGTU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8_MASK)
  .value("PseudoVMSGTU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1)
  .value("PseudoVMSGTU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1_MASK)
  .value("PseudoVMSGTU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2)
  .value("PseudoVMSGTU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2_MASK)
  .value("PseudoVMSGTU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4)
  .value("PseudoVMSGTU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4_MASK)
  .value("PseudoVMSGTU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8)
  .value("PseudoVMSGTU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8_MASK)
  .value("PseudoVMSGTU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2)
  .value("PseudoVMSGTU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2_MASK)
  .value("PseudoVMSGTU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4)
  .value("PseudoVMSGTU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4_MASK)
  .value("PseudoVMSGTU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8)
  .value("PseudoVMSGTU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8_MASK)
  .value("PseudoVMSGT_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1)
  .value("PseudoVMSGT_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1_MASK)
  .value("PseudoVMSGT_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2)
  .value("PseudoVMSGT_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2_MASK)
  .value("PseudoVMSGT_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4)
  .value("PseudoVMSGT_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4_MASK)
  .value("PseudoVMSGT_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8)
  .value("PseudoVMSGT_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8_MASK)
  .value("PseudoVMSGT_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2)
  .value("PseudoVMSGT_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2_MASK)
  .value("PseudoVMSGT_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4)
  .value("PseudoVMSGT_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4_MASK)
  .value("PseudoVMSGT_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8)
  .value("PseudoVMSGT_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8_MASK)
  .value("PseudoVMSGT_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1)
  .value("PseudoVMSGT_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1_MASK)
  .value("PseudoVMSGT_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2)
  .value("PseudoVMSGT_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2_MASK)
  .value("PseudoVMSGT_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4)
  .value("PseudoVMSGT_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4_MASK)
  .value("PseudoVMSGT_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8)
  .value("PseudoVMSGT_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8_MASK)
  .value("PseudoVMSGT_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2)
  .value("PseudoVMSGT_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2_MASK)
  .value("PseudoVMSGT_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4)
  .value("PseudoVMSGT_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4_MASK)
  .value("PseudoVMSGT_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8)
  .value("PseudoVMSGT_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8_MASK)
  .value("PseudoVMSIF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1)
  .value("PseudoVMSIF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16)
  .value("PseudoVMSIF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16_MASK)
  .value("PseudoVMSIF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1_MASK)
  .value("PseudoVMSIF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2)
  .value("PseudoVMSIF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2_MASK)
  .value("PseudoVMSIF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32)
  .value("PseudoVMSIF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32_MASK)
  .value("PseudoVMSIF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4)
  .value("PseudoVMSIF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4_MASK)
  .value("PseudoVMSIF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64)
  .value("PseudoVMSIF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64_MASK)
  .value("PseudoVMSIF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8)
  .value("PseudoVMSIF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8_MASK)
  .value("PseudoVMSLEU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1)
  .value("PseudoVMSLEU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1_MASK)
  .value("PseudoVMSLEU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2)
  .value("PseudoVMSLEU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2_MASK)
  .value("PseudoVMSLEU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4)
  .value("PseudoVMSLEU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4_MASK)
  .value("PseudoVMSLEU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8)
  .value("PseudoVMSLEU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8_MASK)
  .value("PseudoVMSLEU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2)
  .value("PseudoVMSLEU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2_MASK)
  .value("PseudoVMSLEU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4)
  .value("PseudoVMSLEU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4_MASK)
  .value("PseudoVMSLEU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8)
  .value("PseudoVMSLEU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8_MASK)
  .value("PseudoVMSLEU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1)
  .value("PseudoVMSLEU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1_MASK)
  .value("PseudoVMSLEU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2)
  .value("PseudoVMSLEU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2_MASK)
  .value("PseudoVMSLEU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4)
  .value("PseudoVMSLEU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4_MASK)
  .value("PseudoVMSLEU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8)
  .value("PseudoVMSLEU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8_MASK)
  .value("PseudoVMSLEU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2)
  .value("PseudoVMSLEU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2_MASK)
  .value("PseudoVMSLEU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4)
  .value("PseudoVMSLEU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4_MASK)
  .value("PseudoVMSLEU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8)
  .value("PseudoVMSLEU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8_MASK)
  .value("PseudoVMSLEU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1)
  .value("PseudoVMSLEU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1_MASK)
  .value("PseudoVMSLEU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2)
  .value("PseudoVMSLEU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2_MASK)
  .value("PseudoVMSLEU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4)
  .value("PseudoVMSLEU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4_MASK)
  .value("PseudoVMSLEU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8)
  .value("PseudoVMSLEU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8_MASK)
  .value("PseudoVMSLEU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2)
  .value("PseudoVMSLEU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2_MASK)
  .value("PseudoVMSLEU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4)
  .value("PseudoVMSLEU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4_MASK)
  .value("PseudoVMSLEU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8)
  .value("PseudoVMSLEU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8_MASK)
  .value("PseudoVMSLE_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1)
  .value("PseudoVMSLE_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1_MASK)
  .value("PseudoVMSLE_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2)
  .value("PseudoVMSLE_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2_MASK)
  .value("PseudoVMSLE_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4)
  .value("PseudoVMSLE_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4_MASK)
  .value("PseudoVMSLE_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8)
  .value("PseudoVMSLE_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8_MASK)
  .value("PseudoVMSLE_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2)
  .value("PseudoVMSLE_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2_MASK)
  .value("PseudoVMSLE_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4)
  .value("PseudoVMSLE_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4_MASK)
  .value("PseudoVMSLE_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8)
  .value("PseudoVMSLE_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8_MASK)
  .value("PseudoVMSLE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1)
  .value("PseudoVMSLE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1_MASK)
  .value("PseudoVMSLE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2)
  .value("PseudoVMSLE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2_MASK)
  .value("PseudoVMSLE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4)
  .value("PseudoVMSLE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4_MASK)
  .value("PseudoVMSLE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8)
  .value("PseudoVMSLE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8_MASK)
  .value("PseudoVMSLE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2)
  .value("PseudoVMSLE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2_MASK)
  .value("PseudoVMSLE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4)
  .value("PseudoVMSLE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4_MASK)
  .value("PseudoVMSLE_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8)
  .value("PseudoVMSLE_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8_MASK)
  .value("PseudoVMSLE_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1)
  .value("PseudoVMSLE_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1_MASK)
  .value("PseudoVMSLE_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2)
  .value("PseudoVMSLE_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2_MASK)
  .value("PseudoVMSLE_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4)
  .value("PseudoVMSLE_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4_MASK)
  .value("PseudoVMSLE_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8)
  .value("PseudoVMSLE_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8_MASK)
  .value("PseudoVMSLE_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2)
  .value("PseudoVMSLE_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2_MASK)
  .value("PseudoVMSLE_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4)
  .value("PseudoVMSLE_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4_MASK)
  .value("PseudoVMSLE_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8)
  .value("PseudoVMSLE_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8_MASK)
  .value("PseudoVMSLTU_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VI)
  .value("PseudoVMSLTU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1)
  .value("PseudoVMSLTU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1_MASK)
  .value("PseudoVMSLTU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2)
  .value("PseudoVMSLTU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2_MASK)
  .value("PseudoVMSLTU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4)
  .value("PseudoVMSLTU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4_MASK)
  .value("PseudoVMSLTU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8)
  .value("PseudoVMSLTU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8_MASK)
  .value("PseudoVMSLTU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2)
  .value("PseudoVMSLTU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2_MASK)
  .value("PseudoVMSLTU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4)
  .value("PseudoVMSLTU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4_MASK)
  .value("PseudoVMSLTU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8)
  .value("PseudoVMSLTU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8_MASK)
  .value("PseudoVMSLTU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1)
  .value("PseudoVMSLTU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1_MASK)
  .value("PseudoVMSLTU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2)
  .value("PseudoVMSLTU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2_MASK)
  .value("PseudoVMSLTU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4)
  .value("PseudoVMSLTU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4_MASK)
  .value("PseudoVMSLTU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8)
  .value("PseudoVMSLTU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8_MASK)
  .value("PseudoVMSLTU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2)
  .value("PseudoVMSLTU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2_MASK)
  .value("PseudoVMSLTU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4)
  .value("PseudoVMSLTU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4_MASK)
  .value("PseudoVMSLTU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8)
  .value("PseudoVMSLTU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8_MASK)
  .value("PseudoVMSLT_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VI)
  .value("PseudoVMSLT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1)
  .value("PseudoVMSLT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1_MASK)
  .value("PseudoVMSLT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2)
  .value("PseudoVMSLT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2_MASK)
  .value("PseudoVMSLT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4)
  .value("PseudoVMSLT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4_MASK)
  .value("PseudoVMSLT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8)
  .value("PseudoVMSLT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8_MASK)
  .value("PseudoVMSLT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2)
  .value("PseudoVMSLT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2_MASK)
  .value("PseudoVMSLT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4)
  .value("PseudoVMSLT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4_MASK)
  .value("PseudoVMSLT_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8)
  .value("PseudoVMSLT_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8_MASK)
  .value("PseudoVMSLT_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1)
  .value("PseudoVMSLT_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1_MASK)
  .value("PseudoVMSLT_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2)
  .value("PseudoVMSLT_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2_MASK)
  .value("PseudoVMSLT_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4)
  .value("PseudoVMSLT_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4_MASK)
  .value("PseudoVMSLT_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8)
  .value("PseudoVMSLT_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8_MASK)
  .value("PseudoVMSLT_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2)
  .value("PseudoVMSLT_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2_MASK)
  .value("PseudoVMSLT_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4)
  .value("PseudoVMSLT_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4_MASK)
  .value("PseudoVMSLT_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8)
  .value("PseudoVMSLT_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8_MASK)
  .value("PseudoVMSNE_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1)
  .value("PseudoVMSNE_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1_MASK)
  .value("PseudoVMSNE_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2);
  opcodes.value("PseudoVMSNE_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2_MASK)
  .value("PseudoVMSNE_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4)
  .value("PseudoVMSNE_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4_MASK)
  .value("PseudoVMSNE_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8)
  .value("PseudoVMSNE_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8_MASK)
  .value("PseudoVMSNE_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2)
  .value("PseudoVMSNE_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2_MASK)
  .value("PseudoVMSNE_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4)
  .value("PseudoVMSNE_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4_MASK)
  .value("PseudoVMSNE_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8)
  .value("PseudoVMSNE_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8_MASK)
  .value("PseudoVMSNE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1)
  .value("PseudoVMSNE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1_MASK)
  .value("PseudoVMSNE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2)
  .value("PseudoVMSNE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2_MASK)
  .value("PseudoVMSNE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4)
  .value("PseudoVMSNE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4_MASK)
  .value("PseudoVMSNE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8)
  .value("PseudoVMSNE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8_MASK)
  .value("PseudoVMSNE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2)
  .value("PseudoVMSNE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2_MASK)
  .value("PseudoVMSNE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4)
  .value("PseudoVMSNE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4_MASK)
  .value("PseudoVMSNE_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8)
  .value("PseudoVMSNE_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8_MASK)
  .value("PseudoVMSNE_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1)
  .value("PseudoVMSNE_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1_MASK)
  .value("PseudoVMSNE_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2)
  .value("PseudoVMSNE_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2_MASK)
  .value("PseudoVMSNE_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4)
  .value("PseudoVMSNE_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4_MASK)
  .value("PseudoVMSNE_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8)
  .value("PseudoVMSNE_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8_MASK)
  .value("PseudoVMSNE_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2)
  .value("PseudoVMSNE_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2_MASK)
  .value("PseudoVMSNE_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4)
  .value("PseudoVMSNE_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4_MASK)
  .value("PseudoVMSNE_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8)
  .value("PseudoVMSNE_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8_MASK)
  .value("PseudoVMSOF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1)
  .value("PseudoVMSOF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16)
  .value("PseudoVMSOF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16_MASK)
  .value("PseudoVMSOF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1_MASK)
  .value("PseudoVMSOF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2)
  .value("PseudoVMSOF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2_MASK)
  .value("PseudoVMSOF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32)
  .value("PseudoVMSOF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32_MASK)
  .value("PseudoVMSOF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4)
  .value("PseudoVMSOF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4_MASK)
  .value("PseudoVMSOF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64)
  .value("PseudoVMSOF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64_MASK)
  .value("PseudoVMSOF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8)
  .value("PseudoVMSOF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8_MASK)
  .value("PseudoVMULHSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1)
  .value("PseudoVMULHSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1_MASK)
  .value("PseudoVMULHSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2)
  .value("PseudoVMULHSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2_MASK)
  .value("PseudoVMULHSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4)
  .value("PseudoVMULHSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4_MASK)
  .value("PseudoVMULHSU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8)
  .value("PseudoVMULHSU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8_MASK)
  .value("PseudoVMULHSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2)
  .value("PseudoVMULHSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2_MASK)
  .value("PseudoVMULHSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4)
  .value("PseudoVMULHSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4_MASK)
  .value("PseudoVMULHSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8)
  .value("PseudoVMULHSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8_MASK)
  .value("PseudoVMULHSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1)
  .value("PseudoVMULHSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1_MASK)
  .value("PseudoVMULHSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2)
  .value("PseudoVMULHSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2_MASK)
  .value("PseudoVMULHSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4)
  .value("PseudoVMULHSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4_MASK)
  .value("PseudoVMULHSU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8)
  .value("PseudoVMULHSU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8_MASK)
  .value("PseudoVMULHSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2)
  .value("PseudoVMULHSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2_MASK)
  .value("PseudoVMULHSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4)
  .value("PseudoVMULHSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4_MASK)
  .value("PseudoVMULHSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8)
  .value("PseudoVMULHSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8_MASK)
  .value("PseudoVMULHU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1)
  .value("PseudoVMULHU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1_MASK)
  .value("PseudoVMULHU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2)
  .value("PseudoVMULHU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2_MASK)
  .value("PseudoVMULHU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4)
  .value("PseudoVMULHU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4_MASK)
  .value("PseudoVMULHU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8)
  .value("PseudoVMULHU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8_MASK)
  .value("PseudoVMULHU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2)
  .value("PseudoVMULHU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2_MASK)
  .value("PseudoVMULHU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4)
  .value("PseudoVMULHU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4_MASK)
  .value("PseudoVMULHU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8)
  .value("PseudoVMULHU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8_MASK)
  .value("PseudoVMULHU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1)
  .value("PseudoVMULHU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1_MASK)
  .value("PseudoVMULHU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2)
  .value("PseudoVMULHU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2_MASK)
  .value("PseudoVMULHU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4)
  .value("PseudoVMULHU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4_MASK)
  .value("PseudoVMULHU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8)
  .value("PseudoVMULHU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8_MASK)
  .value("PseudoVMULHU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2)
  .value("PseudoVMULHU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2_MASK)
  .value("PseudoVMULHU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4)
  .value("PseudoVMULHU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4_MASK)
  .value("PseudoVMULHU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8)
  .value("PseudoVMULHU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8_MASK)
  .value("PseudoVMULH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1)
  .value("PseudoVMULH_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1_MASK)
  .value("PseudoVMULH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2)
  .value("PseudoVMULH_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2_MASK)
  .value("PseudoVMULH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4)
  .value("PseudoVMULH_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4_MASK)
  .value("PseudoVMULH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8)
  .value("PseudoVMULH_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8_MASK)
  .value("PseudoVMULH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2)
  .value("PseudoVMULH_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2_MASK)
  .value("PseudoVMULH_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4)
  .value("PseudoVMULH_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4_MASK)
  .value("PseudoVMULH_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8)
  .value("PseudoVMULH_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8_MASK)
  .value("PseudoVMULH_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1)
  .value("PseudoVMULH_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1_MASK)
  .value("PseudoVMULH_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2)
  .value("PseudoVMULH_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2_MASK)
  .value("PseudoVMULH_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4)
  .value("PseudoVMULH_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4_MASK)
  .value("PseudoVMULH_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8)
  .value("PseudoVMULH_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8_MASK)
  .value("PseudoVMULH_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2)
  .value("PseudoVMULH_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2_MASK)
  .value("PseudoVMULH_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4)
  .value("PseudoVMULH_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4_MASK)
  .value("PseudoVMULH_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8)
  .value("PseudoVMULH_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8_MASK)
  .value("PseudoVMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1)
  .value("PseudoVMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1_MASK)
  .value("PseudoVMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2)
  .value("PseudoVMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2_MASK)
  .value("PseudoVMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4)
  .value("PseudoVMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4_MASK)
  .value("PseudoVMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8)
  .value("PseudoVMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8_MASK)
  .value("PseudoVMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2)
  .value("PseudoVMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2_MASK)
  .value("PseudoVMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4)
  .value("PseudoVMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4_MASK)
  .value("PseudoVMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8)
  .value("PseudoVMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8_MASK)
  .value("PseudoVMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1)
  .value("PseudoVMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1_MASK)
  .value("PseudoVMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2)
  .value("PseudoVMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2_MASK)
  .value("PseudoVMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4)
  .value("PseudoVMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4_MASK)
  .value("PseudoVMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8)
  .value("PseudoVMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8_MASK)
  .value("PseudoVMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2)
  .value("PseudoVMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2_MASK)
  .value("PseudoVMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4)
  .value("PseudoVMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4_MASK)
  .value("PseudoVMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8)
  .value("PseudoVMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8_MASK)
  .value("PseudoVMV_S_X", LIEF::assembly::riscv::OPCODE::PseudoVMV_S_X)
  .value("PseudoVMV_V_I_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M1)
  .value("PseudoVMV_V_I_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M2)
  .value("PseudoVMV_V_I_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M4)
  .value("PseudoVMV_V_I_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M8)
  .value("PseudoVMV_V_I_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF2)
  .value("PseudoVMV_V_I_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF4)
  .value("PseudoVMV_V_I_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF8)
  .value("PseudoVMV_V_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M1)
  .value("PseudoVMV_V_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M2)
  .value("PseudoVMV_V_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M4)
  .value("PseudoVMV_V_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M8)
  .value("PseudoVMV_V_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF2)
  .value("PseudoVMV_V_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF4)
  .value("PseudoVMV_V_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF8)
  .value("PseudoVMV_V_X_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M1)
  .value("PseudoVMV_V_X_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M2)
  .value("PseudoVMV_V_X_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M4)
  .value("PseudoVMV_V_X_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M8)
  .value("PseudoVMV_V_X_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF2)
  .value("PseudoVMV_V_X_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF4)
  .value("PseudoVMV_V_X_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF8)
  .value("PseudoVMV_X_S", LIEF::assembly::riscv::OPCODE::PseudoVMV_X_S)
  .value("PseudoVMXNOR_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M1)
  .value("PseudoVMXNOR_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M2)
  .value("PseudoVMXNOR_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M4)
  .value("PseudoVMXNOR_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M8)
  .value("PseudoVMXNOR_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF2)
  .value("PseudoVMXNOR_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF4)
  .value("PseudoVMXNOR_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF8)
  .value("PseudoVMXOR_MM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M1)
  .value("PseudoVMXOR_MM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M2)
  .value("PseudoVMXOR_MM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M4)
  .value("PseudoVMXOR_MM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M8)
  .value("PseudoVMXOR_MM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF2)
  .value("PseudoVMXOR_MM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF4)
  .value("PseudoVMXOR_MM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF8)
  .value("PseudoVNCLIPU_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1)
  .value("PseudoVNCLIPU_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1_MASK)
  .value("PseudoVNCLIPU_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2)
  .value("PseudoVNCLIPU_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2_MASK)
  .value("PseudoVNCLIPU_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4)
  .value("PseudoVNCLIPU_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4_MASK)
  .value("PseudoVNCLIPU_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2)
  .value("PseudoVNCLIPU_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2_MASK)
  .value("PseudoVNCLIPU_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4)
  .value("PseudoVNCLIPU_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4_MASK)
  .value("PseudoVNCLIPU_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8)
  .value("PseudoVNCLIPU_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8_MASK)
  .value("PseudoVNCLIPU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1)
  .value("PseudoVNCLIPU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1_MASK)
  .value("PseudoVNCLIPU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2)
  .value("PseudoVNCLIPU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2_MASK)
  .value("PseudoVNCLIPU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4)
  .value("PseudoVNCLIPU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4_MASK)
  .value("PseudoVNCLIPU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2)
  .value("PseudoVNCLIPU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2_MASK)
  .value("PseudoVNCLIPU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4)
  .value("PseudoVNCLIPU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4_MASK)
  .value("PseudoVNCLIPU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8)
  .value("PseudoVNCLIPU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8_MASK)
  .value("PseudoVNCLIPU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1)
  .value("PseudoVNCLIPU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1_MASK)
  .value("PseudoVNCLIPU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2)
  .value("PseudoVNCLIPU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2_MASK)
  .value("PseudoVNCLIPU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4)
  .value("PseudoVNCLIPU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4_MASK)
  .value("PseudoVNCLIPU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2)
  .value("PseudoVNCLIPU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2_MASK)
  .value("PseudoVNCLIPU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4)
  .value("PseudoVNCLIPU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4_MASK)
  .value("PseudoVNCLIPU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8)
  .value("PseudoVNCLIPU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8_MASK)
  .value("PseudoVNCLIP_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1)
  .value("PseudoVNCLIP_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1_MASK)
  .value("PseudoVNCLIP_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2)
  .value("PseudoVNCLIP_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2_MASK)
  .value("PseudoVNCLIP_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4)
  .value("PseudoVNCLIP_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4_MASK)
  .value("PseudoVNCLIP_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2)
  .value("PseudoVNCLIP_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2_MASK)
  .value("PseudoVNCLIP_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4)
  .value("PseudoVNCLIP_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4_MASK)
  .value("PseudoVNCLIP_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8)
  .value("PseudoVNCLIP_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8_MASK)
  .value("PseudoVNCLIP_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1)
  .value("PseudoVNCLIP_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1_MASK)
  .value("PseudoVNCLIP_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2)
  .value("PseudoVNCLIP_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2_MASK)
  .value("PseudoVNCLIP_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4)
  .value("PseudoVNCLIP_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4_MASK)
  .value("PseudoVNCLIP_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2)
  .value("PseudoVNCLIP_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2_MASK)
  .value("PseudoVNCLIP_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4)
  .value("PseudoVNCLIP_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4_MASK)
  .value("PseudoVNCLIP_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8)
  .value("PseudoVNCLIP_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8_MASK)
  .value("PseudoVNCLIP_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1)
  .value("PseudoVNCLIP_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1_MASK)
  .value("PseudoVNCLIP_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2)
  .value("PseudoVNCLIP_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2_MASK)
  .value("PseudoVNCLIP_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4)
  .value("PseudoVNCLIP_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4_MASK)
  .value("PseudoVNCLIP_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2)
  .value("PseudoVNCLIP_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2_MASK)
  .value("PseudoVNCLIP_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4)
  .value("PseudoVNCLIP_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4_MASK)
  .value("PseudoVNCLIP_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8)
  .value("PseudoVNCLIP_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8_MASK)
  .value("PseudoVNMSAC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1)
  .value("PseudoVNMSAC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1_MASK)
  .value("PseudoVNMSAC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2)
  .value("PseudoVNMSAC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2_MASK)
  .value("PseudoVNMSAC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4)
  .value("PseudoVNMSAC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4_MASK)
  .value("PseudoVNMSAC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8)
  .value("PseudoVNMSAC_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8_MASK)
  .value("PseudoVNMSAC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2)
  .value("PseudoVNMSAC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2_MASK)
  .value("PseudoVNMSAC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4)
  .value("PseudoVNMSAC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4_MASK)
  .value("PseudoVNMSAC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8)
  .value("PseudoVNMSAC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8_MASK)
  .value("PseudoVNMSAC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1)
  .value("PseudoVNMSAC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1_MASK)
  .value("PseudoVNMSAC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2)
  .value("PseudoVNMSAC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2_MASK)
  .value("PseudoVNMSAC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4)
  .value("PseudoVNMSAC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4_MASK)
  .value("PseudoVNMSAC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8)
  .value("PseudoVNMSAC_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8_MASK)
  .value("PseudoVNMSAC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2)
  .value("PseudoVNMSAC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2_MASK)
  .value("PseudoVNMSAC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4)
  .value("PseudoVNMSAC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4_MASK);
  opcodes.value("PseudoVNMSAC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8)
  .value("PseudoVNMSAC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8_MASK)
  .value("PseudoVNMSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1)
  .value("PseudoVNMSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1_MASK)
  .value("PseudoVNMSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2)
  .value("PseudoVNMSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2_MASK)
  .value("PseudoVNMSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4)
  .value("PseudoVNMSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4_MASK)
  .value("PseudoVNMSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8)
  .value("PseudoVNMSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8_MASK)
  .value("PseudoVNMSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2)
  .value("PseudoVNMSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2_MASK)
  .value("PseudoVNMSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4)
  .value("PseudoVNMSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4_MASK)
  .value("PseudoVNMSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8)
  .value("PseudoVNMSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8_MASK)
  .value("PseudoVNMSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1)
  .value("PseudoVNMSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1_MASK)
  .value("PseudoVNMSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2)
  .value("PseudoVNMSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2_MASK)
  .value("PseudoVNMSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4)
  .value("PseudoVNMSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4_MASK)
  .value("PseudoVNMSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8)
  .value("PseudoVNMSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8_MASK)
  .value("PseudoVNMSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2)
  .value("PseudoVNMSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2_MASK)
  .value("PseudoVNMSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4)
  .value("PseudoVNMSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4_MASK)
  .value("PseudoVNMSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8)
  .value("PseudoVNMSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8_MASK)
  .value("PseudoVNSRA_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1)
  .value("PseudoVNSRA_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1_MASK)
  .value("PseudoVNSRA_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2)
  .value("PseudoVNSRA_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2_MASK)
  .value("PseudoVNSRA_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4)
  .value("PseudoVNSRA_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4_MASK)
  .value("PseudoVNSRA_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2)
  .value("PseudoVNSRA_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2_MASK)
  .value("PseudoVNSRA_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4)
  .value("PseudoVNSRA_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4_MASK)
  .value("PseudoVNSRA_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8)
  .value("PseudoVNSRA_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8_MASK)
  .value("PseudoVNSRA_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1)
  .value("PseudoVNSRA_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1_MASK)
  .value("PseudoVNSRA_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2)
  .value("PseudoVNSRA_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2_MASK)
  .value("PseudoVNSRA_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4)
  .value("PseudoVNSRA_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4_MASK)
  .value("PseudoVNSRA_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2)
  .value("PseudoVNSRA_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2_MASK)
  .value("PseudoVNSRA_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4)
  .value("PseudoVNSRA_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4_MASK)
  .value("PseudoVNSRA_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8)
  .value("PseudoVNSRA_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8_MASK)
  .value("PseudoVNSRA_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1)
  .value("PseudoVNSRA_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1_MASK)
  .value("PseudoVNSRA_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2)
  .value("PseudoVNSRA_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2_MASK)
  .value("PseudoVNSRA_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4)
  .value("PseudoVNSRA_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4_MASK)
  .value("PseudoVNSRA_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2)
  .value("PseudoVNSRA_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2_MASK)
  .value("PseudoVNSRA_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4)
  .value("PseudoVNSRA_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4_MASK)
  .value("PseudoVNSRA_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8)
  .value("PseudoVNSRA_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8_MASK)
  .value("PseudoVNSRL_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1)
  .value("PseudoVNSRL_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1_MASK)
  .value("PseudoVNSRL_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2)
  .value("PseudoVNSRL_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2_MASK)
  .value("PseudoVNSRL_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4)
  .value("PseudoVNSRL_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4_MASK)
  .value("PseudoVNSRL_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2)
  .value("PseudoVNSRL_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2_MASK)
  .value("PseudoVNSRL_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4)
  .value("PseudoVNSRL_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4_MASK)
  .value("PseudoVNSRL_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8)
  .value("PseudoVNSRL_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8_MASK)
  .value("PseudoVNSRL_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1)
  .value("PseudoVNSRL_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1_MASK)
  .value("PseudoVNSRL_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2)
  .value("PseudoVNSRL_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2_MASK)
  .value("PseudoVNSRL_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4)
  .value("PseudoVNSRL_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4_MASK)
  .value("PseudoVNSRL_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2)
  .value("PseudoVNSRL_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2_MASK)
  .value("PseudoVNSRL_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4)
  .value("PseudoVNSRL_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4_MASK)
  .value("PseudoVNSRL_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8)
  .value("PseudoVNSRL_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8_MASK)
  .value("PseudoVNSRL_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1)
  .value("PseudoVNSRL_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1_MASK)
  .value("PseudoVNSRL_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2)
  .value("PseudoVNSRL_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2_MASK)
  .value("PseudoVNSRL_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4)
  .value("PseudoVNSRL_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4_MASK)
  .value("PseudoVNSRL_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2)
  .value("PseudoVNSRL_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2_MASK)
  .value("PseudoVNSRL_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4)
  .value("PseudoVNSRL_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4_MASK)
  .value("PseudoVNSRL_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8)
  .value("PseudoVNSRL_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8_MASK)
  .value("PseudoVOR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1)
  .value("PseudoVOR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1_MASK)
  .value("PseudoVOR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2)
  .value("PseudoVOR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2_MASK)
  .value("PseudoVOR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4)
  .value("PseudoVOR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4_MASK)
  .value("PseudoVOR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8)
  .value("PseudoVOR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8_MASK)
  .value("PseudoVOR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2)
  .value("PseudoVOR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2_MASK)
  .value("PseudoVOR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4)
  .value("PseudoVOR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4_MASK)
  .value("PseudoVOR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8)
  .value("PseudoVOR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8_MASK)
  .value("PseudoVOR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1)
  .value("PseudoVOR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1_MASK)
  .value("PseudoVOR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2)
  .value("PseudoVOR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2_MASK)
  .value("PseudoVOR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4)
  .value("PseudoVOR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4_MASK)
  .value("PseudoVOR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8)
  .value("PseudoVOR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8_MASK)
  .value("PseudoVOR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2)
  .value("PseudoVOR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2_MASK)
  .value("PseudoVOR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4)
  .value("PseudoVOR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4_MASK)
  .value("PseudoVOR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8)
  .value("PseudoVOR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8_MASK)
  .value("PseudoVOR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1)
  .value("PseudoVOR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1_MASK)
  .value("PseudoVOR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2)
  .value("PseudoVOR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2_MASK)
  .value("PseudoVOR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4)
  .value("PseudoVOR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4_MASK)
  .value("PseudoVOR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8)
  .value("PseudoVOR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8_MASK)
  .value("PseudoVOR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2)
  .value("PseudoVOR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2_MASK)
  .value("PseudoVOR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4)
  .value("PseudoVOR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4_MASK)
  .value("PseudoVOR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8)
  .value("PseudoVOR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8_MASK)
  .value("PseudoVQMACCSU_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M1)
  .value("PseudoVQMACCSU_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M2)
  .value("PseudoVQMACCSU_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M4)
  .value("PseudoVQMACCSU_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M8)
  .value("PseudoVQMACCSU_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M1)
  .value("PseudoVQMACCSU_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M2)
  .value("PseudoVQMACCSU_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M4)
  .value("PseudoVQMACCSU_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_MF2)
  .value("PseudoVQMACCUS_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M1)
  .value("PseudoVQMACCUS_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M2)
  .value("PseudoVQMACCUS_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M4)
  .value("PseudoVQMACCUS_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M8)
  .value("PseudoVQMACCUS_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M1)
  .value("PseudoVQMACCUS_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M2)
  .value("PseudoVQMACCUS_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M4)
  .value("PseudoVQMACCUS_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_MF2)
  .value("PseudoVQMACCU_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M1)
  .value("PseudoVQMACCU_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M2)
  .value("PseudoVQMACCU_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M4)
  .value("PseudoVQMACCU_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M8)
  .value("PseudoVQMACCU_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M1)
  .value("PseudoVQMACCU_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M2)
  .value("PseudoVQMACCU_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M4)
  .value("PseudoVQMACCU_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_MF2)
  .value("PseudoVQMACC_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M1)
  .value("PseudoVQMACC_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M2)
  .value("PseudoVQMACC_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M4)
  .value("PseudoVQMACC_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M8)
  .value("PseudoVQMACC_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M1)
  .value("PseudoVQMACC_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M2)
  .value("PseudoVQMACC_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M4)
  .value("PseudoVQMACC_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_MF2)
  .value("PseudoVREDAND_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16)
  .value("PseudoVREDAND_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16_MASK)
  .value("PseudoVREDAND_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32)
  .value("PseudoVREDAND_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32_MASK)
  .value("PseudoVREDAND_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64)
  .value("PseudoVREDAND_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64_MASK)
  .value("PseudoVREDAND_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8)
  .value("PseudoVREDAND_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8_MASK)
  .value("PseudoVREDAND_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16)
  .value("PseudoVREDAND_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16_MASK)
  .value("PseudoVREDAND_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32)
  .value("PseudoVREDAND_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32_MASK)
  .value("PseudoVREDAND_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64)
  .value("PseudoVREDAND_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64_MASK)
  .value("PseudoVREDAND_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8)
  .value("PseudoVREDAND_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8_MASK)
  .value("PseudoVREDAND_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16)
  .value("PseudoVREDAND_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16_MASK)
  .value("PseudoVREDAND_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32)
  .value("PseudoVREDAND_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32_MASK)
  .value("PseudoVREDAND_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64)
  .value("PseudoVREDAND_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64_MASK)
  .value("PseudoVREDAND_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8)
  .value("PseudoVREDAND_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8_MASK)
  .value("PseudoVREDAND_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16)
  .value("PseudoVREDAND_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16_MASK)
  .value("PseudoVREDAND_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32)
  .value("PseudoVREDAND_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32_MASK)
  .value("PseudoVREDAND_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64)
  .value("PseudoVREDAND_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64_MASK)
  .value("PseudoVREDAND_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8)
  .value("PseudoVREDAND_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8_MASK)
  .value("PseudoVREDAND_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16)
  .value("PseudoVREDAND_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16_MASK)
  .value("PseudoVREDAND_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32)
  .value("PseudoVREDAND_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32_MASK)
  .value("PseudoVREDAND_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8)
  .value("PseudoVREDAND_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8_MASK)
  .value("PseudoVREDAND_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16)
  .value("PseudoVREDAND_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16_MASK)
  .value("PseudoVREDAND_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8)
  .value("PseudoVREDAND_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8_MASK)
  .value("PseudoVREDAND_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8)
  .value("PseudoVREDAND_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8_MASK)
  .value("PseudoVREDMAXU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16)
  .value("PseudoVREDMAXU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16_MASK)
  .value("PseudoVREDMAXU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32)
  .value("PseudoVREDMAXU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32_MASK)
  .value("PseudoVREDMAXU_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64)
  .value("PseudoVREDMAXU_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64_MASK)
  .value("PseudoVREDMAXU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8)
  .value("PseudoVREDMAXU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8_MASK)
  .value("PseudoVREDMAXU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16)
  .value("PseudoVREDMAXU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16_MASK)
  .value("PseudoVREDMAXU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32)
  .value("PseudoVREDMAXU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32_MASK)
  .value("PseudoVREDMAXU_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64)
  .value("PseudoVREDMAXU_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64_MASK)
  .value("PseudoVREDMAXU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8)
  .value("PseudoVREDMAXU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8_MASK)
  .value("PseudoVREDMAXU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16)
  .value("PseudoVREDMAXU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16_MASK)
  .value("PseudoVREDMAXU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32)
  .value("PseudoVREDMAXU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32_MASK)
  .value("PseudoVREDMAXU_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64)
  .value("PseudoVREDMAXU_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64_MASK)
  .value("PseudoVREDMAXU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8)
  .value("PseudoVREDMAXU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8_MASK)
  .value("PseudoVREDMAXU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16)
  .value("PseudoVREDMAXU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16_MASK)
  .value("PseudoVREDMAXU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32)
  .value("PseudoVREDMAXU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32_MASK)
  .value("PseudoVREDMAXU_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64)
  .value("PseudoVREDMAXU_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64_MASK)
  .value("PseudoVREDMAXU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8)
  .value("PseudoVREDMAXU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8_MASK)
  .value("PseudoVREDMAXU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16)
  .value("PseudoVREDMAXU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16_MASK)
  .value("PseudoVREDMAXU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32)
  .value("PseudoVREDMAXU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32_MASK)
  .value("PseudoVREDMAXU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8)
  .value("PseudoVREDMAXU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8_MASK)
  .value("PseudoVREDMAXU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16)
  .value("PseudoVREDMAXU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16_MASK)
  .value("PseudoVREDMAXU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8)
  .value("PseudoVREDMAXU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8_MASK)
  .value("PseudoVREDMAXU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8)
  .value("PseudoVREDMAXU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8_MASK)
  .value("PseudoVREDMAX_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16)
  .value("PseudoVREDMAX_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16_MASK)
  .value("PseudoVREDMAX_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32)
  .value("PseudoVREDMAX_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32_MASK)
  .value("PseudoVREDMAX_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64)
  .value("PseudoVREDMAX_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64_MASK)
  .value("PseudoVREDMAX_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8)
  .value("PseudoVREDMAX_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8_MASK)
  .value("PseudoVREDMAX_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16)
  .value("PseudoVREDMAX_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16_MASK)
  .value("PseudoVREDMAX_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32)
  .value("PseudoVREDMAX_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32_MASK)
  .value("PseudoVREDMAX_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64)
  .value("PseudoVREDMAX_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64_MASK)
  .value("PseudoVREDMAX_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8)
  .value("PseudoVREDMAX_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8_MASK)
  .value("PseudoVREDMAX_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16)
  .value("PseudoVREDMAX_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16_MASK)
  .value("PseudoVREDMAX_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32)
  .value("PseudoVREDMAX_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32_MASK)
  .value("PseudoVREDMAX_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64)
  .value("PseudoVREDMAX_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64_MASK)
  .value("PseudoVREDMAX_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8)
  .value("PseudoVREDMAX_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8_MASK)
  .value("PseudoVREDMAX_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16)
  .value("PseudoVREDMAX_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16_MASK)
  .value("PseudoVREDMAX_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32)
  .value("PseudoVREDMAX_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32_MASK)
  .value("PseudoVREDMAX_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64)
  .value("PseudoVREDMAX_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64_MASK)
  .value("PseudoVREDMAX_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8)
  .value("PseudoVREDMAX_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8_MASK)
  .value("PseudoVREDMAX_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16)
  .value("PseudoVREDMAX_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16_MASK)
  .value("PseudoVREDMAX_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32)
  .value("PseudoVREDMAX_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32_MASK);
  opcodes.value("PseudoVREDMAX_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8)
  .value("PseudoVREDMAX_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8_MASK)
  .value("PseudoVREDMAX_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16)
  .value("PseudoVREDMAX_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16_MASK)
  .value("PseudoVREDMAX_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8)
  .value("PseudoVREDMAX_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8_MASK)
  .value("PseudoVREDMAX_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8)
  .value("PseudoVREDMAX_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8_MASK)
  .value("PseudoVREDMINU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16)
  .value("PseudoVREDMINU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16_MASK)
  .value("PseudoVREDMINU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32)
  .value("PseudoVREDMINU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32_MASK)
  .value("PseudoVREDMINU_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64)
  .value("PseudoVREDMINU_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64_MASK)
  .value("PseudoVREDMINU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8)
  .value("PseudoVREDMINU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8_MASK)
  .value("PseudoVREDMINU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16)
  .value("PseudoVREDMINU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16_MASK)
  .value("PseudoVREDMINU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32)
  .value("PseudoVREDMINU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32_MASK)
  .value("PseudoVREDMINU_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64)
  .value("PseudoVREDMINU_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64_MASK)
  .value("PseudoVREDMINU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8)
  .value("PseudoVREDMINU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8_MASK)
  .value("PseudoVREDMINU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16)
  .value("PseudoVREDMINU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16_MASK)
  .value("PseudoVREDMINU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32)
  .value("PseudoVREDMINU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32_MASK)
  .value("PseudoVREDMINU_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64)
  .value("PseudoVREDMINU_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64_MASK)
  .value("PseudoVREDMINU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8)
  .value("PseudoVREDMINU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8_MASK)
  .value("PseudoVREDMINU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16)
  .value("PseudoVREDMINU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16_MASK)
  .value("PseudoVREDMINU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32)
  .value("PseudoVREDMINU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32_MASK)
  .value("PseudoVREDMINU_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64)
  .value("PseudoVREDMINU_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64_MASK)
  .value("PseudoVREDMINU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8)
  .value("PseudoVREDMINU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8_MASK)
  .value("PseudoVREDMINU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16)
  .value("PseudoVREDMINU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16_MASK)
  .value("PseudoVREDMINU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32)
  .value("PseudoVREDMINU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32_MASK)
  .value("PseudoVREDMINU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8)
  .value("PseudoVREDMINU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8_MASK)
  .value("PseudoVREDMINU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16)
  .value("PseudoVREDMINU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16_MASK)
  .value("PseudoVREDMINU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8)
  .value("PseudoVREDMINU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8_MASK)
  .value("PseudoVREDMINU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8)
  .value("PseudoVREDMINU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8_MASK)
  .value("PseudoVREDMIN_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16)
  .value("PseudoVREDMIN_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16_MASK)
  .value("PseudoVREDMIN_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32)
  .value("PseudoVREDMIN_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32_MASK)
  .value("PseudoVREDMIN_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64)
  .value("PseudoVREDMIN_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64_MASK)
  .value("PseudoVREDMIN_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8)
  .value("PseudoVREDMIN_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8_MASK)
  .value("PseudoVREDMIN_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16)
  .value("PseudoVREDMIN_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16_MASK)
  .value("PseudoVREDMIN_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32)
  .value("PseudoVREDMIN_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32_MASK)
  .value("PseudoVREDMIN_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64)
  .value("PseudoVREDMIN_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64_MASK)
  .value("PseudoVREDMIN_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8)
  .value("PseudoVREDMIN_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8_MASK)
  .value("PseudoVREDMIN_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16)
  .value("PseudoVREDMIN_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16_MASK)
  .value("PseudoVREDMIN_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32)
  .value("PseudoVREDMIN_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32_MASK)
  .value("PseudoVREDMIN_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64)
  .value("PseudoVREDMIN_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64_MASK)
  .value("PseudoVREDMIN_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8)
  .value("PseudoVREDMIN_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8_MASK)
  .value("PseudoVREDMIN_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16)
  .value("PseudoVREDMIN_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16_MASK)
  .value("PseudoVREDMIN_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32)
  .value("PseudoVREDMIN_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32_MASK)
  .value("PseudoVREDMIN_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64)
  .value("PseudoVREDMIN_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64_MASK)
  .value("PseudoVREDMIN_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8)
  .value("PseudoVREDMIN_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8_MASK)
  .value("PseudoVREDMIN_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16)
  .value("PseudoVREDMIN_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16_MASK)
  .value("PseudoVREDMIN_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32)
  .value("PseudoVREDMIN_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32_MASK)
  .value("PseudoVREDMIN_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8)
  .value("PseudoVREDMIN_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8_MASK)
  .value("PseudoVREDMIN_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16)
  .value("PseudoVREDMIN_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16_MASK)
  .value("PseudoVREDMIN_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8)
  .value("PseudoVREDMIN_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8_MASK)
  .value("PseudoVREDMIN_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8)
  .value("PseudoVREDMIN_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8_MASK)
  .value("PseudoVREDOR_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16)
  .value("PseudoVREDOR_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16_MASK)
  .value("PseudoVREDOR_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32)
  .value("PseudoVREDOR_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32_MASK)
  .value("PseudoVREDOR_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64)
  .value("PseudoVREDOR_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64_MASK)
  .value("PseudoVREDOR_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8)
  .value("PseudoVREDOR_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8_MASK)
  .value("PseudoVREDOR_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16)
  .value("PseudoVREDOR_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16_MASK)
  .value("PseudoVREDOR_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32)
  .value("PseudoVREDOR_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32_MASK)
  .value("PseudoVREDOR_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64)
  .value("PseudoVREDOR_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64_MASK)
  .value("PseudoVREDOR_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8)
  .value("PseudoVREDOR_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8_MASK)
  .value("PseudoVREDOR_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16)
  .value("PseudoVREDOR_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16_MASK)
  .value("PseudoVREDOR_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32)
  .value("PseudoVREDOR_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32_MASK)
  .value("PseudoVREDOR_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64)
  .value("PseudoVREDOR_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64_MASK)
  .value("PseudoVREDOR_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8)
  .value("PseudoVREDOR_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8_MASK)
  .value("PseudoVREDOR_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16)
  .value("PseudoVREDOR_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16_MASK)
  .value("PseudoVREDOR_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32)
  .value("PseudoVREDOR_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32_MASK)
  .value("PseudoVREDOR_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64)
  .value("PseudoVREDOR_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64_MASK)
  .value("PseudoVREDOR_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8)
  .value("PseudoVREDOR_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8_MASK)
  .value("PseudoVREDOR_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16)
  .value("PseudoVREDOR_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16_MASK)
  .value("PseudoVREDOR_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32)
  .value("PseudoVREDOR_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32_MASK)
  .value("PseudoVREDOR_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8)
  .value("PseudoVREDOR_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8_MASK)
  .value("PseudoVREDOR_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16)
  .value("PseudoVREDOR_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16_MASK)
  .value("PseudoVREDOR_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8)
  .value("PseudoVREDOR_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8_MASK)
  .value("PseudoVREDOR_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8)
  .value("PseudoVREDOR_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8_MASK)
  .value("PseudoVREDSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16)
  .value("PseudoVREDSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16_MASK)
  .value("PseudoVREDSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32)
  .value("PseudoVREDSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32_MASK)
  .value("PseudoVREDSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64)
  .value("PseudoVREDSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64_MASK)
  .value("PseudoVREDSUM_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8)
  .value("PseudoVREDSUM_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8_MASK)
  .value("PseudoVREDSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16)
  .value("PseudoVREDSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16_MASK)
  .value("PseudoVREDSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32)
  .value("PseudoVREDSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32_MASK)
  .value("PseudoVREDSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64)
  .value("PseudoVREDSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64_MASK)
  .value("PseudoVREDSUM_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8)
  .value("PseudoVREDSUM_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8_MASK)
  .value("PseudoVREDSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16)
  .value("PseudoVREDSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16_MASK)
  .value("PseudoVREDSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32)
  .value("PseudoVREDSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32_MASK)
  .value("PseudoVREDSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64)
  .value("PseudoVREDSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64_MASK)
  .value("PseudoVREDSUM_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8)
  .value("PseudoVREDSUM_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8_MASK)
  .value("PseudoVREDSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16)
  .value("PseudoVREDSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16_MASK)
  .value("PseudoVREDSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32)
  .value("PseudoVREDSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32_MASK)
  .value("PseudoVREDSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64)
  .value("PseudoVREDSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64_MASK)
  .value("PseudoVREDSUM_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8)
  .value("PseudoVREDSUM_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8_MASK)
  .value("PseudoVREDSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16)
  .value("PseudoVREDSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16_MASK)
  .value("PseudoVREDSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32)
  .value("PseudoVREDSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32_MASK)
  .value("PseudoVREDSUM_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8)
  .value("PseudoVREDSUM_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8_MASK)
  .value("PseudoVREDSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16)
  .value("PseudoVREDSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16_MASK)
  .value("PseudoVREDSUM_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8)
  .value("PseudoVREDSUM_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8_MASK)
  .value("PseudoVREDSUM_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8)
  .value("PseudoVREDSUM_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8_MASK)
  .value("PseudoVREDXOR_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16)
  .value("PseudoVREDXOR_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16_MASK)
  .value("PseudoVREDXOR_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32)
  .value("PseudoVREDXOR_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32_MASK)
  .value("PseudoVREDXOR_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64)
  .value("PseudoVREDXOR_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64_MASK)
  .value("PseudoVREDXOR_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8)
  .value("PseudoVREDXOR_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8_MASK)
  .value("PseudoVREDXOR_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16)
  .value("PseudoVREDXOR_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16_MASK)
  .value("PseudoVREDXOR_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32)
  .value("PseudoVREDXOR_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32_MASK)
  .value("PseudoVREDXOR_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64)
  .value("PseudoVREDXOR_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64_MASK)
  .value("PseudoVREDXOR_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8)
  .value("PseudoVREDXOR_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8_MASK)
  .value("PseudoVREDXOR_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16)
  .value("PseudoVREDXOR_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16_MASK)
  .value("PseudoVREDXOR_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32)
  .value("PseudoVREDXOR_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32_MASK)
  .value("PseudoVREDXOR_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64)
  .value("PseudoVREDXOR_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64_MASK)
  .value("PseudoVREDXOR_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8)
  .value("PseudoVREDXOR_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8_MASK)
  .value("PseudoVREDXOR_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16)
  .value("PseudoVREDXOR_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16_MASK)
  .value("PseudoVREDXOR_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32)
  .value("PseudoVREDXOR_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32_MASK)
  .value("PseudoVREDXOR_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64)
  .value("PseudoVREDXOR_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64_MASK)
  .value("PseudoVREDXOR_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8)
  .value("PseudoVREDXOR_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8_MASK)
  .value("PseudoVREDXOR_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16)
  .value("PseudoVREDXOR_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16_MASK)
  .value("PseudoVREDXOR_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32)
  .value("PseudoVREDXOR_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32_MASK)
  .value("PseudoVREDXOR_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8)
  .value("PseudoVREDXOR_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8_MASK)
  .value("PseudoVREDXOR_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16)
  .value("PseudoVREDXOR_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16_MASK)
  .value("PseudoVREDXOR_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8)
  .value("PseudoVREDXOR_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8_MASK)
  .value("PseudoVREDXOR_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8)
  .value("PseudoVREDXOR_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8_MASK)
  .value("PseudoVRELOAD2_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M1)
  .value("PseudoVRELOAD2_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M2)
  .value("PseudoVRELOAD2_M4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M4)
  .value("PseudoVRELOAD2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF2)
  .value("PseudoVRELOAD2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF4)
  .value("PseudoVRELOAD2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF8)
  .value("PseudoVRELOAD3_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M1)
  .value("PseudoVRELOAD3_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M2)
  .value("PseudoVRELOAD3_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF2)
  .value("PseudoVRELOAD3_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF4)
  .value("PseudoVRELOAD3_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF8)
  .value("PseudoVRELOAD4_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M1)
  .value("PseudoVRELOAD4_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M2)
  .value("PseudoVRELOAD4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF2)
  .value("PseudoVRELOAD4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF4)
  .value("PseudoVRELOAD4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF8)
  .value("PseudoVRELOAD5_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_M1)
  .value("PseudoVRELOAD5_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF2)
  .value("PseudoVRELOAD5_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF4)
  .value("PseudoVRELOAD5_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF8)
  .value("PseudoVRELOAD6_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_M1)
  .value("PseudoVRELOAD6_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF2)
  .value("PseudoVRELOAD6_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF4)
  .value("PseudoVRELOAD6_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF8)
  .value("PseudoVRELOAD7_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_M1)
  .value("PseudoVRELOAD7_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF2)
  .value("PseudoVRELOAD7_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF4)
  .value("PseudoVRELOAD7_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF8)
  .value("PseudoVRELOAD8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_M1)
  .value("PseudoVRELOAD8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF2)
  .value("PseudoVRELOAD8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF4)
  .value("PseudoVRELOAD8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF8)
  .value("PseudoVREMU_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16)
  .value("PseudoVREMU_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16_MASK)
  .value("PseudoVREMU_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32)
  .value("PseudoVREMU_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32_MASK)
  .value("PseudoVREMU_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64)
  .value("PseudoVREMU_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64_MASK)
  .value("PseudoVREMU_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8)
  .value("PseudoVREMU_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8_MASK)
  .value("PseudoVREMU_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16)
  .value("PseudoVREMU_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16_MASK)
  .value("PseudoVREMU_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32)
  .value("PseudoVREMU_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32_MASK)
  .value("PseudoVREMU_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64)
  .value("PseudoVREMU_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64_MASK)
  .value("PseudoVREMU_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8)
  .value("PseudoVREMU_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8_MASK)
  .value("PseudoVREMU_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16)
  .value("PseudoVREMU_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16_MASK)
  .value("PseudoVREMU_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32)
  .value("PseudoVREMU_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32_MASK)
  .value("PseudoVREMU_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64)
  .value("PseudoVREMU_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64_MASK)
  .value("PseudoVREMU_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8)
  .value("PseudoVREMU_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8_MASK)
  .value("PseudoVREMU_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16)
  .value("PseudoVREMU_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16_MASK)
  .value("PseudoVREMU_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32)
  .value("PseudoVREMU_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32_MASK)
  .value("PseudoVREMU_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64)
  .value("PseudoVREMU_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64_MASK)
  .value("PseudoVREMU_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8)
  .value("PseudoVREMU_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8_MASK)
  .value("PseudoVREMU_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16)
  .value("PseudoVREMU_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16_MASK)
  .value("PseudoVREMU_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32)
  .value("PseudoVREMU_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32_MASK)
  .value("PseudoVREMU_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8)
  .value("PseudoVREMU_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8_MASK)
  .value("PseudoVREMU_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16)
  .value("PseudoVREMU_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16_MASK);
  opcodes.value("PseudoVREMU_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8)
  .value("PseudoVREMU_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8_MASK)
  .value("PseudoVREMU_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8)
  .value("PseudoVREMU_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8_MASK)
  .value("PseudoVREMU_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16)
  .value("PseudoVREMU_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16_MASK)
  .value("PseudoVREMU_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32)
  .value("PseudoVREMU_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32_MASK)
  .value("PseudoVREMU_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64)
  .value("PseudoVREMU_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64_MASK)
  .value("PseudoVREMU_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8)
  .value("PseudoVREMU_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8_MASK)
  .value("PseudoVREMU_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16)
  .value("PseudoVREMU_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16_MASK)
  .value("PseudoVREMU_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32)
  .value("PseudoVREMU_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32_MASK)
  .value("PseudoVREMU_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64)
  .value("PseudoVREMU_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64_MASK)
  .value("PseudoVREMU_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8)
  .value("PseudoVREMU_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8_MASK)
  .value("PseudoVREMU_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16)
  .value("PseudoVREMU_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16_MASK)
  .value("PseudoVREMU_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32)
  .value("PseudoVREMU_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32_MASK)
  .value("PseudoVREMU_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64)
  .value("PseudoVREMU_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64_MASK)
  .value("PseudoVREMU_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8)
  .value("PseudoVREMU_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8_MASK)
  .value("PseudoVREMU_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16)
  .value("PseudoVREMU_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16_MASK)
  .value("PseudoVREMU_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32)
  .value("PseudoVREMU_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32_MASK)
  .value("PseudoVREMU_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64)
  .value("PseudoVREMU_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64_MASK)
  .value("PseudoVREMU_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8)
  .value("PseudoVREMU_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8_MASK)
  .value("PseudoVREMU_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16)
  .value("PseudoVREMU_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16_MASK)
  .value("PseudoVREMU_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32)
  .value("PseudoVREMU_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32_MASK)
  .value("PseudoVREMU_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8)
  .value("PseudoVREMU_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8_MASK)
  .value("PseudoVREMU_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16)
  .value("PseudoVREMU_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16_MASK)
  .value("PseudoVREMU_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8)
  .value("PseudoVREMU_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8_MASK)
  .value("PseudoVREMU_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8)
  .value("PseudoVREMU_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8_MASK)
  .value("PseudoVREM_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16)
  .value("PseudoVREM_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16_MASK)
  .value("PseudoVREM_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32)
  .value("PseudoVREM_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32_MASK)
  .value("PseudoVREM_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64)
  .value("PseudoVREM_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64_MASK)
  .value("PseudoVREM_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8)
  .value("PseudoVREM_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8_MASK)
  .value("PseudoVREM_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16)
  .value("PseudoVREM_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16_MASK)
  .value("PseudoVREM_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32)
  .value("PseudoVREM_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32_MASK)
  .value("PseudoVREM_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64)
  .value("PseudoVREM_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64_MASK)
  .value("PseudoVREM_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8)
  .value("PseudoVREM_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8_MASK)
  .value("PseudoVREM_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16)
  .value("PseudoVREM_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16_MASK)
  .value("PseudoVREM_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32)
  .value("PseudoVREM_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32_MASK)
  .value("PseudoVREM_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64)
  .value("PseudoVREM_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64_MASK)
  .value("PseudoVREM_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8)
  .value("PseudoVREM_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8_MASK)
  .value("PseudoVREM_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16)
  .value("PseudoVREM_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16_MASK)
  .value("PseudoVREM_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32)
  .value("PseudoVREM_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32_MASK)
  .value("PseudoVREM_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64)
  .value("PseudoVREM_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64_MASK)
  .value("PseudoVREM_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8)
  .value("PseudoVREM_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8_MASK)
  .value("PseudoVREM_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16)
  .value("PseudoVREM_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16_MASK)
  .value("PseudoVREM_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32)
  .value("PseudoVREM_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32_MASK)
  .value("PseudoVREM_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8)
  .value("PseudoVREM_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8_MASK)
  .value("PseudoVREM_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16)
  .value("PseudoVREM_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16_MASK)
  .value("PseudoVREM_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8)
  .value("PseudoVREM_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8_MASK)
  .value("PseudoVREM_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8)
  .value("PseudoVREM_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8_MASK)
  .value("PseudoVREM_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16)
  .value("PseudoVREM_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16_MASK)
  .value("PseudoVREM_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32)
  .value("PseudoVREM_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32_MASK)
  .value("PseudoVREM_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64)
  .value("PseudoVREM_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64_MASK)
  .value("PseudoVREM_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8)
  .value("PseudoVREM_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8_MASK)
  .value("PseudoVREM_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16)
  .value("PseudoVREM_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16_MASK)
  .value("PseudoVREM_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32)
  .value("PseudoVREM_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32_MASK)
  .value("PseudoVREM_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64)
  .value("PseudoVREM_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64_MASK)
  .value("PseudoVREM_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8)
  .value("PseudoVREM_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8_MASK)
  .value("PseudoVREM_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16)
  .value("PseudoVREM_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16_MASK)
  .value("PseudoVREM_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32)
  .value("PseudoVREM_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32_MASK)
  .value("PseudoVREM_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64)
  .value("PseudoVREM_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64_MASK)
  .value("PseudoVREM_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8)
  .value("PseudoVREM_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8_MASK)
  .value("PseudoVREM_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16)
  .value("PseudoVREM_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16_MASK)
  .value("PseudoVREM_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32)
  .value("PseudoVREM_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32_MASK)
  .value("PseudoVREM_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64)
  .value("PseudoVREM_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64_MASK)
  .value("PseudoVREM_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8)
  .value("PseudoVREM_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8_MASK)
  .value("PseudoVREM_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16)
  .value("PseudoVREM_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16_MASK)
  .value("PseudoVREM_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32)
  .value("PseudoVREM_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32_MASK)
  .value("PseudoVREM_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8)
  .value("PseudoVREM_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8_MASK)
  .value("PseudoVREM_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16)
  .value("PseudoVREM_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16_MASK)
  .value("PseudoVREM_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8)
  .value("PseudoVREM_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8_MASK)
  .value("PseudoVREM_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8)
  .value("PseudoVREM_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8_MASK)
  .value("PseudoVREV8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1)
  .value("PseudoVREV8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1_MASK)
  .value("PseudoVREV8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2)
  .value("PseudoVREV8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2_MASK)
  .value("PseudoVREV8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4)
  .value("PseudoVREV8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4_MASK)
  .value("PseudoVREV8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8)
  .value("PseudoVREV8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8_MASK)
  .value("PseudoVREV8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2)
  .value("PseudoVREV8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2_MASK)
  .value("PseudoVREV8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4)
  .value("PseudoVREV8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4_MASK)
  .value("PseudoVREV8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8)
  .value("PseudoVREV8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1)
  .value("PseudoVRGATHEREI16_VV_M1_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2)
  .value("PseudoVRGATHEREI16_VV_M1_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2)
  .value("PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4)
  .value("PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1)
  .value("PseudoVRGATHEREI16_VV_M1_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2)
  .value("PseudoVRGATHEREI16_VV_M1_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2)
  .value("PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E32_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4)
  .value("PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1)
  .value("PseudoVRGATHEREI16_VV_M1_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2)
  .value("PseudoVRGATHEREI16_VV_M1_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E64_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2)
  .value("PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E64_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4)
  .value("PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1)
  .value("PseudoVRGATHEREI16_VV_M1_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2)
  .value("PseudoVRGATHEREI16_VV_M1_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2)
  .value("PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M1_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4)
  .value("PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4)
  .value("PseudoVRGATHEREI16_VV_M2_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2)
  .value("PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4)
  .value("PseudoVRGATHEREI16_VV_M2_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2)
  .value("PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4)
  .value("PseudoVRGATHEREI16_VV_M2_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E64_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2)
  .value("PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4)
  .value("PseudoVRGATHEREI16_VV_M2_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M2_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2)
  .value("PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8)
  .value("PseudoVRGATHEREI16_VV_M4_E16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8)
  .value("PseudoVRGATHEREI16_VV_M4_E32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8)
  .value("PseudoVRGATHEREI16_VV_M4_E64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8)
  .value("PseudoVRGATHEREI16_VV_M4_E8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8)
  .value("PseudoVRGATHEREI16_VV_M8_E16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8)
  .value("PseudoVRGATHEREI16_VV_M8_E32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8)
  .value("PseudoVRGATHEREI16_VV_M8_E64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8)
  .value("PseudoVRGATHEREI16_VV_M8_E8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8)
  .value("PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8)
  .value("PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8)
  .value("PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8)
  .value("PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK);
  opcodes.value("PseudoVRGATHEREI16_VV_MF4_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2)
  .value("PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK)
  .value("PseudoVRGATHEREI16_VV_MF4_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4)
  .value("PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF4_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8)
  .value("PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK)
  .value("PseudoVRGATHEREI16_VV_MF8_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4)
  .value("PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK)
  .value("PseudoVRGATHEREI16_VV_MF8_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8)
  .value("PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK)
  .value("PseudoVRGATHER_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1)
  .value("PseudoVRGATHER_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1_MASK)
  .value("PseudoVRGATHER_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2)
  .value("PseudoVRGATHER_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2_MASK)
  .value("PseudoVRGATHER_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4)
  .value("PseudoVRGATHER_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4_MASK)
  .value("PseudoVRGATHER_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8)
  .value("PseudoVRGATHER_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8_MASK)
  .value("PseudoVRGATHER_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2)
  .value("PseudoVRGATHER_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2_MASK)
  .value("PseudoVRGATHER_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4)
  .value("PseudoVRGATHER_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4_MASK)
  .value("PseudoVRGATHER_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8)
  .value("PseudoVRGATHER_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8_MASK)
  .value("PseudoVRGATHER_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16)
  .value("PseudoVRGATHER_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16_MASK)
  .value("PseudoVRGATHER_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32)
  .value("PseudoVRGATHER_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32_MASK)
  .value("PseudoVRGATHER_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64)
  .value("PseudoVRGATHER_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64_MASK)
  .value("PseudoVRGATHER_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8)
  .value("PseudoVRGATHER_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8_MASK)
  .value("PseudoVRGATHER_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16)
  .value("PseudoVRGATHER_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16_MASK)
  .value("PseudoVRGATHER_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32)
  .value("PseudoVRGATHER_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32_MASK)
  .value("PseudoVRGATHER_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64)
  .value("PseudoVRGATHER_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64_MASK)
  .value("PseudoVRGATHER_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8)
  .value("PseudoVRGATHER_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8_MASK)
  .value("PseudoVRGATHER_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16)
  .value("PseudoVRGATHER_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16_MASK)
  .value("PseudoVRGATHER_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32)
  .value("PseudoVRGATHER_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32_MASK)
  .value("PseudoVRGATHER_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64)
  .value("PseudoVRGATHER_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64_MASK)
  .value("PseudoVRGATHER_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8)
  .value("PseudoVRGATHER_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8_MASK)
  .value("PseudoVRGATHER_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16)
  .value("PseudoVRGATHER_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16_MASK)
  .value("PseudoVRGATHER_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32)
  .value("PseudoVRGATHER_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32_MASK)
  .value("PseudoVRGATHER_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64)
  .value("PseudoVRGATHER_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64_MASK)
  .value("PseudoVRGATHER_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8)
  .value("PseudoVRGATHER_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8_MASK)
  .value("PseudoVRGATHER_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16)
  .value("PseudoVRGATHER_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16_MASK)
  .value("PseudoVRGATHER_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32)
  .value("PseudoVRGATHER_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32_MASK)
  .value("PseudoVRGATHER_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8)
  .value("PseudoVRGATHER_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8_MASK)
  .value("PseudoVRGATHER_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16)
  .value("PseudoVRGATHER_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16_MASK)
  .value("PseudoVRGATHER_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8)
  .value("PseudoVRGATHER_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8_MASK)
  .value("PseudoVRGATHER_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8)
  .value("PseudoVRGATHER_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8_MASK)
  .value("PseudoVRGATHER_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1)
  .value("PseudoVRGATHER_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1_MASK)
  .value("PseudoVRGATHER_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2)
  .value("PseudoVRGATHER_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2_MASK)
  .value("PseudoVRGATHER_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4)
  .value("PseudoVRGATHER_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4_MASK)
  .value("PseudoVRGATHER_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8)
  .value("PseudoVRGATHER_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8_MASK)
  .value("PseudoVRGATHER_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2)
  .value("PseudoVRGATHER_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2_MASK)
  .value("PseudoVRGATHER_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4)
  .value("PseudoVRGATHER_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4_MASK)
  .value("PseudoVRGATHER_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8)
  .value("PseudoVRGATHER_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8_MASK)
  .value("PseudoVROL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1)
  .value("PseudoVROL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1_MASK)
  .value("PseudoVROL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2)
  .value("PseudoVROL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2_MASK)
  .value("PseudoVROL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4)
  .value("PseudoVROL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4_MASK)
  .value("PseudoVROL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8)
  .value("PseudoVROL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8_MASK)
  .value("PseudoVROL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2)
  .value("PseudoVROL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2_MASK)
  .value("PseudoVROL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4)
  .value("PseudoVROL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4_MASK)
  .value("PseudoVROL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8)
  .value("PseudoVROL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8_MASK)
  .value("PseudoVROL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1)
  .value("PseudoVROL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1_MASK)
  .value("PseudoVROL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2)
  .value("PseudoVROL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2_MASK)
  .value("PseudoVROL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4)
  .value("PseudoVROL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4_MASK)
  .value("PseudoVROL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8)
  .value("PseudoVROL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8_MASK)
  .value("PseudoVROL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2)
  .value("PseudoVROL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2_MASK)
  .value("PseudoVROL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4)
  .value("PseudoVROL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4_MASK)
  .value("PseudoVROL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8)
  .value("PseudoVROL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8_MASK)
  .value("PseudoVROR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1)
  .value("PseudoVROR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1_MASK)
  .value("PseudoVROR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2)
  .value("PseudoVROR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2_MASK)
  .value("PseudoVROR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4)
  .value("PseudoVROR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4_MASK)
  .value("PseudoVROR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8)
  .value("PseudoVROR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8_MASK)
  .value("PseudoVROR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2)
  .value("PseudoVROR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2_MASK)
  .value("PseudoVROR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4)
  .value("PseudoVROR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4_MASK)
  .value("PseudoVROR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8)
  .value("PseudoVROR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8_MASK)
  .value("PseudoVROR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1)
  .value("PseudoVROR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1_MASK)
  .value("PseudoVROR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2)
  .value("PseudoVROR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2_MASK)
  .value("PseudoVROR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4)
  .value("PseudoVROR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4_MASK)
  .value("PseudoVROR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8)
  .value("PseudoVROR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8_MASK)
  .value("PseudoVROR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2)
  .value("PseudoVROR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2_MASK)
  .value("PseudoVROR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4)
  .value("PseudoVROR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4_MASK)
  .value("PseudoVROR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8)
  .value("PseudoVROR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8_MASK)
  .value("PseudoVROR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1)
  .value("PseudoVROR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1_MASK)
  .value("PseudoVROR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2)
  .value("PseudoVROR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2_MASK)
  .value("PseudoVROR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4)
  .value("PseudoVROR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4_MASK)
  .value("PseudoVROR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8)
  .value("PseudoVROR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8_MASK)
  .value("PseudoVROR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2)
  .value("PseudoVROR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2_MASK)
  .value("PseudoVROR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4)
  .value("PseudoVROR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4_MASK)
  .value("PseudoVROR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8)
  .value("PseudoVROR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8_MASK)
  .value("PseudoVRSUB_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1)
  .value("PseudoVRSUB_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1_MASK)
  .value("PseudoVRSUB_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2)
  .value("PseudoVRSUB_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2_MASK)
  .value("PseudoVRSUB_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4)
  .value("PseudoVRSUB_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4_MASK)
  .value("PseudoVRSUB_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8)
  .value("PseudoVRSUB_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8_MASK)
  .value("PseudoVRSUB_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2)
  .value("PseudoVRSUB_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2_MASK)
  .value("PseudoVRSUB_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4)
  .value("PseudoVRSUB_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4_MASK)
  .value("PseudoVRSUB_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8)
  .value("PseudoVRSUB_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8_MASK)
  .value("PseudoVRSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1)
  .value("PseudoVRSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1_MASK)
  .value("PseudoVRSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2)
  .value("PseudoVRSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2_MASK)
  .value("PseudoVRSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4)
  .value("PseudoVRSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4_MASK)
  .value("PseudoVRSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8)
  .value("PseudoVRSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8_MASK)
  .value("PseudoVRSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2)
  .value("PseudoVRSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2_MASK)
  .value("PseudoVRSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4)
  .value("PseudoVRSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4_MASK)
  .value("PseudoVRSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8)
  .value("PseudoVRSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8_MASK)
  .value("PseudoVSADDU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1)
  .value("PseudoVSADDU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1_MASK)
  .value("PseudoVSADDU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2)
  .value("PseudoVSADDU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2_MASK)
  .value("PseudoVSADDU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4)
  .value("PseudoVSADDU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4_MASK)
  .value("PseudoVSADDU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8)
  .value("PseudoVSADDU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8_MASK)
  .value("PseudoVSADDU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2)
  .value("PseudoVSADDU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2_MASK)
  .value("PseudoVSADDU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4)
  .value("PseudoVSADDU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4_MASK)
  .value("PseudoVSADDU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8)
  .value("PseudoVSADDU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8_MASK)
  .value("PseudoVSADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1)
  .value("PseudoVSADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1_MASK)
  .value("PseudoVSADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2)
  .value("PseudoVSADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2_MASK)
  .value("PseudoVSADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4)
  .value("PseudoVSADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4_MASK)
  .value("PseudoVSADDU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8)
  .value("PseudoVSADDU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8_MASK)
  .value("PseudoVSADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2)
  .value("PseudoVSADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2_MASK)
  .value("PseudoVSADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4)
  .value("PseudoVSADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4_MASK)
  .value("PseudoVSADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8)
  .value("PseudoVSADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8_MASK)
  .value("PseudoVSADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1)
  .value("PseudoVSADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1_MASK)
  .value("PseudoVSADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2)
  .value("PseudoVSADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2_MASK)
  .value("PseudoVSADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4)
  .value("PseudoVSADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4_MASK)
  .value("PseudoVSADDU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8)
  .value("PseudoVSADDU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8_MASK)
  .value("PseudoVSADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2)
  .value("PseudoVSADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2_MASK)
  .value("PseudoVSADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4)
  .value("PseudoVSADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4_MASK)
  .value("PseudoVSADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8)
  .value("PseudoVSADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8_MASK)
  .value("PseudoVSADD_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1)
  .value("PseudoVSADD_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1_MASK)
  .value("PseudoVSADD_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2)
  .value("PseudoVSADD_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2_MASK)
  .value("PseudoVSADD_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4)
  .value("PseudoVSADD_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4_MASK)
  .value("PseudoVSADD_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8)
  .value("PseudoVSADD_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8_MASK)
  .value("PseudoVSADD_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2)
  .value("PseudoVSADD_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2_MASK)
  .value("PseudoVSADD_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4)
  .value("PseudoVSADD_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4_MASK)
  .value("PseudoVSADD_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8)
  .value("PseudoVSADD_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8_MASK)
  .value("PseudoVSADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1)
  .value("PseudoVSADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1_MASK)
  .value("PseudoVSADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2)
  .value("PseudoVSADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2_MASK)
  .value("PseudoVSADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4)
  .value("PseudoVSADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4_MASK)
  .value("PseudoVSADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8)
  .value("PseudoVSADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8_MASK)
  .value("PseudoVSADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2)
  .value("PseudoVSADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2_MASK)
  .value("PseudoVSADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4)
  .value("PseudoVSADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4_MASK)
  .value("PseudoVSADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8)
  .value("PseudoVSADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8_MASK)
  .value("PseudoVSADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1)
  .value("PseudoVSADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1_MASK)
  .value("PseudoVSADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2)
  .value("PseudoVSADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2_MASK)
  .value("PseudoVSADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4)
  .value("PseudoVSADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4_MASK)
  .value("PseudoVSADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8)
  .value("PseudoVSADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8_MASK)
  .value("PseudoVSADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2)
  .value("PseudoVSADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2_MASK)
  .value("PseudoVSADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4)
  .value("PseudoVSADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4_MASK)
  .value("PseudoVSADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8)
  .value("PseudoVSADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8_MASK)
  .value("PseudoVSBC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M1)
  .value("PseudoVSBC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M2)
  .value("PseudoVSBC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M4)
  .value("PseudoVSBC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M8)
  .value("PseudoVSBC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF2)
  .value("PseudoVSBC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF4)
  .value("PseudoVSBC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF8)
  .value("PseudoVSBC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M1)
  .value("PseudoVSBC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M2)
  .value("PseudoVSBC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M4)
  .value("PseudoVSBC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M8)
  .value("PseudoVSBC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF2)
  .value("PseudoVSBC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF4)
  .value("PseudoVSBC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF8)
  .value("PseudoVSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1)
  .value("PseudoVSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1_MASK)
  .value("PseudoVSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2)
  .value("PseudoVSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2_MASK)
  .value("PseudoVSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4)
  .value("PseudoVSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4_MASK)
  .value("PseudoVSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8)
  .value("PseudoVSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8_MASK)
  .value("PseudoVSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2)
  .value("PseudoVSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2_MASK)
  .value("PseudoVSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4)
  .value("PseudoVSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4_MASK)
  .value("PseudoVSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1)
  .value("PseudoVSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1_MASK)
  .value("PseudoVSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2)
  .value("PseudoVSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2_MASK)
  .value("PseudoVSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4)
  .value("PseudoVSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4_MASK)
  .value("PseudoVSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8)
  .value("PseudoVSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8_MASK)
  .value("PseudoVSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2)
  .value("PseudoVSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2_MASK);
  opcodes.value("PseudoVSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1)
  .value("PseudoVSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1_MASK)
  .value("PseudoVSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2)
  .value("PseudoVSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2_MASK)
  .value("PseudoVSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4)
  .value("PseudoVSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4_MASK)
  .value("PseudoVSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8)
  .value("PseudoVSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8_MASK)
  .value("PseudoVSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1)
  .value("PseudoVSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1_MASK)
  .value("PseudoVSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2)
  .value("PseudoVSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2_MASK)
  .value("PseudoVSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4)
  .value("PseudoVSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4_MASK)
  .value("PseudoVSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8)
  .value("PseudoVSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8_MASK)
  .value("PseudoVSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2)
  .value("PseudoVSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2_MASK)
  .value("PseudoVSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4)
  .value("PseudoVSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4_MASK)
  .value("PseudoVSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8)
  .value("PseudoVSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8_MASK)
  .value("PseudoVSETIVLI", LIEF::assembly::riscv::OPCODE::PseudoVSETIVLI)
  .value("PseudoVSETVLI", LIEF::assembly::riscv::OPCODE::PseudoVSETVLI)
  .value("PseudoVSETVLIX0", LIEF::assembly::riscv::OPCODE::PseudoVSETVLIX0)
  .value("PseudoVSEXT_VF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1)
  .value("PseudoVSEXT_VF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1_MASK)
  .value("PseudoVSEXT_VF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2)
  .value("PseudoVSEXT_VF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2_MASK)
  .value("PseudoVSEXT_VF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4)
  .value("PseudoVSEXT_VF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4_MASK)
  .value("PseudoVSEXT_VF2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8)
  .value("PseudoVSEXT_VF2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8_MASK)
  .value("PseudoVSEXT_VF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2)
  .value("PseudoVSEXT_VF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2_MASK)
  .value("PseudoVSEXT_VF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4)
  .value("PseudoVSEXT_VF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4_MASK)
  .value("PseudoVSEXT_VF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1)
  .value("PseudoVSEXT_VF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1_MASK)
  .value("PseudoVSEXT_VF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2)
  .value("PseudoVSEXT_VF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2_MASK)
  .value("PseudoVSEXT_VF4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4)
  .value("PseudoVSEXT_VF4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4_MASK)
  .value("PseudoVSEXT_VF4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8)
  .value("PseudoVSEXT_VF4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8_MASK)
  .value("PseudoVSEXT_VF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2)
  .value("PseudoVSEXT_VF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2_MASK)
  .value("PseudoVSEXT_VF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1)
  .value("PseudoVSEXT_VF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1_MASK)
  .value("PseudoVSEXT_VF8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2)
  .value("PseudoVSEXT_VF8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2_MASK)
  .value("PseudoVSEXT_VF8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4)
  .value("PseudoVSEXT_VF8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4_MASK)
  .value("PseudoVSEXT_VF8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8)
  .value("PseudoVSEXT_VF8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8_MASK)
  .value("PseudoVSHA2CH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M1)
  .value("PseudoVSHA2CH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M2)
  .value("PseudoVSHA2CH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M4)
  .value("PseudoVSHA2CH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M8)
  .value("PseudoVSHA2CH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_MF2)
  .value("PseudoVSHA2CL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M1)
  .value("PseudoVSHA2CL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M2)
  .value("PseudoVSHA2CL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M4)
  .value("PseudoVSHA2CL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M8)
  .value("PseudoVSHA2CL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_MF2)
  .value("PseudoVSHA2MS_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M1)
  .value("PseudoVSHA2MS_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M2)
  .value("PseudoVSHA2MS_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M4)
  .value("PseudoVSHA2MS_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M8)
  .value("PseudoVSHA2MS_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_MF2)
  .value("PseudoVSLIDE1DOWN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1)
  .value("PseudoVSLIDE1DOWN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1_MASK)
  .value("PseudoVSLIDE1DOWN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2)
  .value("PseudoVSLIDE1DOWN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2_MASK)
  .value("PseudoVSLIDE1DOWN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4)
  .value("PseudoVSLIDE1DOWN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4_MASK)
  .value("PseudoVSLIDE1DOWN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8)
  .value("PseudoVSLIDE1DOWN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8_MASK)
  .value("PseudoVSLIDE1DOWN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2)
  .value("PseudoVSLIDE1DOWN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2_MASK)
  .value("PseudoVSLIDE1DOWN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4)
  .value("PseudoVSLIDE1DOWN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4_MASK)
  .value("PseudoVSLIDE1DOWN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8)
  .value("PseudoVSLIDE1DOWN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8_MASK)
  .value("PseudoVSLIDE1UP_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1)
  .value("PseudoVSLIDE1UP_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1_MASK)
  .value("PseudoVSLIDE1UP_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2)
  .value("PseudoVSLIDE1UP_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2_MASK)
  .value("PseudoVSLIDE1UP_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4)
  .value("PseudoVSLIDE1UP_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4_MASK)
  .value("PseudoVSLIDE1UP_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8)
  .value("PseudoVSLIDE1UP_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8_MASK)
  .value("PseudoVSLIDE1UP_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2)
  .value("PseudoVSLIDE1UP_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2_MASK)
  .value("PseudoVSLIDE1UP_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4)
  .value("PseudoVSLIDE1UP_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4_MASK)
  .value("PseudoVSLIDE1UP_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8)
  .value("PseudoVSLIDE1UP_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8_MASK)
  .value("PseudoVSLIDEDOWN_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1)
  .value("PseudoVSLIDEDOWN_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1_MASK)
  .value("PseudoVSLIDEDOWN_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2)
  .value("PseudoVSLIDEDOWN_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2_MASK)
  .value("PseudoVSLIDEDOWN_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4)
  .value("PseudoVSLIDEDOWN_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4_MASK)
  .value("PseudoVSLIDEDOWN_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8)
  .value("PseudoVSLIDEDOWN_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8_MASK)
  .value("PseudoVSLIDEDOWN_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2)
  .value("PseudoVSLIDEDOWN_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2_MASK)
  .value("PseudoVSLIDEDOWN_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4)
  .value("PseudoVSLIDEDOWN_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4_MASK)
  .value("PseudoVSLIDEDOWN_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8)
  .value("PseudoVSLIDEDOWN_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8_MASK)
  .value("PseudoVSLIDEDOWN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1)
  .value("PseudoVSLIDEDOWN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1_MASK)
  .value("PseudoVSLIDEDOWN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2)
  .value("PseudoVSLIDEDOWN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2_MASK)
  .value("PseudoVSLIDEDOWN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4)
  .value("PseudoVSLIDEDOWN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4_MASK)
  .value("PseudoVSLIDEDOWN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8)
  .value("PseudoVSLIDEDOWN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8_MASK)
  .value("PseudoVSLIDEDOWN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2)
  .value("PseudoVSLIDEDOWN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2_MASK)
  .value("PseudoVSLIDEDOWN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4)
  .value("PseudoVSLIDEDOWN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4_MASK)
  .value("PseudoVSLIDEDOWN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8)
  .value("PseudoVSLIDEDOWN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8_MASK)
  .value("PseudoVSLIDEUP_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1)
  .value("PseudoVSLIDEUP_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1_MASK)
  .value("PseudoVSLIDEUP_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2)
  .value("PseudoVSLIDEUP_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2_MASK)
  .value("PseudoVSLIDEUP_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4)
  .value("PseudoVSLIDEUP_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4_MASK)
  .value("PseudoVSLIDEUP_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8)
  .value("PseudoVSLIDEUP_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8_MASK)
  .value("PseudoVSLIDEUP_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2)
  .value("PseudoVSLIDEUP_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2_MASK)
  .value("PseudoVSLIDEUP_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4)
  .value("PseudoVSLIDEUP_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4_MASK)
  .value("PseudoVSLIDEUP_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8)
  .value("PseudoVSLIDEUP_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8_MASK)
  .value("PseudoVSLIDEUP_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1)
  .value("PseudoVSLIDEUP_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1_MASK)
  .value("PseudoVSLIDEUP_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2)
  .value("PseudoVSLIDEUP_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2_MASK)
  .value("PseudoVSLIDEUP_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4)
  .value("PseudoVSLIDEUP_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4_MASK)
  .value("PseudoVSLIDEUP_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8)
  .value("PseudoVSLIDEUP_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8_MASK)
  .value("PseudoVSLIDEUP_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2)
  .value("PseudoVSLIDEUP_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2_MASK)
  .value("PseudoVSLIDEUP_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4)
  .value("PseudoVSLIDEUP_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4_MASK)
  .value("PseudoVSLIDEUP_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8)
  .value("PseudoVSLIDEUP_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8_MASK)
  .value("PseudoVSLL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1)
  .value("PseudoVSLL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1_MASK)
  .value("PseudoVSLL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2)
  .value("PseudoVSLL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2_MASK)
  .value("PseudoVSLL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4)
  .value("PseudoVSLL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4_MASK)
  .value("PseudoVSLL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8)
  .value("PseudoVSLL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8_MASK)
  .value("PseudoVSLL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2)
  .value("PseudoVSLL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2_MASK)
  .value("PseudoVSLL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4)
  .value("PseudoVSLL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4_MASK)
  .value("PseudoVSLL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8)
  .value("PseudoVSLL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8_MASK)
  .value("PseudoVSLL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1)
  .value("PseudoVSLL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1_MASK)
  .value("PseudoVSLL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2)
  .value("PseudoVSLL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2_MASK)
  .value("PseudoVSLL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4)
  .value("PseudoVSLL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4_MASK)
  .value("PseudoVSLL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8)
  .value("PseudoVSLL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8_MASK)
  .value("PseudoVSLL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2)
  .value("PseudoVSLL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2_MASK)
  .value("PseudoVSLL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4)
  .value("PseudoVSLL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4_MASK)
  .value("PseudoVSLL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8)
  .value("PseudoVSLL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8_MASK)
  .value("PseudoVSLL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1)
  .value("PseudoVSLL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1_MASK)
  .value("PseudoVSLL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2)
  .value("PseudoVSLL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2_MASK)
  .value("PseudoVSLL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4)
  .value("PseudoVSLL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4_MASK)
  .value("PseudoVSLL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8)
  .value("PseudoVSLL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8_MASK)
  .value("PseudoVSLL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2)
  .value("PseudoVSLL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2_MASK)
  .value("PseudoVSLL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4)
  .value("PseudoVSLL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4_MASK)
  .value("PseudoVSLL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8)
  .value("PseudoVSLL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8_MASK)
  .value("PseudoVSM3C_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M1)
  .value("PseudoVSM3C_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M2)
  .value("PseudoVSM3C_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M4)
  .value("PseudoVSM3C_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M8)
  .value("PseudoVSM3C_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_MF2)
  .value("PseudoVSM3ME_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M1)
  .value("PseudoVSM3ME_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M2)
  .value("PseudoVSM3ME_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M4)
  .value("PseudoVSM3ME_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M8)
  .value("PseudoVSM3ME_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_MF2)
  .value("PseudoVSM4K_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M1)
  .value("PseudoVSM4K_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M2)
  .value("PseudoVSM4K_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M4)
  .value("PseudoVSM4K_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M8)
  .value("PseudoVSM4K_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_MF2)
  .value("PseudoVSM4R_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_M1)
  .value("PseudoVSM4R_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF2)
  .value("PseudoVSM4R_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF4)
  .value("PseudoVSM4R_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF8)
  .value("PseudoVSM4R_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M1)
  .value("PseudoVSM4R_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M2)
  .value("PseudoVSM4R_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF2)
  .value("PseudoVSM4R_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF4)
  .value("PseudoVSM4R_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF8)
  .value("PseudoVSM4R_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M1)
  .value("PseudoVSM4R_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M2)
  .value("PseudoVSM4R_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M4)
  .value("PseudoVSM4R_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF2)
  .value("PseudoVSM4R_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF4)
  .value("PseudoVSM4R_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF8)
  .value("PseudoVSM4R_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M1)
  .value("PseudoVSM4R_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M2)
  .value("PseudoVSM4R_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M4)
  .value("PseudoVSM4R_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF2)
  .value("PseudoVSM4R_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF4)
  .value("PseudoVSM4R_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF8)
  .value("PseudoVSM4R_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF2)
  .value("PseudoVSM4R_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF4)
  .value("PseudoVSM4R_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF8)
  .value("PseudoVSM4R_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M1)
  .value("PseudoVSM4R_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M2)
  .value("PseudoVSM4R_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M4)
  .value("PseudoVSM4R_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M8)
  .value("PseudoVSM4R_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_MF2)
  .value("PseudoVSMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1)
  .value("PseudoVSMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1_MASK)
  .value("PseudoVSMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2)
  .value("PseudoVSMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2_MASK)
  .value("PseudoVSMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4)
  .value("PseudoVSMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4_MASK)
  .value("PseudoVSMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8)
  .value("PseudoVSMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8_MASK)
  .value("PseudoVSMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2)
  .value("PseudoVSMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2_MASK)
  .value("PseudoVSMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4)
  .value("PseudoVSMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4_MASK)
  .value("PseudoVSMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8)
  .value("PseudoVSMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8_MASK)
  .value("PseudoVSMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1)
  .value("PseudoVSMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1_MASK)
  .value("PseudoVSMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2)
  .value("PseudoVSMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2_MASK)
  .value("PseudoVSMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4)
  .value("PseudoVSMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4_MASK)
  .value("PseudoVSMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8)
  .value("PseudoVSMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8_MASK)
  .value("PseudoVSMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2)
  .value("PseudoVSMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2_MASK)
  .value("PseudoVSMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4)
  .value("PseudoVSMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4_MASK)
  .value("PseudoVSMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8)
  .value("PseudoVSMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8_MASK)
  .value("PseudoVSM_V_B1", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B1)
  .value("PseudoVSM_V_B16", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B16)
  .value("PseudoVSM_V_B2", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B2)
  .value("PseudoVSM_V_B32", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B32)
  .value("PseudoVSM_V_B4", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B4)
  .value("PseudoVSM_V_B64", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B64)
  .value("PseudoVSM_V_B8", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B8)
  .value("PseudoVSOXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1)
  .value("PseudoVSOXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1_MASK)
  .value("PseudoVSOXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2)
  .value("PseudoVSOXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2_MASK)
  .value("PseudoVSOXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4)
  .value("PseudoVSOXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4_MASK)
  .value("PseudoVSOXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2)
  .value("PseudoVSOXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2_MASK)
  .value("PseudoVSOXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1)
  .value("PseudoVSOXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1_MASK)
  .value("PseudoVSOXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2)
  .value("PseudoVSOXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2_MASK)
  .value("PseudoVSOXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4)
  .value("PseudoVSOXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4_MASK)
  .value("PseudoVSOXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8)
  .value("PseudoVSOXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8_MASK)
  .value("PseudoVSOXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2)
  .value("PseudoVSOXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2_MASK)
  .value("PseudoVSOXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4)
  .value("PseudoVSOXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4_MASK)
  .value("PseudoVSOXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8)
  .value("PseudoVSOXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8_MASK)
  .value("PseudoVSOXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4)
  .value("PseudoVSOXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4_MASK)
  .value("PseudoVSOXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8);
  opcodes.value("PseudoVSOXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8_MASK)
  .value("PseudoVSOXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1)
  .value("PseudoVSOXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1_MASK)
  .value("PseudoVSOXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2)
  .value("PseudoVSOXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2_MASK)
  .value("PseudoVSOXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2)
  .value("PseudoVSOXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4)
  .value("PseudoVSOXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1)
  .value("PseudoVSOXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1_MASK)
  .value("PseudoVSOXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2)
  .value("PseudoVSOXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4)
  .value("PseudoVSOXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8)
  .value("PseudoVSOXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1)
  .value("PseudoVSOXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1_MASK)
  .value("PseudoVSOXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2)
  .value("PseudoVSOXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2_MASK)
  .value("PseudoVSOXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2)
  .value("PseudoVSOXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2_MASK)
  .value("PseudoVSOXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4)
  .value("PseudoVSOXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4_MASK)
  .value("PseudoVSOXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1)
  .value("PseudoVSOXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1_MASK)
  .value("PseudoVSOXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2)
  .value("PseudoVSOXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2_MASK)
  .value("PseudoVSOXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4)
  .value("PseudoVSOXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4_MASK)
  .value("PseudoVSOXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2)
  .value("PseudoVSOXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2_MASK)
  .value("PseudoVSOXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1)
  .value("PseudoVSOXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1_MASK)
  .value("PseudoVSOXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2)
  .value("PseudoVSOXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2_MASK)
  .value("PseudoVSOXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4)
  .value("PseudoVSOXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4_MASK)
  .value("PseudoVSOXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8)
  .value("PseudoVSOXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8_MASK)
  .value("PseudoVSOXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2)
  .value("PseudoVSOXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2_MASK)
  .value("PseudoVSOXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4)
  .value("PseudoVSOXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4_MASK)
  .value("PseudoVSOXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8)
  .value("PseudoVSOXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8_MASK)
  .value("PseudoVSOXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1)
  .value("PseudoVSOXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1_MASK)
  .value("PseudoVSOXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2)
  .value("PseudoVSOXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4)
  .value("PseudoVSOXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8)
  .value("PseudoVSOXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1)
  .value("PseudoVSOXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1_MASK)
  .value("PseudoVSOXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2)
  .value("PseudoVSOXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2_MASK)
  .value("PseudoVSOXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4)
  .value("PseudoVSOXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4_MASK)
  .value("PseudoVSOXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8)
  .value("PseudoVSOXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8_MASK)
  .value("PseudoVSOXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1)
  .value("PseudoVSOXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1_MASK)
  .value("PseudoVSOXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2)
  .value("PseudoVSOXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2_MASK)
  .value("PseudoVSOXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2)
  .value("PseudoVSOXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2_MASK)
  .value("PseudoVSOXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4)
  .value("PseudoVSOXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4_MASK)
  .value("PseudoVSOXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1)
  .value("PseudoVSOXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1_MASK)
  .value("PseudoVSOXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2)
  .value("PseudoVSOXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2_MASK)
  .value("PseudoVSOXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4)
  .value("PseudoVSOXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4_MASK)
  .value("PseudoVSOXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2)
  .value("PseudoVSOXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2_MASK)
  .value("PseudoVSOXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1)
  .value("PseudoVSOXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1_MASK)
  .value("PseudoVSOXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2)
  .value("PseudoVSOXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2_MASK)
  .value("PseudoVSOXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4)
  .value("PseudoVSOXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4_MASK)
  .value("PseudoVSOXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8)
  .value("PseudoVSOXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8_MASK)
  .value("PseudoVSOXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1)
  .value("PseudoVSOXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1_MASK)
  .value("PseudoVSOXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2)
  .value("PseudoVSOXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2_MASK)
  .value("PseudoVSOXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4)
  .value("PseudoVSOXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4_MASK)
  .value("PseudoVSOXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8)
  .value("PseudoVSOXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8_MASK)
  .value("PseudoVSOXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2)
  .value("PseudoVSOXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2_MASK)
  .value("PseudoVSOXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4)
  .value("PseudoVSOXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4_MASK)
  .value("PseudoVSOXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8)
  .value("PseudoVSOXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8_MASK)
  .value("PseudoVSOXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4)
  .value("PseudoVSOXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4_MASK)
  .value("PseudoVSOXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8)
  .value("PseudoVSOXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8_MASK)
  .value("PseudoVSOXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8)
  .value("PseudoVSOXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8_MASK)
  .value("PseudoVSOXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1)
  .value("PseudoVSOXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1_MASK)
  .value("PseudoVSOXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2)
  .value("PseudoVSOXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2_MASK)
  .value("PseudoVSOXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4)
  .value("PseudoVSOXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4_MASK)
  .value("PseudoVSOXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2)
  .value("PseudoVSOXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1)
  .value("PseudoVSOXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1_MASK)
  .value("PseudoVSOXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2)
  .value("PseudoVSOXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2_MASK)
  .value("PseudoVSOXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2)
  .value("PseudoVSOXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4)
  .value("PseudoVSOXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1)
  .value("PseudoVSOXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1_MASK)
  .value("PseudoVSOXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2)
  .value("PseudoVSOXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4)
  .value("PseudoVSOXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8)
  .value("PseudoVSOXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1)
  .value("PseudoVSOXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2)
  .value("PseudoVSOXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2_MASK)
  .value("PseudoVSOXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4)
  .value("PseudoVSOXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4_MASK)
  .value("PseudoVSOXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2)
  .value("PseudoVSOXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1)
  .value("PseudoVSOXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2)
  .value("PseudoVSOXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2_MASK)
  .value("PseudoVSOXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4)
  .value("PseudoVSOXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4_MASK)
  .value("PseudoVSOXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2)
  .value("PseudoVSOXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2_MASK)
  .value("PseudoVSOXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4)
  .value("PseudoVSOXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4_MASK)
  .value("PseudoVSOXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4)
  .value("PseudoVSOXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1)
  .value("PseudoVSOXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2)
  .value("PseudoVSOXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1)
  .value("PseudoVSOXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1)
  .value("PseudoVSOXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2)
  .value("PseudoVSOXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2)
  .value("PseudoVSOXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4)
  .value("PseudoVSOXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1)
  .value("PseudoVSOXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2)
  .value("PseudoVSOXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4)
  .value("PseudoVSOXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4_MASK)
  .value("PseudoVSOXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2)
  .value("PseudoVSOXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1)
  .value("PseudoVSOXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2)
  .value("PseudoVSOXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4)
  .value("PseudoVSOXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4_MASK)
  .value("PseudoVSOXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2)
  .value("PseudoVSOXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2_MASK)
  .value("PseudoVSOXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4)
  .value("PseudoVSOXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4_MASK)
  .value("PseudoVSOXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1)
  .value("PseudoVSOXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1)
  .value("PseudoVSOXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2)
  .value("PseudoVSOXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4)
  .value("PseudoVSOXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8)
  .value("PseudoVSOXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1)
  .value("PseudoVSOXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2)
  .value("PseudoVSOXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2)
  .value("PseudoVSOXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4)
  .value("PseudoVSOXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1)
  .value("PseudoVSOXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2)
  .value("PseudoVSOXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4)
  .value("PseudoVSOXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4_MASK)
  .value("PseudoVSOXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2)
  .value("PseudoVSOXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1)
  .value("PseudoVSOXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2)
  .value("PseudoVSOXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2_MASK)
  .value("PseudoVSOXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4)
  .value("PseudoVSOXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4_MASK)
  .value("PseudoVSOXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1)
  .value("PseudoVSOXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2)
  .value("PseudoVSOXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2_MASK)
  .value("PseudoVSOXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4)
  .value("PseudoVSOXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4_MASK)
  .value("PseudoVSOXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2)
  .value("PseudoVSOXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2_MASK)
  .value("PseudoVSOXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4)
  .value("PseudoVSOXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4_MASK)
  .value("PseudoVSOXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4)
  .value("PseudoVSOXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1)
  .value("PseudoVSOXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2)
  .value("PseudoVSOXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4)
  .value("PseudoVSOXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1)
  .value("PseudoVSOXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2)
  .value("PseudoVSOXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1)
  .value("PseudoVSOXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1)
  .value("PseudoVSOXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2)
  .value("PseudoVSOXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2_MASK)
  .value("PseudoVSOXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2)
  .value("PseudoVSOXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1)
  .value("PseudoVSOXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2)
  .value("PseudoVSOXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2_MASK)
  .value("PseudoVSOXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2)
  .value("PseudoVSOXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1)
  .value("PseudoVSOXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2)
  .value("PseudoVSOXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1)
  .value("PseudoVSOXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1)
  .value("PseudoVSOXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2)
  .value("PseudoVSOXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2_MASK)
  .value("PseudoVSOXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2);
  opcodes.value("PseudoVSOXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4)
  .value("PseudoVSOXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1)
  .value("PseudoVSOXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2)
  .value("PseudoVSOXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2_MASK)
  .value("PseudoVSOXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2)
  .value("PseudoVSOXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1)
  .value("PseudoVSOXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2)
  .value("PseudoVSOXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2_MASK)
  .value("PseudoVSOXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2)
  .value("PseudoVSOXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2_MASK)
  .value("PseudoVSOXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1)
  .value("PseudoVSOXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1)
  .value("PseudoVSOXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2)
  .value("PseudoVSOXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4)
  .value("PseudoVSOXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8)
  .value("PseudoVSOXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1)
  .value("PseudoVSOXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2)
  .value("PseudoVSOXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2_MASK)
  .value("PseudoVSOXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2)
  .value("PseudoVSOXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4)
  .value("PseudoVSOXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1)
  .value("PseudoVSOXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2)
  .value("PseudoVSOXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2_MASK)
  .value("PseudoVSOXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2)
  .value("PseudoVSOXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1)
  .value("PseudoVSOXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2)
  .value("PseudoVSOXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2_MASK)
  .value("PseudoVSOXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1)
  .value("PseudoVSOXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2)
  .value("PseudoVSOXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2_MASK)
  .value("PseudoVSOXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2)
  .value("PseudoVSOXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1)
  .value("PseudoVSOXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2)
  .value("PseudoVSOXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1)
  .value("PseudoVSOXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2)
  .value("PseudoVSOXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1)
  .value("PseudoVSOXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1)
  .value("PseudoVSOXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2)
  .value("PseudoVSOXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2_MASK)
  .value("PseudoVSOXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2)
  .value("PseudoVSOXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1)
  .value("PseudoVSOXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2)
  .value("PseudoVSOXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2_MASK)
  .value("PseudoVSOXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2)
  .value("PseudoVSOXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1)
  .value("PseudoVSOXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2)
  .value("PseudoVSOXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1)
  .value("PseudoVSOXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1)
  .value("PseudoVSOXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2)
  .value("PseudoVSOXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2_MASK)
  .value("PseudoVSOXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2)
  .value("PseudoVSOXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4)
  .value("PseudoVSOXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1)
  .value("PseudoVSOXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2)
  .value("PseudoVSOXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2_MASK)
  .value("PseudoVSOXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2)
  .value("PseudoVSOXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1)
  .value("PseudoVSOXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2)
  .value("PseudoVSOXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2_MASK)
  .value("PseudoVSOXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2)
  .value("PseudoVSOXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2_MASK)
  .value("PseudoVSOXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1)
  .value("PseudoVSOXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1)
  .value("PseudoVSOXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2)
  .value("PseudoVSOXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4)
  .value("PseudoVSOXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8)
  .value("PseudoVSOXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1)
  .value("PseudoVSOXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2)
  .value("PseudoVSOXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2_MASK)
  .value("PseudoVSOXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2)
  .value("PseudoVSOXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4)
  .value("PseudoVSOXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1)
  .value("PseudoVSOXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2)
  .value("PseudoVSOXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2_MASK)
  .value("PseudoVSOXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2)
  .value("PseudoVSOXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1)
  .value("PseudoVSOXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2)
  .value("PseudoVSOXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2_MASK)
  .value("PseudoVSOXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1)
  .value("PseudoVSOXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2)
  .value("PseudoVSOXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2_MASK)
  .value("PseudoVSOXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2)
  .value("PseudoVSOXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1)
  .value("PseudoVSOXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2)
  .value("PseudoVSOXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1)
  .value("PseudoVSOXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2)
  .value("PseudoVSOXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1)
  .value("PseudoVSOXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1)
  .value("PseudoVSOXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2)
  .value("PseudoVSOXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1)
  .value("PseudoVSOXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1)
  .value("PseudoVSOXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1)
  .value("PseudoVSOXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1)
  .value("PseudoVSOXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2)
  .value("PseudoVSOXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4)
  .value("PseudoVSOXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1)
  .value("PseudoVSOXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2)
  .value("PseudoVSOXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1)
  .value("PseudoVSOXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1)
  .value("PseudoVSOXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1)
  .value("PseudoVSOXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2)
  .value("PseudoVSOXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4)
  .value("PseudoVSOXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8)
  .value("PseudoVSOXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1)
  .value("PseudoVSOXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2)
  .value("PseudoVSOXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4)
  .value("PseudoVSOXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1)
  .value("PseudoVSOXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2)
  .value("PseudoVSOXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1)
  .value("PseudoVSOXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1)
  .value("PseudoVSOXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1)
  .value("PseudoVSOXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1)
  .value("PseudoVSOXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1)
  .value("PseudoVSOXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1)
  .value("PseudoVSOXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2)
  .value("PseudoVSOXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1)
  .value("PseudoVSOXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1)
  .value("PseudoVSOXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1)
  .value("PseudoVSOXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1)
  .value("PseudoVSOXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2)
  .value("PseudoVSOXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4)
  .value("PseudoVSOXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1)
  .value("PseudoVSOXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2)
  .value("PseudoVSOXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1)
  .value("PseudoVSOXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1);
  opcodes.value("PseudoVSOXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1)
  .value("PseudoVSOXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2)
  .value("PseudoVSOXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4)
  .value("PseudoVSOXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8)
  .value("PseudoVSOXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1)
  .value("PseudoVSOXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2)
  .value("PseudoVSOXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4)
  .value("PseudoVSOXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1)
  .value("PseudoVSOXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2)
  .value("PseudoVSOXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1)
  .value("PseudoVSOXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1)
  .value("PseudoVSOXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1)
  .value("PseudoVSOXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1)
  .value("PseudoVSOXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1)
  .value("PseudoVSOXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1)
  .value("PseudoVSOXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2)
  .value("PseudoVSOXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1)
  .value("PseudoVSOXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1)
  .value("PseudoVSOXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1)
  .value("PseudoVSOXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1)
  .value("PseudoVSOXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2)
  .value("PseudoVSOXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4)
  .value("PseudoVSOXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1)
  .value("PseudoVSOXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2)
  .value("PseudoVSOXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1)
  .value("PseudoVSOXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1)
  .value("PseudoVSOXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1)
  .value("PseudoVSOXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2)
  .value("PseudoVSOXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4)
  .value("PseudoVSOXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8)
  .value("PseudoVSOXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1)
  .value("PseudoVSOXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2)
  .value("PseudoVSOXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4)
  .value("PseudoVSOXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1)
  .value("PseudoVSOXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2)
  .value("PseudoVSOXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1)
  .value("PseudoVSOXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1)
  .value("PseudoVSOXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1)
  .value("PseudoVSOXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1)
  .value("PseudoVSOXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1)
  .value("PseudoVSOXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK)
  .value("PseudoVSOXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1)
  .value("PseudoVSOXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1_MASK)
  .value("PseudoVSOXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2)
  .value("PseudoVSOXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1)
  .value("PseudoVSOXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1)
  .value("PseudoVSOXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2)
  .value("PseudoVSOXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4)
  .value("PseudoVSOXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1)
  .value("PseudoVSOXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8)
  .value("PseudoVSOXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK)
  .value("PseudoVSOXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1)
  .value("PseudoVSOXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1_MASK)
  .value("PseudoVSOXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2)
  .value("PseudoVSOXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4)
  .value("PseudoVSOXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1)
  .value("PseudoVSOXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1_MASK)
  .value("PseudoVSOXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2)
  .value("PseudoVSOXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1)
  .value("PseudoVSOXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1_MASK)
  .value("PseudoVSOXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1)
  .value("PseudoVSOXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8)
  .value("PseudoVSOXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK)
  .value("PseudoVSOXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1)
  .value("PseudoVSOXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1_MASK)
  .value("PseudoVSOXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2)
  .value("PseudoVSOXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2_MASK)
  .value("PseudoVSOXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4)
  .value("PseudoVSOXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4_MASK)
  .value("PseudoVSOXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8)
  .value("PseudoVSOXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8_MASK)
  .value("PseudoVSOXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1)
  .value("PseudoVSOXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1_MASK)
  .value("PseudoVSOXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2)
  .value("PseudoVSOXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2_MASK)
  .value("PseudoVSOXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4)
  .value("PseudoVSOXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4_MASK)
  .value("PseudoVSOXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1)
  .value("PseudoVSOXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1_MASK)
  .value("PseudoVSOXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2)
  .value("PseudoVSOXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2_MASK)
  .value("PseudoVSOXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1)
  .value("PseudoVSOXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1_MASK)
  .value("PseudoVSOXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1)
  .value("PseudoVSOXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1)
  .value("PseudoVSOXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2)
  .value("PseudoVSOXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1)
  .value("PseudoVSOXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2)
  .value("PseudoVSOXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4)
  .value("PseudoVSOXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1)
  .value("PseudoVSOXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8)
  .value("PseudoVSOXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK)
  .value("PseudoVSPILL2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M1)
  .value("PseudoVSPILL2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M2)
  .value("PseudoVSPILL2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M4)
  .value("PseudoVSPILL2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF2)
  .value("PseudoVSPILL2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF4)
  .value("PseudoVSPILL2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF8)
  .value("PseudoVSPILL3_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M1)
  .value("PseudoVSPILL3_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M2)
  .value("PseudoVSPILL3_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF2)
  .value("PseudoVSPILL3_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF4)
  .value("PseudoVSPILL3_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF8)
  .value("PseudoVSPILL4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M1)
  .value("PseudoVSPILL4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M2)
  .value("PseudoVSPILL4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF2)
  .value("PseudoVSPILL4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF4)
  .value("PseudoVSPILL4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF8)
  .value("PseudoVSPILL5_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_M1)
  .value("PseudoVSPILL5_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF2)
  .value("PseudoVSPILL5_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF4)
  .value("PseudoVSPILL5_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF8)
  .value("PseudoVSPILL6_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_M1)
  .value("PseudoVSPILL6_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF2)
  .value("PseudoVSPILL6_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF4)
  .value("PseudoVSPILL6_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF8)
  .value("PseudoVSPILL7_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_M1)
  .value("PseudoVSPILL7_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF2)
  .value("PseudoVSPILL7_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF4)
  .value("PseudoVSPILL7_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF8)
  .value("PseudoVSPILL8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_M1)
  .value("PseudoVSPILL8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF2)
  .value("PseudoVSPILL8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF4)
  .value("PseudoVSPILL8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF8)
  .value("PseudoVSRA_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1)
  .value("PseudoVSRA_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1_MASK)
  .value("PseudoVSRA_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2)
  .value("PseudoVSRA_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2_MASK)
  .value("PseudoVSRA_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4)
  .value("PseudoVSRA_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4_MASK)
  .value("PseudoVSRA_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8)
  .value("PseudoVSRA_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8_MASK)
  .value("PseudoVSRA_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2)
  .value("PseudoVSRA_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2_MASK)
  .value("PseudoVSRA_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4)
  .value("PseudoVSRA_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4_MASK)
  .value("PseudoVSRA_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8)
  .value("PseudoVSRA_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8_MASK)
  .value("PseudoVSRA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1)
  .value("PseudoVSRA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1_MASK)
  .value("PseudoVSRA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2)
  .value("PseudoVSRA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2_MASK)
  .value("PseudoVSRA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4)
  .value("PseudoVSRA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4_MASK)
  .value("PseudoVSRA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8)
  .value("PseudoVSRA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8_MASK)
  .value("PseudoVSRA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2)
  .value("PseudoVSRA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2_MASK)
  .value("PseudoVSRA_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4)
  .value("PseudoVSRA_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4_MASK)
  .value("PseudoVSRA_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8)
  .value("PseudoVSRA_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8_MASK)
  .value("PseudoVSRA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1)
  .value("PseudoVSRA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1_MASK)
  .value("PseudoVSRA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2)
  .value("PseudoVSRA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2_MASK)
  .value("PseudoVSRA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4)
  .value("PseudoVSRA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4_MASK)
  .value("PseudoVSRA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8)
  .value("PseudoVSRA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8_MASK)
  .value("PseudoVSRA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2)
  .value("PseudoVSRA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2_MASK)
  .value("PseudoVSRA_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4)
  .value("PseudoVSRA_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4_MASK)
  .value("PseudoVSRA_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8)
  .value("PseudoVSRA_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8_MASK)
  .value("PseudoVSRL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1)
  .value("PseudoVSRL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1_MASK)
  .value("PseudoVSRL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2)
  .value("PseudoVSRL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2_MASK)
  .value("PseudoVSRL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4)
  .value("PseudoVSRL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4_MASK)
  .value("PseudoVSRL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8)
  .value("PseudoVSRL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8_MASK)
  .value("PseudoVSRL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2)
  .value("PseudoVSRL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2_MASK)
  .value("PseudoVSRL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4)
  .value("PseudoVSRL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4_MASK)
  .value("PseudoVSRL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8)
  .value("PseudoVSRL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8_MASK)
  .value("PseudoVSRL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1)
  .value("PseudoVSRL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1_MASK)
  .value("PseudoVSRL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2)
  .value("PseudoVSRL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2_MASK)
  .value("PseudoVSRL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4);
  opcodes.value("PseudoVSRL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4_MASK)
  .value("PseudoVSRL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8)
  .value("PseudoVSRL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8_MASK)
  .value("PseudoVSRL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2)
  .value("PseudoVSRL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2_MASK)
  .value("PseudoVSRL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4)
  .value("PseudoVSRL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4_MASK)
  .value("PseudoVSRL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8)
  .value("PseudoVSRL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8_MASK)
  .value("PseudoVSRL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1)
  .value("PseudoVSRL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1_MASK)
  .value("PseudoVSRL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2)
  .value("PseudoVSRL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2_MASK)
  .value("PseudoVSRL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4)
  .value("PseudoVSRL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4_MASK)
  .value("PseudoVSRL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8)
  .value("PseudoVSRL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8_MASK)
  .value("PseudoVSRL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2)
  .value("PseudoVSRL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2_MASK)
  .value("PseudoVSRL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4)
  .value("PseudoVSRL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4_MASK)
  .value("PseudoVSRL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8)
  .value("PseudoVSRL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8_MASK)
  .value("PseudoVSSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1)
  .value("PseudoVSSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1_MASK)
  .value("PseudoVSSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2)
  .value("PseudoVSSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2_MASK)
  .value("PseudoVSSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4)
  .value("PseudoVSSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4_MASK)
  .value("PseudoVSSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8)
  .value("PseudoVSSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8_MASK)
  .value("PseudoVSSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2)
  .value("PseudoVSSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2_MASK)
  .value("PseudoVSSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4)
  .value("PseudoVSSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4_MASK)
  .value("PseudoVSSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1)
  .value("PseudoVSSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1_MASK)
  .value("PseudoVSSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2)
  .value("PseudoVSSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2_MASK)
  .value("PseudoVSSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4)
  .value("PseudoVSSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4_MASK)
  .value("PseudoVSSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8)
  .value("PseudoVSSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8_MASK)
  .value("PseudoVSSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2)
  .value("PseudoVSSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2_MASK)
  .value("PseudoVSSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1)
  .value("PseudoVSSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1_MASK)
  .value("PseudoVSSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2)
  .value("PseudoVSSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2_MASK)
  .value("PseudoVSSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4)
  .value("PseudoVSSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4_MASK)
  .value("PseudoVSSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8)
  .value("PseudoVSSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8_MASK)
  .value("PseudoVSSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1)
  .value("PseudoVSSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1_MASK)
  .value("PseudoVSSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2)
  .value("PseudoVSSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2_MASK)
  .value("PseudoVSSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4)
  .value("PseudoVSSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4_MASK)
  .value("PseudoVSSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8)
  .value("PseudoVSSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8_MASK)
  .value("PseudoVSSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2)
  .value("PseudoVSSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2_MASK)
  .value("PseudoVSSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4)
  .value("PseudoVSSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4_MASK)
  .value("PseudoVSSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8)
  .value("PseudoVSSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8_MASK)
  .value("PseudoVSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1)
  .value("PseudoVSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1_MASK)
  .value("PseudoVSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2)
  .value("PseudoVSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2_MASK)
  .value("PseudoVSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4)
  .value("PseudoVSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4_MASK)
  .value("PseudoVSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2)
  .value("PseudoVSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2_MASK)
  .value("PseudoVSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4)
  .value("PseudoVSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4_MASK)
  .value("PseudoVSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1)
  .value("PseudoVSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1_MASK)
  .value("PseudoVSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2)
  .value("PseudoVSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2_MASK)
  .value("PseudoVSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4)
  .value("PseudoVSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4_MASK)
  .value("PseudoVSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2)
  .value("PseudoVSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2_MASK)
  .value("PseudoVSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1)
  .value("PseudoVSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1_MASK)
  .value("PseudoVSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2)
  .value("PseudoVSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2_MASK)
  .value("PseudoVSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4)
  .value("PseudoVSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4_MASK)
  .value("PseudoVSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1)
  .value("PseudoVSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1_MASK)
  .value("PseudoVSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2)
  .value("PseudoVSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2_MASK)
  .value("PseudoVSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4)
  .value("PseudoVSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4_MASK)
  .value("PseudoVSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2)
  .value("PseudoVSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2_MASK)
  .value("PseudoVSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4)
  .value("PseudoVSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4_MASK)
  .value("PseudoVSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8)
  .value("PseudoVSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8_MASK)
  .value("PseudoVSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1)
  .value("PseudoVSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1_MASK)
  .value("PseudoVSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2)
  .value("PseudoVSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2_MASK)
  .value("PseudoVSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2)
  .value("PseudoVSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2_MASK)
  .value("PseudoVSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4)
  .value("PseudoVSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4_MASK)
  .value("PseudoVSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1)
  .value("PseudoVSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1_MASK)
  .value("PseudoVSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2)
  .value("PseudoVSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2_MASK)
  .value("PseudoVSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2)
  .value("PseudoVSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2_MASK)
  .value("PseudoVSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1)
  .value("PseudoVSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1_MASK)
  .value("PseudoVSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2)
  .value("PseudoVSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2_MASK)
  .value("PseudoVSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1)
  .value("PseudoVSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1_MASK)
  .value("PseudoVSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2)
  .value("PseudoVSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2_MASK)
  .value("PseudoVSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2)
  .value("PseudoVSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2_MASK)
  .value("PseudoVSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4)
  .value("PseudoVSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4_MASK)
  .value("PseudoVSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8)
  .value("PseudoVSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8_MASK)
  .value("PseudoVSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1)
  .value("PseudoVSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1_MASK)
  .value("PseudoVSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2)
  .value("PseudoVSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2_MASK)
  .value("PseudoVSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2)
  .value("PseudoVSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2_MASK)
  .value("PseudoVSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4)
  .value("PseudoVSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4_MASK)
  .value("PseudoVSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1)
  .value("PseudoVSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1_MASK)
  .value("PseudoVSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2)
  .value("PseudoVSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2_MASK)
  .value("PseudoVSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2)
  .value("PseudoVSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2_MASK)
  .value("PseudoVSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1)
  .value("PseudoVSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1_MASK)
  .value("PseudoVSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2)
  .value("PseudoVSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2_MASK)
  .value("PseudoVSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1)
  .value("PseudoVSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1_MASK)
  .value("PseudoVSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2)
  .value("PseudoVSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2_MASK)
  .value("PseudoVSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2)
  .value("PseudoVSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2_MASK)
  .value("PseudoVSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4)
  .value("PseudoVSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4_MASK)
  .value("PseudoVSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8)
  .value("PseudoVSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8_MASK)
  .value("PseudoVSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1)
  .value("PseudoVSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1_MASK)
  .value("PseudoVSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2)
  .value("PseudoVSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2_MASK)
  .value("PseudoVSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4)
  .value("PseudoVSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4_MASK)
  .value("PseudoVSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1)
  .value("PseudoVSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1_MASK)
  .value("PseudoVSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2)
  .value("PseudoVSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2_MASK)
  .value("PseudoVSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1)
  .value("PseudoVSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1_MASK)
  .value("PseudoVSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1)
  .value("PseudoVSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1_MASK)
  .value("PseudoVSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2)
  .value("PseudoVSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2_MASK)
  .value("PseudoVSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4)
  .value("PseudoVSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4_MASK)
  .value("PseudoVSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8)
  .value("PseudoVSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8_MASK)
  .value("PseudoVSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1)
  .value("PseudoVSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1_MASK)
  .value("PseudoVSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2)
  .value("PseudoVSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2_MASK)
  .value("PseudoVSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4)
  .value("PseudoVSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4_MASK)
  .value("PseudoVSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1)
  .value("PseudoVSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1_MASK)
  .value("PseudoVSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2)
  .value("PseudoVSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2_MASK)
  .value("PseudoVSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1)
  .value("PseudoVSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1_MASK)
  .value("PseudoVSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1)
  .value("PseudoVSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1_MASK)
  .value("PseudoVSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2)
  .value("PseudoVSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2_MASK)
  .value("PseudoVSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4)
  .value("PseudoVSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4_MASK)
  .value("PseudoVSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8)
  .value("PseudoVSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8_MASK)
  .value("PseudoVSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1)
  .value("PseudoVSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1_MASK)
  .value("PseudoVSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2)
  .value("PseudoVSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2_MASK)
  .value("PseudoVSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4)
  .value("PseudoVSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4_MASK)
  .value("PseudoVSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1)
  .value("PseudoVSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1_MASK)
  .value("PseudoVSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2)
  .value("PseudoVSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2_MASK)
  .value("PseudoVSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1)
  .value("PseudoVSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1_MASK)
  .value("PseudoVSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1)
  .value("PseudoVSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1_MASK)
  .value("PseudoVSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2)
  .value("PseudoVSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2_MASK)
  .value("PseudoVSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4)
  .value("PseudoVSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4_MASK)
  .value("PseudoVSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8)
  .value("PseudoVSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8_MASK)
  .value("PseudoVSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1)
  .value("PseudoVSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1_MASK)
  .value("PseudoVSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2)
  .value("PseudoVSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2_MASK)
  .value("PseudoVSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4)
  .value("PseudoVSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4_MASK)
  .value("PseudoVSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1)
  .value("PseudoVSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1_MASK)
  .value("PseudoVSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2)
  .value("PseudoVSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2_MASK)
  .value("PseudoVSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1)
  .value("PseudoVSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1_MASK)
  .value("PseudoVSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1)
  .value("PseudoVSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1_MASK)
  .value("PseudoVSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2)
  .value("PseudoVSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2_MASK)
  .value("PseudoVSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4)
  .value("PseudoVSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4_MASK)
  .value("PseudoVSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8)
  .value("PseudoVSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8_MASK)
  .value("PseudoVSSRA_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1)
  .value("PseudoVSSRA_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1_MASK)
  .value("PseudoVSSRA_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2)
  .value("PseudoVSSRA_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2_MASK)
  .value("PseudoVSSRA_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4)
  .value("PseudoVSSRA_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4_MASK)
  .value("PseudoVSSRA_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8)
  .value("PseudoVSSRA_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8_MASK)
  .value("PseudoVSSRA_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2)
  .value("PseudoVSSRA_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2_MASK)
  .value("PseudoVSSRA_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4)
  .value("PseudoVSSRA_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4_MASK)
  .value("PseudoVSSRA_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8)
  .value("PseudoVSSRA_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8_MASK)
  .value("PseudoVSSRA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1)
  .value("PseudoVSSRA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1_MASK)
  .value("PseudoVSSRA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2)
  .value("PseudoVSSRA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2_MASK)
  .value("PseudoVSSRA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4)
  .value("PseudoVSSRA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4_MASK)
  .value("PseudoVSSRA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8)
  .value("PseudoVSSRA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8_MASK)
  .value("PseudoVSSRA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2)
  .value("PseudoVSSRA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2_MASK)
  .value("PseudoVSSRA_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4)
  .value("PseudoVSSRA_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4_MASK)
  .value("PseudoVSSRA_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8)
  .value("PseudoVSSRA_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8_MASK)
  .value("PseudoVSSRA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1)
  .value("PseudoVSSRA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1_MASK)
  .value("PseudoVSSRA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2)
  .value("PseudoVSSRA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2_MASK)
  .value("PseudoVSSRA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4)
  .value("PseudoVSSRA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4_MASK)
  .value("PseudoVSSRA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8)
  .value("PseudoVSSRA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8_MASK)
  .value("PseudoVSSRA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2)
  .value("PseudoVSSRA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2_MASK)
  .value("PseudoVSSRA_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4)
  .value("PseudoVSSRA_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4_MASK)
  .value("PseudoVSSRA_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8)
  .value("PseudoVSSRA_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8_MASK)
  .value("PseudoVSSRL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1)
  .value("PseudoVSSRL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1_MASK)
  .value("PseudoVSSRL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2)
  .value("PseudoVSSRL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2_MASK)
  .value("PseudoVSSRL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4)
  .value("PseudoVSSRL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4_MASK)
  .value("PseudoVSSRL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8)
  .value("PseudoVSSRL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8_MASK)
  .value("PseudoVSSRL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2)
  .value("PseudoVSSRL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2_MASK)
  .value("PseudoVSSRL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4)
  .value("PseudoVSSRL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4_MASK)
  .value("PseudoVSSRL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8)
  .value("PseudoVSSRL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8_MASK)
  .value("PseudoVSSRL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1)
  .value("PseudoVSSRL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1_MASK)
  .value("PseudoVSSRL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2)
  .value("PseudoVSSRL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2_MASK)
  .value("PseudoVSSRL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4);
  opcodes.value("PseudoVSSRL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4_MASK)
  .value("PseudoVSSRL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8)
  .value("PseudoVSSRL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8_MASK)
  .value("PseudoVSSRL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2)
  .value("PseudoVSSRL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2_MASK)
  .value("PseudoVSSRL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4)
  .value("PseudoVSSRL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4_MASK)
  .value("PseudoVSSRL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8)
  .value("PseudoVSSRL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8_MASK)
  .value("PseudoVSSRL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1)
  .value("PseudoVSSRL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1_MASK)
  .value("PseudoVSSRL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2)
  .value("PseudoVSSRL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2_MASK)
  .value("PseudoVSSRL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4)
  .value("PseudoVSSRL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4_MASK)
  .value("PseudoVSSRL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8)
  .value("PseudoVSSRL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8_MASK)
  .value("PseudoVSSRL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2)
  .value("PseudoVSSRL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2_MASK)
  .value("PseudoVSSRL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4)
  .value("PseudoVSSRL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4_MASK)
  .value("PseudoVSSRL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8)
  .value("PseudoVSSRL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8_MASK)
  .value("PseudoVSSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1)
  .value("PseudoVSSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1_MASK)
  .value("PseudoVSSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2)
  .value("PseudoVSSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2_MASK)
  .value("PseudoVSSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4)
  .value("PseudoVSSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4_MASK)
  .value("PseudoVSSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2)
  .value("PseudoVSSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2_MASK)
  .value("PseudoVSSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4)
  .value("PseudoVSSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4_MASK)
  .value("PseudoVSSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1)
  .value("PseudoVSSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1_MASK)
  .value("PseudoVSSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2)
  .value("PseudoVSSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2_MASK)
  .value("PseudoVSSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4)
  .value("PseudoVSSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4_MASK)
  .value("PseudoVSSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2)
  .value("PseudoVSSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2_MASK)
  .value("PseudoVSSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1)
  .value("PseudoVSSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1_MASK)
  .value("PseudoVSSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2)
  .value("PseudoVSSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2_MASK)
  .value("PseudoVSSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4)
  .value("PseudoVSSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4_MASK)
  .value("PseudoVSSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1)
  .value("PseudoVSSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1_MASK)
  .value("PseudoVSSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2)
  .value("PseudoVSSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2_MASK)
  .value("PseudoVSSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4)
  .value("PseudoVSSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4_MASK)
  .value("PseudoVSSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2)
  .value("PseudoVSSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2_MASK)
  .value("PseudoVSSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4)
  .value("PseudoVSSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4_MASK)
  .value("PseudoVSSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8)
  .value("PseudoVSSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8_MASK)
  .value("PseudoVSSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1)
  .value("PseudoVSSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1_MASK)
  .value("PseudoVSSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2)
  .value("PseudoVSSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2_MASK)
  .value("PseudoVSSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2)
  .value("PseudoVSSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2_MASK)
  .value("PseudoVSSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4)
  .value("PseudoVSSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4_MASK)
  .value("PseudoVSSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1)
  .value("PseudoVSSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1_MASK)
  .value("PseudoVSSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2)
  .value("PseudoVSSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2_MASK)
  .value("PseudoVSSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2)
  .value("PseudoVSSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2_MASK)
  .value("PseudoVSSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1)
  .value("PseudoVSSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1_MASK)
  .value("PseudoVSSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2)
  .value("PseudoVSSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2_MASK)
  .value("PseudoVSSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1)
  .value("PseudoVSSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1_MASK)
  .value("PseudoVSSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2)
  .value("PseudoVSSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2_MASK)
  .value("PseudoVSSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2)
  .value("PseudoVSSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2_MASK)
  .value("PseudoVSSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4)
  .value("PseudoVSSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4_MASK)
  .value("PseudoVSSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8)
  .value("PseudoVSSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8_MASK)
  .value("PseudoVSSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1)
  .value("PseudoVSSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1_MASK)
  .value("PseudoVSSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2)
  .value("PseudoVSSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2_MASK)
  .value("PseudoVSSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2)
  .value("PseudoVSSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2_MASK)
  .value("PseudoVSSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4)
  .value("PseudoVSSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4_MASK)
  .value("PseudoVSSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1)
  .value("PseudoVSSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1_MASK)
  .value("PseudoVSSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2)
  .value("PseudoVSSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2_MASK)
  .value("PseudoVSSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2)
  .value("PseudoVSSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2_MASK)
  .value("PseudoVSSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1)
  .value("PseudoVSSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1_MASK)
  .value("PseudoVSSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2)
  .value("PseudoVSSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2_MASK)
  .value("PseudoVSSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1)
  .value("PseudoVSSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1_MASK)
  .value("PseudoVSSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2)
  .value("PseudoVSSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2_MASK)
  .value("PseudoVSSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2)
  .value("PseudoVSSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2_MASK)
  .value("PseudoVSSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4)
  .value("PseudoVSSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4_MASK)
  .value("PseudoVSSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8)
  .value("PseudoVSSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8_MASK)
  .value("PseudoVSSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1)
  .value("PseudoVSSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1_MASK)
  .value("PseudoVSSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2)
  .value("PseudoVSSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2_MASK)
  .value("PseudoVSSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4)
  .value("PseudoVSSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4_MASK)
  .value("PseudoVSSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1)
  .value("PseudoVSSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1_MASK)
  .value("PseudoVSSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2)
  .value("PseudoVSSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2_MASK)
  .value("PseudoVSSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1)
  .value("PseudoVSSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1_MASK)
  .value("PseudoVSSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1)
  .value("PseudoVSSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1_MASK)
  .value("PseudoVSSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2)
  .value("PseudoVSSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2_MASK)
  .value("PseudoVSSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4)
  .value("PseudoVSSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4_MASK)
  .value("PseudoVSSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8)
  .value("PseudoVSSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8_MASK)
  .value("PseudoVSSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1)
  .value("PseudoVSSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1_MASK)
  .value("PseudoVSSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2)
  .value("PseudoVSSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2_MASK)
  .value("PseudoVSSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4)
  .value("PseudoVSSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4_MASK)
  .value("PseudoVSSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1)
  .value("PseudoVSSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1_MASK)
  .value("PseudoVSSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2)
  .value("PseudoVSSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2_MASK)
  .value("PseudoVSSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1)
  .value("PseudoVSSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1_MASK)
  .value("PseudoVSSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1)
  .value("PseudoVSSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1_MASK)
  .value("PseudoVSSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2)
  .value("PseudoVSSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2_MASK)
  .value("PseudoVSSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4)
  .value("PseudoVSSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4_MASK)
  .value("PseudoVSSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8)
  .value("PseudoVSSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8_MASK)
  .value("PseudoVSSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1)
  .value("PseudoVSSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1_MASK)
  .value("PseudoVSSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2)
  .value("PseudoVSSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2_MASK)
  .value("PseudoVSSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4)
  .value("PseudoVSSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4_MASK)
  .value("PseudoVSSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1)
  .value("PseudoVSSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1_MASK)
  .value("PseudoVSSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2)
  .value("PseudoVSSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2_MASK)
  .value("PseudoVSSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1)
  .value("PseudoVSSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1_MASK)
  .value("PseudoVSSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1)
  .value("PseudoVSSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1_MASK)
  .value("PseudoVSSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2)
  .value("PseudoVSSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2_MASK)
  .value("PseudoVSSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4)
  .value("PseudoVSSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4_MASK)
  .value("PseudoVSSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8)
  .value("PseudoVSSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8_MASK)
  .value("PseudoVSSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1)
  .value("PseudoVSSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1_MASK)
  .value("PseudoVSSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2)
  .value("PseudoVSSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2_MASK)
  .value("PseudoVSSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4)
  .value("PseudoVSSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4_MASK)
  .value("PseudoVSSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1)
  .value("PseudoVSSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1_MASK)
  .value("PseudoVSSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2)
  .value("PseudoVSSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2_MASK)
  .value("PseudoVSSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1)
  .value("PseudoVSSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1_MASK)
  .value("PseudoVSSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1)
  .value("PseudoVSSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1_MASK)
  .value("PseudoVSSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2)
  .value("PseudoVSSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2_MASK)
  .value("PseudoVSSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4)
  .value("PseudoVSSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4_MASK)
  .value("PseudoVSSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8)
  .value("PseudoVSSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8_MASK)
  .value("PseudoVSSUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1)
  .value("PseudoVSSUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1_MASK)
  .value("PseudoVSSUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2)
  .value("PseudoVSSUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2_MASK)
  .value("PseudoVSSUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4)
  .value("PseudoVSSUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4_MASK)
  .value("PseudoVSSUBU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8)
  .value("PseudoVSSUBU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8_MASK)
  .value("PseudoVSSUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2)
  .value("PseudoVSSUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2_MASK)
  .value("PseudoVSSUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4)
  .value("PseudoVSSUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4_MASK)
  .value("PseudoVSSUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8)
  .value("PseudoVSSUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8_MASK)
  .value("PseudoVSSUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1)
  .value("PseudoVSSUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1_MASK)
  .value("PseudoVSSUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2)
  .value("PseudoVSSUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2_MASK)
  .value("PseudoVSSUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4)
  .value("PseudoVSSUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4_MASK)
  .value("PseudoVSSUBU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8)
  .value("PseudoVSSUBU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8_MASK)
  .value("PseudoVSSUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2)
  .value("PseudoVSSUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2_MASK)
  .value("PseudoVSSUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4)
  .value("PseudoVSSUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4_MASK)
  .value("PseudoVSSUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8)
  .value("PseudoVSSUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8_MASK)
  .value("PseudoVSSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1)
  .value("PseudoVSSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1_MASK)
  .value("PseudoVSSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2)
  .value("PseudoVSSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2_MASK)
  .value("PseudoVSSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4)
  .value("PseudoVSSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4_MASK)
  .value("PseudoVSSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8)
  .value("PseudoVSSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8_MASK)
  .value("PseudoVSSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2)
  .value("PseudoVSSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2_MASK)
  .value("PseudoVSSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4)
  .value("PseudoVSSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4_MASK)
  .value("PseudoVSSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8)
  .value("PseudoVSSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8_MASK)
  .value("PseudoVSSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1)
  .value("PseudoVSSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1_MASK)
  .value("PseudoVSSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2)
  .value("PseudoVSSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2_MASK)
  .value("PseudoVSSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4)
  .value("PseudoVSSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4_MASK)
  .value("PseudoVSSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8)
  .value("PseudoVSSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8_MASK)
  .value("PseudoVSSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2)
  .value("PseudoVSSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2_MASK)
  .value("PseudoVSSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4)
  .value("PseudoVSSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4_MASK)
  .value("PseudoVSSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8)
  .value("PseudoVSSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8_MASK)
  .value("PseudoVSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1)
  .value("PseudoVSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1_MASK)
  .value("PseudoVSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2)
  .value("PseudoVSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2_MASK)
  .value("PseudoVSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4)
  .value("PseudoVSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4_MASK)
  .value("PseudoVSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8)
  .value("PseudoVSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8_MASK)
  .value("PseudoVSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2)
  .value("PseudoVSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2_MASK)
  .value("PseudoVSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4)
  .value("PseudoVSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4_MASK)
  .value("PseudoVSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8)
  .value("PseudoVSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8_MASK)
  .value("PseudoVSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1)
  .value("PseudoVSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1_MASK)
  .value("PseudoVSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2)
  .value("PseudoVSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2_MASK)
  .value("PseudoVSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4)
  .value("PseudoVSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4_MASK)
  .value("PseudoVSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8)
  .value("PseudoVSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8_MASK)
  .value("PseudoVSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2)
  .value("PseudoVSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2_MASK)
  .value("PseudoVSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4)
  .value("PseudoVSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4_MASK)
  .value("PseudoVSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8)
  .value("PseudoVSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8_MASK)
  .value("PseudoVSUXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1)
  .value("PseudoVSUXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1_MASK)
  .value("PseudoVSUXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2)
  .value("PseudoVSUXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2_MASK)
  .value("PseudoVSUXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4)
  .value("PseudoVSUXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4_MASK)
  .value("PseudoVSUXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2)
  .value("PseudoVSUXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2_MASK)
  .value("PseudoVSUXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1)
  .value("PseudoVSUXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1_MASK)
  .value("PseudoVSUXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2)
  .value("PseudoVSUXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2_MASK)
  .value("PseudoVSUXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4)
  .value("PseudoVSUXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4_MASK)
  .value("PseudoVSUXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8)
  .value("PseudoVSUXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8_MASK)
  .value("PseudoVSUXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2)
  .value("PseudoVSUXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2_MASK)
  .value("PseudoVSUXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4)
  .value("PseudoVSUXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4_MASK)
  .value("PseudoVSUXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8);
  opcodes.value("PseudoVSUXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8_MASK)
  .value("PseudoVSUXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4)
  .value("PseudoVSUXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4_MASK)
  .value("PseudoVSUXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8)
  .value("PseudoVSUXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8_MASK)
  .value("PseudoVSUXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1)
  .value("PseudoVSUXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1_MASK)
  .value("PseudoVSUXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2)
  .value("PseudoVSUXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2_MASK)
  .value("PseudoVSUXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2)
  .value("PseudoVSUXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4)
  .value("PseudoVSUXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1)
  .value("PseudoVSUXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1_MASK)
  .value("PseudoVSUXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2)
  .value("PseudoVSUXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4)
  .value("PseudoVSUXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8)
  .value("PseudoVSUXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1)
  .value("PseudoVSUXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1_MASK)
  .value("PseudoVSUXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2)
  .value("PseudoVSUXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2_MASK)
  .value("PseudoVSUXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2)
  .value("PseudoVSUXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2_MASK)
  .value("PseudoVSUXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4)
  .value("PseudoVSUXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4_MASK)
  .value("PseudoVSUXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1)
  .value("PseudoVSUXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1_MASK)
  .value("PseudoVSUXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2)
  .value("PseudoVSUXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2_MASK)
  .value("PseudoVSUXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4)
  .value("PseudoVSUXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4_MASK)
  .value("PseudoVSUXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2)
  .value("PseudoVSUXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2_MASK)
  .value("PseudoVSUXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1)
  .value("PseudoVSUXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1_MASK)
  .value("PseudoVSUXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2)
  .value("PseudoVSUXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2_MASK)
  .value("PseudoVSUXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4)
  .value("PseudoVSUXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4_MASK)
  .value("PseudoVSUXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8)
  .value("PseudoVSUXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8_MASK)
  .value("PseudoVSUXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2)
  .value("PseudoVSUXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2_MASK)
  .value("PseudoVSUXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4)
  .value("PseudoVSUXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4_MASK)
  .value("PseudoVSUXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8)
  .value("PseudoVSUXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8_MASK)
  .value("PseudoVSUXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1)
  .value("PseudoVSUXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1_MASK)
  .value("PseudoVSUXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2)
  .value("PseudoVSUXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4)
  .value("PseudoVSUXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8)
  .value("PseudoVSUXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1)
  .value("PseudoVSUXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1_MASK)
  .value("PseudoVSUXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2)
  .value("PseudoVSUXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2_MASK)
  .value("PseudoVSUXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4)
  .value("PseudoVSUXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4_MASK)
  .value("PseudoVSUXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8)
  .value("PseudoVSUXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8_MASK)
  .value("PseudoVSUXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1)
  .value("PseudoVSUXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1_MASK)
  .value("PseudoVSUXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2)
  .value("PseudoVSUXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2_MASK)
  .value("PseudoVSUXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2)
  .value("PseudoVSUXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2_MASK)
  .value("PseudoVSUXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4)
  .value("PseudoVSUXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4_MASK)
  .value("PseudoVSUXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1)
  .value("PseudoVSUXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1_MASK)
  .value("PseudoVSUXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2)
  .value("PseudoVSUXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2_MASK)
  .value("PseudoVSUXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4)
  .value("PseudoVSUXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4_MASK)
  .value("PseudoVSUXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2)
  .value("PseudoVSUXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2_MASK)
  .value("PseudoVSUXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1)
  .value("PseudoVSUXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1_MASK)
  .value("PseudoVSUXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2)
  .value("PseudoVSUXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2_MASK)
  .value("PseudoVSUXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4)
  .value("PseudoVSUXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4_MASK)
  .value("PseudoVSUXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8)
  .value("PseudoVSUXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8_MASK)
  .value("PseudoVSUXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1)
  .value("PseudoVSUXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1_MASK)
  .value("PseudoVSUXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2)
  .value("PseudoVSUXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2_MASK)
  .value("PseudoVSUXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4)
  .value("PseudoVSUXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4_MASK)
  .value("PseudoVSUXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8)
  .value("PseudoVSUXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8_MASK)
  .value("PseudoVSUXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2)
  .value("PseudoVSUXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2_MASK)
  .value("PseudoVSUXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4)
  .value("PseudoVSUXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4_MASK)
  .value("PseudoVSUXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8)
  .value("PseudoVSUXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8_MASK)
  .value("PseudoVSUXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4)
  .value("PseudoVSUXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4_MASK)
  .value("PseudoVSUXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8)
  .value("PseudoVSUXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8_MASK)
  .value("PseudoVSUXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8)
  .value("PseudoVSUXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8_MASK)
  .value("PseudoVSUXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1)
  .value("PseudoVSUXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1_MASK)
  .value("PseudoVSUXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2)
  .value("PseudoVSUXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2_MASK)
  .value("PseudoVSUXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4)
  .value("PseudoVSUXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4_MASK)
  .value("PseudoVSUXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2)
  .value("PseudoVSUXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1)
  .value("PseudoVSUXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1_MASK)
  .value("PseudoVSUXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2)
  .value("PseudoVSUXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2_MASK)
  .value("PseudoVSUXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2)
  .value("PseudoVSUXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4)
  .value("PseudoVSUXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1)
  .value("PseudoVSUXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1_MASK)
  .value("PseudoVSUXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2)
  .value("PseudoVSUXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4)
  .value("PseudoVSUXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8)
  .value("PseudoVSUXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1)
  .value("PseudoVSUXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2)
  .value("PseudoVSUXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2_MASK)
  .value("PseudoVSUXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4)
  .value("PseudoVSUXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4_MASK)
  .value("PseudoVSUXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2)
  .value("PseudoVSUXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1)
  .value("PseudoVSUXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2)
  .value("PseudoVSUXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2_MASK)
  .value("PseudoVSUXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4)
  .value("PseudoVSUXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4_MASK)
  .value("PseudoVSUXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2)
  .value("PseudoVSUXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2_MASK)
  .value("PseudoVSUXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4)
  .value("PseudoVSUXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4_MASK)
  .value("PseudoVSUXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4)
  .value("PseudoVSUXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1)
  .value("PseudoVSUXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2)
  .value("PseudoVSUXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1)
  .value("PseudoVSUXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1)
  .value("PseudoVSUXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2)
  .value("PseudoVSUXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2)
  .value("PseudoVSUXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4)
  .value("PseudoVSUXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1)
  .value("PseudoVSUXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2)
  .value("PseudoVSUXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4)
  .value("PseudoVSUXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4_MASK)
  .value("PseudoVSUXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2)
  .value("PseudoVSUXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1)
  .value("PseudoVSUXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2)
  .value("PseudoVSUXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4)
  .value("PseudoVSUXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4_MASK)
  .value("PseudoVSUXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2)
  .value("PseudoVSUXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2_MASK)
  .value("PseudoVSUXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4)
  .value("PseudoVSUXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4_MASK)
  .value("PseudoVSUXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1)
  .value("PseudoVSUXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1)
  .value("PseudoVSUXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2)
  .value("PseudoVSUXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4)
  .value("PseudoVSUXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8)
  .value("PseudoVSUXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1)
  .value("PseudoVSUXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2)
  .value("PseudoVSUXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2)
  .value("PseudoVSUXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4)
  .value("PseudoVSUXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1)
  .value("PseudoVSUXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2)
  .value("PseudoVSUXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4)
  .value("PseudoVSUXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4_MASK)
  .value("PseudoVSUXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2)
  .value("PseudoVSUXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1)
  .value("PseudoVSUXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2)
  .value("PseudoVSUXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2_MASK)
  .value("PseudoVSUXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4)
  .value("PseudoVSUXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4_MASK)
  .value("PseudoVSUXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1)
  .value("PseudoVSUXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2)
  .value("PseudoVSUXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2_MASK)
  .value("PseudoVSUXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4)
  .value("PseudoVSUXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4_MASK)
  .value("PseudoVSUXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2)
  .value("PseudoVSUXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2_MASK)
  .value("PseudoVSUXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4)
  .value("PseudoVSUXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4_MASK)
  .value("PseudoVSUXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4)
  .value("PseudoVSUXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1)
  .value("PseudoVSUXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2)
  .value("PseudoVSUXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4)
  .value("PseudoVSUXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1)
  .value("PseudoVSUXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2)
  .value("PseudoVSUXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1)
  .value("PseudoVSUXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1)
  .value("PseudoVSUXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2)
  .value("PseudoVSUXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2_MASK)
  .value("PseudoVSUXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2)
  .value("PseudoVSUXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1)
  .value("PseudoVSUXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2)
  .value("PseudoVSUXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2_MASK)
  .value("PseudoVSUXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2)
  .value("PseudoVSUXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1)
  .value("PseudoVSUXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2)
  .value("PseudoVSUXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1)
  .value("PseudoVSUXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1);
  opcodes.value("PseudoVSUXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2)
  .value("PseudoVSUXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2_MASK)
  .value("PseudoVSUXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2)
  .value("PseudoVSUXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4)
  .value("PseudoVSUXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1)
  .value("PseudoVSUXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2)
  .value("PseudoVSUXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2_MASK)
  .value("PseudoVSUXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2)
  .value("PseudoVSUXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1)
  .value("PseudoVSUXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2)
  .value("PseudoVSUXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2_MASK)
  .value("PseudoVSUXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2)
  .value("PseudoVSUXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2_MASK)
  .value("PseudoVSUXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1)
  .value("PseudoVSUXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1)
  .value("PseudoVSUXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2)
  .value("PseudoVSUXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4)
  .value("PseudoVSUXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8)
  .value("PseudoVSUXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1)
  .value("PseudoVSUXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2)
  .value("PseudoVSUXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2_MASK)
  .value("PseudoVSUXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2)
  .value("PseudoVSUXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4)
  .value("PseudoVSUXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1)
  .value("PseudoVSUXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2)
  .value("PseudoVSUXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2_MASK)
  .value("PseudoVSUXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2)
  .value("PseudoVSUXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1)
  .value("PseudoVSUXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2)
  .value("PseudoVSUXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2_MASK)
  .value("PseudoVSUXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1)
  .value("PseudoVSUXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2)
  .value("PseudoVSUXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2_MASK)
  .value("PseudoVSUXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2)
  .value("PseudoVSUXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1)
  .value("PseudoVSUXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2)
  .value("PseudoVSUXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1)
  .value("PseudoVSUXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2)
  .value("PseudoVSUXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1)
  .value("PseudoVSUXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1)
  .value("PseudoVSUXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2)
  .value("PseudoVSUXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2_MASK)
  .value("PseudoVSUXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2)
  .value("PseudoVSUXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1)
  .value("PseudoVSUXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2)
  .value("PseudoVSUXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2_MASK)
  .value("PseudoVSUXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2)
  .value("PseudoVSUXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1)
  .value("PseudoVSUXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2)
  .value("PseudoVSUXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1)
  .value("PseudoVSUXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1)
  .value("PseudoVSUXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2)
  .value("PseudoVSUXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2_MASK)
  .value("PseudoVSUXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2)
  .value("PseudoVSUXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4)
  .value("PseudoVSUXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1)
  .value("PseudoVSUXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2)
  .value("PseudoVSUXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2_MASK)
  .value("PseudoVSUXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2)
  .value("PseudoVSUXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1)
  .value("PseudoVSUXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2)
  .value("PseudoVSUXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2_MASK)
  .value("PseudoVSUXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2)
  .value("PseudoVSUXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2_MASK)
  .value("PseudoVSUXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1)
  .value("PseudoVSUXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1)
  .value("PseudoVSUXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2)
  .value("PseudoVSUXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4)
  .value("PseudoVSUXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8)
  .value("PseudoVSUXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1)
  .value("PseudoVSUXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2)
  .value("PseudoVSUXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2_MASK)
  .value("PseudoVSUXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2)
  .value("PseudoVSUXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4)
  .value("PseudoVSUXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1)
  .value("PseudoVSUXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2)
  .value("PseudoVSUXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2_MASK)
  .value("PseudoVSUXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2)
  .value("PseudoVSUXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1)
  .value("PseudoVSUXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2)
  .value("PseudoVSUXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2_MASK)
  .value("PseudoVSUXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1)
  .value("PseudoVSUXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2)
  .value("PseudoVSUXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2_MASK)
  .value("PseudoVSUXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2)
  .value("PseudoVSUXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1)
  .value("PseudoVSUXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2)
  .value("PseudoVSUXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1)
  .value("PseudoVSUXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2)
  .value("PseudoVSUXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1)
  .value("PseudoVSUXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1)
  .value("PseudoVSUXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2)
  .value("PseudoVSUXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1)
  .value("PseudoVSUXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1)
  .value("PseudoVSUXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1)
  .value("PseudoVSUXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1)
  .value("PseudoVSUXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2)
  .value("PseudoVSUXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4)
  .value("PseudoVSUXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1)
  .value("PseudoVSUXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2)
  .value("PseudoVSUXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1)
  .value("PseudoVSUXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1)
  .value("PseudoVSUXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1)
  .value("PseudoVSUXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2)
  .value("PseudoVSUXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4)
  .value("PseudoVSUXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8)
  .value("PseudoVSUXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1)
  .value("PseudoVSUXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2)
  .value("PseudoVSUXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4)
  .value("PseudoVSUXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1)
  .value("PseudoVSUXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2)
  .value("PseudoVSUXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1)
  .value("PseudoVSUXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1)
  .value("PseudoVSUXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1)
  .value("PseudoVSUXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1)
  .value("PseudoVSUXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1)
  .value("PseudoVSUXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1)
  .value("PseudoVSUXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2)
  .value("PseudoVSUXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1)
  .value("PseudoVSUXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1)
  .value("PseudoVSUXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1)
  .value("PseudoVSUXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1)
  .value("PseudoVSUXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2)
  .value("PseudoVSUXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4)
  .value("PseudoVSUXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1)
  .value("PseudoVSUXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2);
  opcodes.value("PseudoVSUXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1)
  .value("PseudoVSUXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1)
  .value("PseudoVSUXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1)
  .value("PseudoVSUXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2)
  .value("PseudoVSUXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4)
  .value("PseudoVSUXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8)
  .value("PseudoVSUXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1)
  .value("PseudoVSUXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2)
  .value("PseudoVSUXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4)
  .value("PseudoVSUXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1)
  .value("PseudoVSUXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2)
  .value("PseudoVSUXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1)
  .value("PseudoVSUXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1)
  .value("PseudoVSUXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1)
  .value("PseudoVSUXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1)
  .value("PseudoVSUXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1)
  .value("PseudoVSUXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1)
  .value("PseudoVSUXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2)
  .value("PseudoVSUXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1)
  .value("PseudoVSUXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1)
  .value("PseudoVSUXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1)
  .value("PseudoVSUXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1)
  .value("PseudoVSUXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2)
  .value("PseudoVSUXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4)
  .value("PseudoVSUXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1)
  .value("PseudoVSUXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2)
  .value("PseudoVSUXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1)
  .value("PseudoVSUXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1)
  .value("PseudoVSUXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1)
  .value("PseudoVSUXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2)
  .value("PseudoVSUXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4)
  .value("PseudoVSUXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8)
  .value("PseudoVSUXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1)
  .value("PseudoVSUXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2)
  .value("PseudoVSUXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4)
  .value("PseudoVSUXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1)
  .value("PseudoVSUXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2)
  .value("PseudoVSUXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1)
  .value("PseudoVSUXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1)
  .value("PseudoVSUXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1)
  .value("PseudoVSUXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1)
  .value("PseudoVSUXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1)
  .value("PseudoVSUXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK)
  .value("PseudoVSUXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1)
  .value("PseudoVSUXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1_MASK)
  .value("PseudoVSUXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2)
  .value("PseudoVSUXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1)
  .value("PseudoVSUXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1)
  .value("PseudoVSUXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2)
  .value("PseudoVSUXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4)
  .value("PseudoVSUXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1)
  .value("PseudoVSUXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8)
  .value("PseudoVSUXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK)
  .value("PseudoVSUXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1)
  .value("PseudoVSUXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1_MASK)
  .value("PseudoVSUXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2)
  .value("PseudoVSUXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4)
  .value("PseudoVSUXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1)
  .value("PseudoVSUXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1_MASK)
  .value("PseudoVSUXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2)
  .value("PseudoVSUXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1)
  .value("PseudoVSUXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1_MASK)
  .value("PseudoVSUXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1)
  .value("PseudoVSUXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8)
  .value("PseudoVSUXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK)
  .value("PseudoVSUXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1)
  .value("PseudoVSUXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1_MASK)
  .value("PseudoVSUXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2)
  .value("PseudoVSUXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2_MASK)
  .value("PseudoVSUXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4)
  .value("PseudoVSUXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4_MASK)
  .value("PseudoVSUXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8)
  .value("PseudoVSUXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8_MASK)
  .value("PseudoVSUXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1)
  .value("PseudoVSUXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1_MASK)
  .value("PseudoVSUXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2)
  .value("PseudoVSUXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2_MASK)
  .value("PseudoVSUXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4)
  .value("PseudoVSUXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4_MASK)
  .value("PseudoVSUXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1)
  .value("PseudoVSUXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1_MASK)
  .value("PseudoVSUXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2)
  .value("PseudoVSUXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2_MASK)
  .value("PseudoVSUXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1)
  .value("PseudoVSUXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1_MASK)
  .value("PseudoVSUXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1)
  .value("PseudoVSUXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1)
  .value("PseudoVSUXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2)
  .value("PseudoVSUXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1)
  .value("PseudoVSUXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2)
  .value("PseudoVSUXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4)
  .value("PseudoVSUXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1)
  .value("PseudoVSUXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8)
  .value("PseudoVSUXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK)
  .value("PseudoVWADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1)
  .value("PseudoVWADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1_MASK)
  .value("PseudoVWADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2)
  .value("PseudoVWADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2_MASK)
  .value("PseudoVWADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4)
  .value("PseudoVWADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4_MASK)
  .value("PseudoVWADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2)
  .value("PseudoVWADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2_MASK)
  .value("PseudoVWADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4)
  .value("PseudoVWADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4_MASK)
  .value("PseudoVWADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8)
  .value("PseudoVWADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8_MASK)
  .value("PseudoVWADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1)
  .value("PseudoVWADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1_MASK)
  .value("PseudoVWADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2)
  .value("PseudoVWADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2_MASK)
  .value("PseudoVWADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4)
  .value("PseudoVWADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4_MASK)
  .value("PseudoVWADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2)
  .value("PseudoVWADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2_MASK)
  .value("PseudoVWADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4)
  .value("PseudoVWADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4_MASK)
  .value("PseudoVWADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8)
  .value("PseudoVWADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8_MASK)
  .value("PseudoVWADDU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1)
  .value("PseudoVWADDU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK)
  .value("PseudoVWADDU_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK_TIED)
  .value("PseudoVWADDU_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_TIED)
  .value("PseudoVWADDU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2)
  .value("PseudoVWADDU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK)
  .value("PseudoVWADDU_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK_TIED)
  .value("PseudoVWADDU_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_TIED)
  .value("PseudoVWADDU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4)
  .value("PseudoVWADDU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK)
  .value("PseudoVWADDU_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK_TIED)
  .value("PseudoVWADDU_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_TIED)
  .value("PseudoVWADDU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2)
  .value("PseudoVWADDU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK)
  .value("PseudoVWADDU_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK_TIED)
  .value("PseudoVWADDU_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_TIED)
  .value("PseudoVWADDU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4)
  .value("PseudoVWADDU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK)
  .value("PseudoVWADDU_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK_TIED)
  .value("PseudoVWADDU_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_TIED)
  .value("PseudoVWADDU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8)
  .value("PseudoVWADDU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK)
  .value("PseudoVWADDU_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK_TIED)
  .value("PseudoVWADDU_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_TIED)
  .value("PseudoVWADDU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1)
  .value("PseudoVWADDU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1_MASK)
  .value("PseudoVWADDU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2)
  .value("PseudoVWADDU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2_MASK)
  .value("PseudoVWADDU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4)
  .value("PseudoVWADDU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4_MASK)
  .value("PseudoVWADDU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2)
  .value("PseudoVWADDU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2_MASK)
  .value("PseudoVWADDU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4)
  .value("PseudoVWADDU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4_MASK)
  .value("PseudoVWADDU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8)
  .value("PseudoVWADDU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8_MASK)
  .value("PseudoVWADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1)
  .value("PseudoVWADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1_MASK)
  .value("PseudoVWADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2)
  .value("PseudoVWADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2_MASK)
  .value("PseudoVWADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4)
  .value("PseudoVWADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4_MASK)
  .value("PseudoVWADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2)
  .value("PseudoVWADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2_MASK)
  .value("PseudoVWADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4)
  .value("PseudoVWADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4_MASK)
  .value("PseudoVWADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8)
  .value("PseudoVWADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8_MASK)
  .value("PseudoVWADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1)
  .value("PseudoVWADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1_MASK)
  .value("PseudoVWADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2)
  .value("PseudoVWADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2_MASK)
  .value("PseudoVWADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4)
  .value("PseudoVWADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4_MASK)
  .value("PseudoVWADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2)
  .value("PseudoVWADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2_MASK)
  .value("PseudoVWADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4)
  .value("PseudoVWADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4_MASK)
  .value("PseudoVWADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8)
  .value("PseudoVWADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8_MASK)
  .value("PseudoVWADD_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1)
  .value("PseudoVWADD_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK)
  .value("PseudoVWADD_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK_TIED)
  .value("PseudoVWADD_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_TIED)
  .value("PseudoVWADD_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2);
  opcodes.value("PseudoVWADD_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK)
  .value("PseudoVWADD_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK_TIED)
  .value("PseudoVWADD_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_TIED)
  .value("PseudoVWADD_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4)
  .value("PseudoVWADD_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK)
  .value("PseudoVWADD_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK_TIED)
  .value("PseudoVWADD_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_TIED)
  .value("PseudoVWADD_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2)
  .value("PseudoVWADD_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK)
  .value("PseudoVWADD_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK_TIED)
  .value("PseudoVWADD_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_TIED)
  .value("PseudoVWADD_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4)
  .value("PseudoVWADD_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK)
  .value("PseudoVWADD_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK_TIED)
  .value("PseudoVWADD_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_TIED)
  .value("PseudoVWADD_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8)
  .value("PseudoVWADD_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK)
  .value("PseudoVWADD_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK_TIED)
  .value("PseudoVWADD_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_TIED)
  .value("PseudoVWADD_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1)
  .value("PseudoVWADD_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1_MASK)
  .value("PseudoVWADD_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2)
  .value("PseudoVWADD_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2_MASK)
  .value("PseudoVWADD_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4)
  .value("PseudoVWADD_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4_MASK)
  .value("PseudoVWADD_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2)
  .value("PseudoVWADD_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2_MASK)
  .value("PseudoVWADD_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4)
  .value("PseudoVWADD_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4_MASK)
  .value("PseudoVWADD_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8)
  .value("PseudoVWADD_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8_MASK)
  .value("PseudoVWMACCSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1)
  .value("PseudoVWMACCSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1_MASK)
  .value("PseudoVWMACCSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2)
  .value("PseudoVWMACCSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2_MASK)
  .value("PseudoVWMACCSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4)
  .value("PseudoVWMACCSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4_MASK)
  .value("PseudoVWMACCSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2)
  .value("PseudoVWMACCSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2_MASK)
  .value("PseudoVWMACCSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4)
  .value("PseudoVWMACCSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4_MASK)
  .value("PseudoVWMACCSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8)
  .value("PseudoVWMACCSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8_MASK)
  .value("PseudoVWMACCSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1)
  .value("PseudoVWMACCSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1_MASK)
  .value("PseudoVWMACCSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2)
  .value("PseudoVWMACCSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2_MASK)
  .value("PseudoVWMACCSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4)
  .value("PseudoVWMACCSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4_MASK)
  .value("PseudoVWMACCSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2)
  .value("PseudoVWMACCSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2_MASK)
  .value("PseudoVWMACCSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4)
  .value("PseudoVWMACCSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4_MASK)
  .value("PseudoVWMACCSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8)
  .value("PseudoVWMACCSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8_MASK)
  .value("PseudoVWMACCUS_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1)
  .value("PseudoVWMACCUS_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1_MASK)
  .value("PseudoVWMACCUS_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2)
  .value("PseudoVWMACCUS_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2_MASK)
  .value("PseudoVWMACCUS_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4)
  .value("PseudoVWMACCUS_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4_MASK)
  .value("PseudoVWMACCUS_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2)
  .value("PseudoVWMACCUS_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2_MASK)
  .value("PseudoVWMACCUS_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4)
  .value("PseudoVWMACCUS_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4_MASK)
  .value("PseudoVWMACCUS_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8)
  .value("PseudoVWMACCUS_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8_MASK)
  .value("PseudoVWMACCU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1)
  .value("PseudoVWMACCU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1_MASK)
  .value("PseudoVWMACCU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2)
  .value("PseudoVWMACCU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2_MASK)
  .value("PseudoVWMACCU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4)
  .value("PseudoVWMACCU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4_MASK)
  .value("PseudoVWMACCU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2)
  .value("PseudoVWMACCU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2_MASK)
  .value("PseudoVWMACCU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4)
  .value("PseudoVWMACCU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4_MASK)
  .value("PseudoVWMACCU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8)
  .value("PseudoVWMACCU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8_MASK)
  .value("PseudoVWMACCU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1)
  .value("PseudoVWMACCU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1_MASK)
  .value("PseudoVWMACCU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2)
  .value("PseudoVWMACCU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2_MASK)
  .value("PseudoVWMACCU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4)
  .value("PseudoVWMACCU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4_MASK)
  .value("PseudoVWMACCU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2)
  .value("PseudoVWMACCU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2_MASK)
  .value("PseudoVWMACCU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4)
  .value("PseudoVWMACCU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4_MASK)
  .value("PseudoVWMACCU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8)
  .value("PseudoVWMACCU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8_MASK)
  .value("PseudoVWMACC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1)
  .value("PseudoVWMACC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1_MASK)
  .value("PseudoVWMACC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2)
  .value("PseudoVWMACC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2_MASK)
  .value("PseudoVWMACC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4)
  .value("PseudoVWMACC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4_MASK)
  .value("PseudoVWMACC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2)
  .value("PseudoVWMACC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2_MASK)
  .value("PseudoVWMACC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4)
  .value("PseudoVWMACC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4_MASK)
  .value("PseudoVWMACC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8)
  .value("PseudoVWMACC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8_MASK)
  .value("PseudoVWMACC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1)
  .value("PseudoVWMACC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1_MASK)
  .value("PseudoVWMACC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2)
  .value("PseudoVWMACC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2_MASK)
  .value("PseudoVWMACC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4)
  .value("PseudoVWMACC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4_MASK)
  .value("PseudoVWMACC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2)
  .value("PseudoVWMACC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2_MASK)
  .value("PseudoVWMACC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4)
  .value("PseudoVWMACC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4_MASK)
  .value("PseudoVWMACC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8)
  .value("PseudoVWMACC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8_MASK)
  .value("PseudoVWMULSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1)
  .value("PseudoVWMULSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1_MASK)
  .value("PseudoVWMULSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2)
  .value("PseudoVWMULSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2_MASK)
  .value("PseudoVWMULSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4)
  .value("PseudoVWMULSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4_MASK)
  .value("PseudoVWMULSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2)
  .value("PseudoVWMULSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2_MASK)
  .value("PseudoVWMULSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4)
  .value("PseudoVWMULSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4_MASK)
  .value("PseudoVWMULSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8)
  .value("PseudoVWMULSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8_MASK)
  .value("PseudoVWMULSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1)
  .value("PseudoVWMULSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1_MASK)
  .value("PseudoVWMULSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2)
  .value("PseudoVWMULSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2_MASK)
  .value("PseudoVWMULSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4)
  .value("PseudoVWMULSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4_MASK)
  .value("PseudoVWMULSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2)
  .value("PseudoVWMULSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2_MASK)
  .value("PseudoVWMULSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4)
  .value("PseudoVWMULSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4_MASK)
  .value("PseudoVWMULSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8)
  .value("PseudoVWMULSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8_MASK)
  .value("PseudoVWMULU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1)
  .value("PseudoVWMULU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1_MASK)
  .value("PseudoVWMULU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2)
  .value("PseudoVWMULU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2_MASK)
  .value("PseudoVWMULU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4)
  .value("PseudoVWMULU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4_MASK)
  .value("PseudoVWMULU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2)
  .value("PseudoVWMULU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2_MASK)
  .value("PseudoVWMULU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4)
  .value("PseudoVWMULU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4_MASK)
  .value("PseudoVWMULU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8)
  .value("PseudoVWMULU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8_MASK)
  .value("PseudoVWMULU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1)
  .value("PseudoVWMULU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1_MASK)
  .value("PseudoVWMULU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2)
  .value("PseudoVWMULU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2_MASK)
  .value("PseudoVWMULU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4)
  .value("PseudoVWMULU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4_MASK)
  .value("PseudoVWMULU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2)
  .value("PseudoVWMULU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2_MASK)
  .value("PseudoVWMULU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4)
  .value("PseudoVWMULU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4_MASK)
  .value("PseudoVWMULU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8)
  .value("PseudoVWMULU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8_MASK)
  .value("PseudoVWMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1)
  .value("PseudoVWMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1_MASK)
  .value("PseudoVWMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2)
  .value("PseudoVWMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2_MASK)
  .value("PseudoVWMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4)
  .value("PseudoVWMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4_MASK)
  .value("PseudoVWMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2)
  .value("PseudoVWMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2_MASK)
  .value("PseudoVWMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4)
  .value("PseudoVWMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4_MASK)
  .value("PseudoVWMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8)
  .value("PseudoVWMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8_MASK)
  .value("PseudoVWMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1)
  .value("PseudoVWMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1_MASK)
  .value("PseudoVWMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2)
  .value("PseudoVWMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2_MASK)
  .value("PseudoVWMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4)
  .value("PseudoVWMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4_MASK)
  .value("PseudoVWMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2)
  .value("PseudoVWMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2_MASK)
  .value("PseudoVWMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4)
  .value("PseudoVWMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4_MASK)
  .value("PseudoVWMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8)
  .value("PseudoVWMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8_MASK)
  .value("PseudoVWREDSUMU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16)
  .value("PseudoVWREDSUMU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16_MASK)
  .value("PseudoVWREDSUMU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32)
  .value("PseudoVWREDSUMU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32_MASK)
  .value("PseudoVWREDSUMU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8)
  .value("PseudoVWREDSUMU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8_MASK)
  .value("PseudoVWREDSUMU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16)
  .value("PseudoVWREDSUMU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16_MASK)
  .value("PseudoVWREDSUMU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32)
  .value("PseudoVWREDSUMU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32_MASK)
  .value("PseudoVWREDSUMU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8)
  .value("PseudoVWREDSUMU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8_MASK)
  .value("PseudoVWREDSUMU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16)
  .value("PseudoVWREDSUMU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16_MASK)
  .value("PseudoVWREDSUMU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32)
  .value("PseudoVWREDSUMU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32_MASK)
  .value("PseudoVWREDSUMU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8)
  .value("PseudoVWREDSUMU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8_MASK)
  .value("PseudoVWREDSUMU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16)
  .value("PseudoVWREDSUMU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16_MASK)
  .value("PseudoVWREDSUMU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32)
  .value("PseudoVWREDSUMU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32_MASK)
  .value("PseudoVWREDSUMU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8)
  .value("PseudoVWREDSUMU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8_MASK)
  .value("PseudoVWREDSUMU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16)
  .value("PseudoVWREDSUMU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16_MASK)
  .value("PseudoVWREDSUMU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32)
  .value("PseudoVWREDSUMU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32_MASK)
  .value("PseudoVWREDSUMU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8)
  .value("PseudoVWREDSUMU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8_MASK)
  .value("PseudoVWREDSUMU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16)
  .value("PseudoVWREDSUMU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16_MASK)
  .value("PseudoVWREDSUMU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8)
  .value("PseudoVWREDSUMU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8_MASK)
  .value("PseudoVWREDSUMU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8)
  .value("PseudoVWREDSUMU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8_MASK)
  .value("PseudoVWREDSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16)
  .value("PseudoVWREDSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16_MASK)
  .value("PseudoVWREDSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32)
  .value("PseudoVWREDSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32_MASK)
  .value("PseudoVWREDSUM_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8)
  .value("PseudoVWREDSUM_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8_MASK)
  .value("PseudoVWREDSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16)
  .value("PseudoVWREDSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16_MASK)
  .value("PseudoVWREDSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32)
  .value("PseudoVWREDSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32_MASK)
  .value("PseudoVWREDSUM_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8)
  .value("PseudoVWREDSUM_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8_MASK)
  .value("PseudoVWREDSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16)
  .value("PseudoVWREDSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16_MASK)
  .value("PseudoVWREDSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32)
  .value("PseudoVWREDSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32_MASK)
  .value("PseudoVWREDSUM_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8)
  .value("PseudoVWREDSUM_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8_MASK)
  .value("PseudoVWREDSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16)
  .value("PseudoVWREDSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16_MASK)
  .value("PseudoVWREDSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32)
  .value("PseudoVWREDSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32_MASK)
  .value("PseudoVWREDSUM_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8)
  .value("PseudoVWREDSUM_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8_MASK)
  .value("PseudoVWREDSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16)
  .value("PseudoVWREDSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16_MASK)
  .value("PseudoVWREDSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32)
  .value("PseudoVWREDSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32_MASK)
  .value("PseudoVWREDSUM_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8)
  .value("PseudoVWREDSUM_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8_MASK)
  .value("PseudoVWREDSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16)
  .value("PseudoVWREDSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16_MASK)
  .value("PseudoVWREDSUM_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8)
  .value("PseudoVWREDSUM_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8_MASK)
  .value("PseudoVWREDSUM_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8)
  .value("PseudoVWREDSUM_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8_MASK)
  .value("PseudoVWSLL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1)
  .value("PseudoVWSLL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1_MASK)
  .value("PseudoVWSLL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2)
  .value("PseudoVWSLL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2_MASK)
  .value("PseudoVWSLL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4)
  .value("PseudoVWSLL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4_MASK)
  .value("PseudoVWSLL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2)
  .value("PseudoVWSLL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2_MASK)
  .value("PseudoVWSLL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4)
  .value("PseudoVWSLL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4_MASK)
  .value("PseudoVWSLL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8)
  .value("PseudoVWSLL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8_MASK)
  .value("PseudoVWSLL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1)
  .value("PseudoVWSLL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1_MASK)
  .value("PseudoVWSLL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2)
  .value("PseudoVWSLL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2_MASK)
  .value("PseudoVWSLL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4)
  .value("PseudoVWSLL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4_MASK)
  .value("PseudoVWSLL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2)
  .value("PseudoVWSLL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2_MASK)
  .value("PseudoVWSLL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4)
  .value("PseudoVWSLL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4_MASK)
  .value("PseudoVWSLL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8)
  .value("PseudoVWSLL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8_MASK)
  .value("PseudoVWSLL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1)
  .value("PseudoVWSLL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1_MASK)
  .value("PseudoVWSLL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2)
  .value("PseudoVWSLL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2_MASK)
  .value("PseudoVWSLL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4)
  .value("PseudoVWSLL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4_MASK)
  .value("PseudoVWSLL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2)
  .value("PseudoVWSLL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2_MASK)
  .value("PseudoVWSLL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4)
  .value("PseudoVWSLL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4_MASK)
  .value("PseudoVWSLL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8)
  .value("PseudoVWSLL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8_MASK)
  .value("PseudoVWSUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1)
  .value("PseudoVWSUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1_MASK)
  .value("PseudoVWSUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2)
  .value("PseudoVWSUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2_MASK)
  .value("PseudoVWSUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4);
  opcodes.value("PseudoVWSUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4_MASK)
  .value("PseudoVWSUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2)
  .value("PseudoVWSUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2_MASK)
  .value("PseudoVWSUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4)
  .value("PseudoVWSUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4_MASK)
  .value("PseudoVWSUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8)
  .value("PseudoVWSUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8_MASK)
  .value("PseudoVWSUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1)
  .value("PseudoVWSUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1_MASK)
  .value("PseudoVWSUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2)
  .value("PseudoVWSUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2_MASK)
  .value("PseudoVWSUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4)
  .value("PseudoVWSUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4_MASK)
  .value("PseudoVWSUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2)
  .value("PseudoVWSUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2_MASK)
  .value("PseudoVWSUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4)
  .value("PseudoVWSUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4_MASK)
  .value("PseudoVWSUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8)
  .value("PseudoVWSUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8_MASK)
  .value("PseudoVWSUBU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1)
  .value("PseudoVWSUBU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK)
  .value("PseudoVWSUBU_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK_TIED)
  .value("PseudoVWSUBU_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_TIED)
  .value("PseudoVWSUBU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2)
  .value("PseudoVWSUBU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK)
  .value("PseudoVWSUBU_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK_TIED)
  .value("PseudoVWSUBU_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_TIED)
  .value("PseudoVWSUBU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4)
  .value("PseudoVWSUBU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK)
  .value("PseudoVWSUBU_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK_TIED)
  .value("PseudoVWSUBU_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_TIED)
  .value("PseudoVWSUBU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2)
  .value("PseudoVWSUBU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK)
  .value("PseudoVWSUBU_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK_TIED)
  .value("PseudoVWSUBU_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_TIED)
  .value("PseudoVWSUBU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4)
  .value("PseudoVWSUBU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK)
  .value("PseudoVWSUBU_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK_TIED)
  .value("PseudoVWSUBU_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_TIED)
  .value("PseudoVWSUBU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8)
  .value("PseudoVWSUBU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK)
  .value("PseudoVWSUBU_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK_TIED)
  .value("PseudoVWSUBU_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_TIED)
  .value("PseudoVWSUBU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1)
  .value("PseudoVWSUBU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1_MASK)
  .value("PseudoVWSUBU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2)
  .value("PseudoVWSUBU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2_MASK)
  .value("PseudoVWSUBU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4)
  .value("PseudoVWSUBU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4_MASK)
  .value("PseudoVWSUBU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2)
  .value("PseudoVWSUBU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2_MASK)
  .value("PseudoVWSUBU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4)
  .value("PseudoVWSUBU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4_MASK)
  .value("PseudoVWSUBU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8)
  .value("PseudoVWSUBU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8_MASK)
  .value("PseudoVWSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1)
  .value("PseudoVWSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1_MASK)
  .value("PseudoVWSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2)
  .value("PseudoVWSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2_MASK)
  .value("PseudoVWSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4)
  .value("PseudoVWSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4_MASK)
  .value("PseudoVWSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2)
  .value("PseudoVWSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2_MASK)
  .value("PseudoVWSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4)
  .value("PseudoVWSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4_MASK)
  .value("PseudoVWSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8)
  .value("PseudoVWSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8_MASK)
  .value("PseudoVWSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1)
  .value("PseudoVWSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1_MASK)
  .value("PseudoVWSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2)
  .value("PseudoVWSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2_MASK)
  .value("PseudoVWSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4)
  .value("PseudoVWSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4_MASK)
  .value("PseudoVWSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2)
  .value("PseudoVWSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2_MASK)
  .value("PseudoVWSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4)
  .value("PseudoVWSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4_MASK)
  .value("PseudoVWSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8)
  .value("PseudoVWSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8_MASK)
  .value("PseudoVWSUB_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1)
  .value("PseudoVWSUB_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK)
  .value("PseudoVWSUB_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK_TIED)
  .value("PseudoVWSUB_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_TIED)
  .value("PseudoVWSUB_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2)
  .value("PseudoVWSUB_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK)
  .value("PseudoVWSUB_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK_TIED)
  .value("PseudoVWSUB_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_TIED)
  .value("PseudoVWSUB_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4)
  .value("PseudoVWSUB_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK)
  .value("PseudoVWSUB_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK_TIED)
  .value("PseudoVWSUB_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_TIED)
  .value("PseudoVWSUB_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2)
  .value("PseudoVWSUB_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK)
  .value("PseudoVWSUB_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK_TIED)
  .value("PseudoVWSUB_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_TIED)
  .value("PseudoVWSUB_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4)
  .value("PseudoVWSUB_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK)
  .value("PseudoVWSUB_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK_TIED)
  .value("PseudoVWSUB_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_TIED)
  .value("PseudoVWSUB_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8)
  .value("PseudoVWSUB_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK)
  .value("PseudoVWSUB_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK_TIED)
  .value("PseudoVWSUB_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_TIED)
  .value("PseudoVWSUB_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1)
  .value("PseudoVWSUB_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1_MASK)
  .value("PseudoVWSUB_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2)
  .value("PseudoVWSUB_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2_MASK)
  .value("PseudoVWSUB_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4)
  .value("PseudoVWSUB_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4_MASK)
  .value("PseudoVWSUB_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2)
  .value("PseudoVWSUB_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2_MASK)
  .value("PseudoVWSUB_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4)
  .value("PseudoVWSUB_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4_MASK)
  .value("PseudoVWSUB_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8)
  .value("PseudoVWSUB_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8_MASK)
  .value("PseudoVXOR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1)
  .value("PseudoVXOR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1_MASK)
  .value("PseudoVXOR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2)
  .value("PseudoVXOR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2_MASK)
  .value("PseudoVXOR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4)
  .value("PseudoVXOR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4_MASK)
  .value("PseudoVXOR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8)
  .value("PseudoVXOR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8_MASK)
  .value("PseudoVXOR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2)
  .value("PseudoVXOR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2_MASK)
  .value("PseudoVXOR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4)
  .value("PseudoVXOR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4_MASK)
  .value("PseudoVXOR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8)
  .value("PseudoVXOR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8_MASK)
  .value("PseudoVXOR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1)
  .value("PseudoVXOR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1_MASK)
  .value("PseudoVXOR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2)
  .value("PseudoVXOR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2_MASK)
  .value("PseudoVXOR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4)
  .value("PseudoVXOR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4_MASK)
  .value("PseudoVXOR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8)
  .value("PseudoVXOR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8_MASK)
  .value("PseudoVXOR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2)
  .value("PseudoVXOR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2_MASK)
  .value("PseudoVXOR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4)
  .value("PseudoVXOR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4_MASK)
  .value("PseudoVXOR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8)
  .value("PseudoVXOR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8_MASK)
  .value("PseudoVXOR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1)
  .value("PseudoVXOR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1_MASK)
  .value("PseudoVXOR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2)
  .value("PseudoVXOR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2_MASK)
  .value("PseudoVXOR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4)
  .value("PseudoVXOR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4_MASK)
  .value("PseudoVXOR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8)
  .value("PseudoVXOR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8_MASK)
  .value("PseudoVXOR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2)
  .value("PseudoVXOR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2_MASK)
  .value("PseudoVXOR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4)
  .value("PseudoVXOR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4_MASK)
  .value("PseudoVXOR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8)
  .value("PseudoVXOR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8_MASK)
  .value("PseudoVZEXT_VF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1)
  .value("PseudoVZEXT_VF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1_MASK)
  .value("PseudoVZEXT_VF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2)
  .value("PseudoVZEXT_VF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2_MASK)
  .value("PseudoVZEXT_VF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4)
  .value("PseudoVZEXT_VF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4_MASK)
  .value("PseudoVZEXT_VF2_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8)
  .value("PseudoVZEXT_VF2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8_MASK)
  .value("PseudoVZEXT_VF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2)
  .value("PseudoVZEXT_VF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2_MASK)
  .value("PseudoVZEXT_VF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4)
  .value("PseudoVZEXT_VF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4_MASK)
  .value("PseudoVZEXT_VF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1)
  .value("PseudoVZEXT_VF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1_MASK)
  .value("PseudoVZEXT_VF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2)
  .value("PseudoVZEXT_VF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2_MASK)
  .value("PseudoVZEXT_VF4_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4)
  .value("PseudoVZEXT_VF4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4_MASK)
  .value("PseudoVZEXT_VF4_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8)
  .value("PseudoVZEXT_VF4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8_MASK)
  .value("PseudoVZEXT_VF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2)
  .value("PseudoVZEXT_VF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2_MASK)
  .value("PseudoVZEXT_VF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1)
  .value("PseudoVZEXT_VF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1_MASK)
  .value("PseudoVZEXT_VF8_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2)
  .value("PseudoVZEXT_VF8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2_MASK)
  .value("PseudoVZEXT_VF8_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4)
  .value("PseudoVZEXT_VF8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4_MASK)
  .value("PseudoVZEXT_VF8_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8)
  .value("PseudoVZEXT_VF8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8_MASK)
  .value("PseudoZEXT_H", LIEF::assembly::riscv::OPCODE::PseudoZEXT_H)
  .value("PseudoZEXT_W", LIEF::assembly::riscv::OPCODE::PseudoZEXT_W)
  .value("ReadCounterWide", LIEF::assembly::riscv::OPCODE::ReadCounterWide)
  .value("ReadFFLAGS", LIEF::assembly::riscv::OPCODE::ReadFFLAGS)
  .value("ReadFRM", LIEF::assembly::riscv::OPCODE::ReadFRM)
  .value("Select_FPR16INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR16INX_Using_CC_GPR)
  .value("Select_FPR16_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR16_Using_CC_GPR)
  .value("Select_FPR32INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR32INX_Using_CC_GPR)
  .value("Select_FPR32_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR32_Using_CC_GPR)
  .value("Select_FPR64IN32X_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64IN32X_Using_CC_GPR)
  .value("Select_FPR64INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64INX_Using_CC_GPR)
  .value("Select_FPR64_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64_Using_CC_GPR)
  .value("Select_GPR_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_GPR)
  .value("Select_GPR_Using_CC_Imm", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_Imm)
  .value("SplitF64Pseudo", LIEF::assembly::riscv::OPCODE::SplitF64Pseudo)
  .value("SwapFRMImm", LIEF::assembly::riscv::OPCODE::SwapFRMImm)
  .value("WriteFFLAGS", LIEF::assembly::riscv::OPCODE::WriteFFLAGS)
  .value("WriteFRM", LIEF::assembly::riscv::OPCODE::WriteFRM)
  .value("WriteFRMImm", LIEF::assembly::riscv::OPCODE::WriteFRMImm)
  .value("WriteVXRMImm", LIEF::assembly::riscv::OPCODE::WriteVXRMImm)
  .value("ADD", LIEF::assembly::riscv::OPCODE::ADD)
  .value("ADDI", LIEF::assembly::riscv::OPCODE::ADDI)
  .value("ADDIW", LIEF::assembly::riscv::OPCODE::ADDIW)
  .value("ADDW", LIEF::assembly::riscv::OPCODE::ADDW)
  .value("ADD_UW", LIEF::assembly::riscv::OPCODE::ADD_UW)
  .value("AES32DSI", LIEF::assembly::riscv::OPCODE::AES32DSI)
  .value("AES32DSMI", LIEF::assembly::riscv::OPCODE::AES32DSMI)
  .value("AES32ESI", LIEF::assembly::riscv::OPCODE::AES32ESI)
  .value("AES32ESMI", LIEF::assembly::riscv::OPCODE::AES32ESMI)
  .value("AES64DS", LIEF::assembly::riscv::OPCODE::AES64DS)
  .value("AES64DSM", LIEF::assembly::riscv::OPCODE::AES64DSM)
  .value("AES64ES", LIEF::assembly::riscv::OPCODE::AES64ES)
  .value("AES64ESM", LIEF::assembly::riscv::OPCODE::AES64ESM)
  .value("AES64IM", LIEF::assembly::riscv::OPCODE::AES64IM)
  .value("AES64KS1I", LIEF::assembly::riscv::OPCODE::AES64KS1I)
  .value("AES64KS2", LIEF::assembly::riscv::OPCODE::AES64KS2)
  .value("AMOADD_B", LIEF::assembly::riscv::OPCODE::AMOADD_B)
  .value("AMOADD_B_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_B_AQ)
  .value("AMOADD_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOADD_B_AQ_RL)
  .value("AMOADD_B_RL", LIEF::assembly::riscv::OPCODE::AMOADD_B_RL)
  .value("AMOADD_D", LIEF::assembly::riscv::OPCODE::AMOADD_D)
  .value("AMOADD_D_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_D_AQ)
  .value("AMOADD_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOADD_D_AQ_RL)
  .value("AMOADD_D_RL", LIEF::assembly::riscv::OPCODE::AMOADD_D_RL)
  .value("AMOADD_H", LIEF::assembly::riscv::OPCODE::AMOADD_H)
  .value("AMOADD_H_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_H_AQ)
  .value("AMOADD_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOADD_H_AQ_RL)
  .value("AMOADD_H_RL", LIEF::assembly::riscv::OPCODE::AMOADD_H_RL)
  .value("AMOADD_W", LIEF::assembly::riscv::OPCODE::AMOADD_W)
  .value("AMOADD_W_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_W_AQ)
  .value("AMOADD_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOADD_W_AQ_RL)
  .value("AMOADD_W_RL", LIEF::assembly::riscv::OPCODE::AMOADD_W_RL)
  .value("AMOAND_B", LIEF::assembly::riscv::OPCODE::AMOAND_B)
  .value("AMOAND_B_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_B_AQ)
  .value("AMOAND_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOAND_B_AQ_RL)
  .value("AMOAND_B_RL", LIEF::assembly::riscv::OPCODE::AMOAND_B_RL)
  .value("AMOAND_D", LIEF::assembly::riscv::OPCODE::AMOAND_D)
  .value("AMOAND_D_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_D_AQ)
  .value("AMOAND_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOAND_D_AQ_RL)
  .value("AMOAND_D_RL", LIEF::assembly::riscv::OPCODE::AMOAND_D_RL)
  .value("AMOAND_H", LIEF::assembly::riscv::OPCODE::AMOAND_H)
  .value("AMOAND_H_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_H_AQ)
  .value("AMOAND_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOAND_H_AQ_RL)
  .value("AMOAND_H_RL", LIEF::assembly::riscv::OPCODE::AMOAND_H_RL)
  .value("AMOAND_W", LIEF::assembly::riscv::OPCODE::AMOAND_W)
  .value("AMOAND_W_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_W_AQ)
  .value("AMOAND_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOAND_W_AQ_RL)
  .value("AMOAND_W_RL", LIEF::assembly::riscv::OPCODE::AMOAND_W_RL)
  .value("AMOCAS_B", LIEF::assembly::riscv::OPCODE::AMOCAS_B)
  .value("AMOCAS_B_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQ)
  .value("AMOCAS_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQ_RL)
  .value("AMOCAS_B_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_B_RL)
  .value("AMOCAS_D_RV32", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32)
  .value("AMOCAS_D_RV32_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQ)
  .value("AMOCAS_D_RV32_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQ_RL)
  .value("AMOCAS_D_RV32_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_RL)
  .value("AMOCAS_D_RV64", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64)
  .value("AMOCAS_D_RV64_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQ)
  .value("AMOCAS_D_RV64_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQ_RL)
  .value("AMOCAS_D_RV64_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_RL)
  .value("AMOCAS_H", LIEF::assembly::riscv::OPCODE::AMOCAS_H)
  .value("AMOCAS_H_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQ)
  .value("AMOCAS_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQ_RL)
  .value("AMOCAS_H_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_H_RL)
  .value("AMOCAS_Q", LIEF::assembly::riscv::OPCODE::AMOCAS_Q)
  .value("AMOCAS_Q_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQ)
  .value("AMOCAS_Q_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQ_RL)
  .value("AMOCAS_Q_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_RL)
  .value("AMOCAS_W", LIEF::assembly::riscv::OPCODE::AMOCAS_W)
  .value("AMOCAS_W_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQ)
  .value("AMOCAS_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQ_RL)
  .value("AMOCAS_W_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_W_RL)
  .value("AMOMAXU_B", LIEF::assembly::riscv::OPCODE::AMOMAXU_B)
  .value("AMOMAXU_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQ)
  .value("AMOMAXU_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQ_RL)
  .value("AMOMAXU_B_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_RL)
  .value("AMOMAXU_D", LIEF::assembly::riscv::OPCODE::AMOMAXU_D)
  .value("AMOMAXU_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQ)
  .value("AMOMAXU_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQ_RL)
  .value("AMOMAXU_D_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_RL)
  .value("AMOMAXU_H", LIEF::assembly::riscv::OPCODE::AMOMAXU_H)
  .value("AMOMAXU_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQ)
  .value("AMOMAXU_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQ_RL)
  .value("AMOMAXU_H_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_RL)
  .value("AMOMAXU_W", LIEF::assembly::riscv::OPCODE::AMOMAXU_W)
  .value("AMOMAXU_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQ)
  .value("AMOMAXU_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQ_RL)
  .value("AMOMAXU_W_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_RL)
  .value("AMOMAX_B", LIEF::assembly::riscv::OPCODE::AMOMAX_B)
  .value("AMOMAX_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQ)
  .value("AMOMAX_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQ_RL)
  .value("AMOMAX_B_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_B_RL)
  .value("AMOMAX_D", LIEF::assembly::riscv::OPCODE::AMOMAX_D);
  opcodes.value("AMOMAX_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQ)
  .value("AMOMAX_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQ_RL)
  .value("AMOMAX_D_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_D_RL)
  .value("AMOMAX_H", LIEF::assembly::riscv::OPCODE::AMOMAX_H)
  .value("AMOMAX_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQ)
  .value("AMOMAX_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQ_RL)
  .value("AMOMAX_H_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_H_RL)
  .value("AMOMAX_W", LIEF::assembly::riscv::OPCODE::AMOMAX_W)
  .value("AMOMAX_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQ)
  .value("AMOMAX_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQ_RL)
  .value("AMOMAX_W_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_W_RL)
  .value("AMOMINU_B", LIEF::assembly::riscv::OPCODE::AMOMINU_B)
  .value("AMOMINU_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQ)
  .value("AMOMINU_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQ_RL)
  .value("AMOMINU_B_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_B_RL)
  .value("AMOMINU_D", LIEF::assembly::riscv::OPCODE::AMOMINU_D)
  .value("AMOMINU_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQ)
  .value("AMOMINU_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQ_RL)
  .value("AMOMINU_D_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_D_RL)
  .value("AMOMINU_H", LIEF::assembly::riscv::OPCODE::AMOMINU_H)
  .value("AMOMINU_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQ)
  .value("AMOMINU_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQ_RL)
  .value("AMOMINU_H_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_H_RL)
  .value("AMOMINU_W", LIEF::assembly::riscv::OPCODE::AMOMINU_W)
  .value("AMOMINU_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQ)
  .value("AMOMINU_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQ_RL)
  .value("AMOMINU_W_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_W_RL)
  .value("AMOMIN_B", LIEF::assembly::riscv::OPCODE::AMOMIN_B)
  .value("AMOMIN_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQ)
  .value("AMOMIN_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQ_RL)
  .value("AMOMIN_B_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_B_RL)
  .value("AMOMIN_D", LIEF::assembly::riscv::OPCODE::AMOMIN_D)
  .value("AMOMIN_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQ)
  .value("AMOMIN_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQ_RL)
  .value("AMOMIN_D_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_D_RL)
  .value("AMOMIN_H", LIEF::assembly::riscv::OPCODE::AMOMIN_H)
  .value("AMOMIN_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQ)
  .value("AMOMIN_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQ_RL)
  .value("AMOMIN_H_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_H_RL)
  .value("AMOMIN_W", LIEF::assembly::riscv::OPCODE::AMOMIN_W)
  .value("AMOMIN_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQ)
  .value("AMOMIN_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQ_RL)
  .value("AMOMIN_W_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_W_RL)
  .value("AMOOR_B", LIEF::assembly::riscv::OPCODE::AMOOR_B)
  .value("AMOOR_B_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_B_AQ)
  .value("AMOOR_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOOR_B_AQ_RL)
  .value("AMOOR_B_RL", LIEF::assembly::riscv::OPCODE::AMOOR_B_RL)
  .value("AMOOR_D", LIEF::assembly::riscv::OPCODE::AMOOR_D)
  .value("AMOOR_D_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_D_AQ)
  .value("AMOOR_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOOR_D_AQ_RL)
  .value("AMOOR_D_RL", LIEF::assembly::riscv::OPCODE::AMOOR_D_RL)
  .value("AMOOR_H", LIEF::assembly::riscv::OPCODE::AMOOR_H)
  .value("AMOOR_H_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_H_AQ)
  .value("AMOOR_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOOR_H_AQ_RL)
  .value("AMOOR_H_RL", LIEF::assembly::riscv::OPCODE::AMOOR_H_RL)
  .value("AMOOR_W", LIEF::assembly::riscv::OPCODE::AMOOR_W)
  .value("AMOOR_W_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_W_AQ)
  .value("AMOOR_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOOR_W_AQ_RL)
  .value("AMOOR_W_RL", LIEF::assembly::riscv::OPCODE::AMOOR_W_RL)
  .value("AMOSWAP_B", LIEF::assembly::riscv::OPCODE::AMOSWAP_B)
  .value("AMOSWAP_B_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQ)
  .value("AMOSWAP_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQ_RL)
  .value("AMOSWAP_B_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_RL)
  .value("AMOSWAP_D", LIEF::assembly::riscv::OPCODE::AMOSWAP_D)
  .value("AMOSWAP_D_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQ)
  .value("AMOSWAP_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQ_RL)
  .value("AMOSWAP_D_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_RL)
  .value("AMOSWAP_H", LIEF::assembly::riscv::OPCODE::AMOSWAP_H)
  .value("AMOSWAP_H_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQ)
  .value("AMOSWAP_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQ_RL)
  .value("AMOSWAP_H_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_RL)
  .value("AMOSWAP_W", LIEF::assembly::riscv::OPCODE::AMOSWAP_W)
  .value("AMOSWAP_W_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQ)
  .value("AMOSWAP_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQ_RL)
  .value("AMOSWAP_W_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_RL)
  .value("AMOXOR_B", LIEF::assembly::riscv::OPCODE::AMOXOR_B)
  .value("AMOXOR_B_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQ)
  .value("AMOXOR_B_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQ_RL)
  .value("AMOXOR_B_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_B_RL)
  .value("AMOXOR_D", LIEF::assembly::riscv::OPCODE::AMOXOR_D)
  .value("AMOXOR_D_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQ)
  .value("AMOXOR_D_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQ_RL)
  .value("AMOXOR_D_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_D_RL)
  .value("AMOXOR_H", LIEF::assembly::riscv::OPCODE::AMOXOR_H)
  .value("AMOXOR_H_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQ)
  .value("AMOXOR_H_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQ_RL)
  .value("AMOXOR_H_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_H_RL)
  .value("AMOXOR_W", LIEF::assembly::riscv::OPCODE::AMOXOR_W)
  .value("AMOXOR_W_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQ)
  .value("AMOXOR_W_AQ_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQ_RL)
  .value("AMOXOR_W_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_W_RL)
  .value("AND", LIEF::assembly::riscv::OPCODE::AND)
  .value("ANDI", LIEF::assembly::riscv::OPCODE::ANDI)
  .value("ANDN", LIEF::assembly::riscv::OPCODE::ANDN)
  .value("AUIPC", LIEF::assembly::riscv::OPCODE::AUIPC)
  .value("BCLR", LIEF::assembly::riscv::OPCODE::BCLR)
  .value("BCLRI", LIEF::assembly::riscv::OPCODE::BCLRI)
  .value("BEQ", LIEF::assembly::riscv::OPCODE::BEQ)
  .value("BEXT", LIEF::assembly::riscv::OPCODE::BEXT)
  .value("BEXTI", LIEF::assembly::riscv::OPCODE::BEXTI)
  .value("BGE", LIEF::assembly::riscv::OPCODE::BGE)
  .value("BGEU", LIEF::assembly::riscv::OPCODE::BGEU)
  .value("BINV", LIEF::assembly::riscv::OPCODE::BINV)
  .value("BINVI", LIEF::assembly::riscv::OPCODE::BINVI)
  .value("BLT", LIEF::assembly::riscv::OPCODE::BLT)
  .value("BLTU", LIEF::assembly::riscv::OPCODE::BLTU)
  .value("BNE", LIEF::assembly::riscv::OPCODE::BNE)
  .value("BREV8", LIEF::assembly::riscv::OPCODE::BREV8)
  .value("BSET", LIEF::assembly::riscv::OPCODE::BSET)
  .value("BSETI", LIEF::assembly::riscv::OPCODE::BSETI)
  .value("CBO_CLEAN", LIEF::assembly::riscv::OPCODE::CBO_CLEAN)
  .value("CBO_FLUSH", LIEF::assembly::riscv::OPCODE::CBO_FLUSH)
  .value("CBO_INVAL", LIEF::assembly::riscv::OPCODE::CBO_INVAL)
  .value("CBO_ZERO", LIEF::assembly::riscv::OPCODE::CBO_ZERO)
  .value("CLMUL", LIEF::assembly::riscv::OPCODE::CLMUL)
  .value("CLMULH", LIEF::assembly::riscv::OPCODE::CLMULH)
  .value("CLMULR", LIEF::assembly::riscv::OPCODE::CLMULR)
  .value("CLZ", LIEF::assembly::riscv::OPCODE::CLZ)
  .value("CLZW", LIEF::assembly::riscv::OPCODE::CLZW)
  .value("CM_JALT", LIEF::assembly::riscv::OPCODE::CM_JALT)
  .value("CM_JT", LIEF::assembly::riscv::OPCODE::CM_JT)
  .value("CM_MVA01S", LIEF::assembly::riscv::OPCODE::CM_MVA01S)
  .value("CM_MVSA01", LIEF::assembly::riscv::OPCODE::CM_MVSA01)
  .value("CM_POP", LIEF::assembly::riscv::OPCODE::CM_POP)
  .value("CM_POPRET", LIEF::assembly::riscv::OPCODE::CM_POPRET)
  .value("CM_POPRETZ", LIEF::assembly::riscv::OPCODE::CM_POPRETZ)
  .value("CM_PUSH", LIEF::assembly::riscv::OPCODE::CM_PUSH)
  .value("CPOP", LIEF::assembly::riscv::OPCODE::CPOP)
  .value("CPOPW", LIEF::assembly::riscv::OPCODE::CPOPW)
  .value("CSRRC", LIEF::assembly::riscv::OPCODE::CSRRC)
  .value("CSRRCI", LIEF::assembly::riscv::OPCODE::CSRRCI)
  .value("CSRRS", LIEF::assembly::riscv::OPCODE::CSRRS)
  .value("CSRRSI", LIEF::assembly::riscv::OPCODE::CSRRSI)
  .value("CSRRW", LIEF::assembly::riscv::OPCODE::CSRRW)
  .value("CSRRWI", LIEF::assembly::riscv::OPCODE::CSRRWI)
  .value("CTZ", LIEF::assembly::riscv::OPCODE::CTZ)
  .value("CTZW", LIEF::assembly::riscv::OPCODE::CTZW)
  .value("CV_ABS", LIEF::assembly::riscv::OPCODE::CV_ABS)
  .value("CV_ABS_B", LIEF::assembly::riscv::OPCODE::CV_ABS_B)
  .value("CV_ABS_H", LIEF::assembly::riscv::OPCODE::CV_ABS_H)
  .value("CV_ADDN", LIEF::assembly::riscv::OPCODE::CV_ADDN)
  .value("CV_ADDNR", LIEF::assembly::riscv::OPCODE::CV_ADDNR)
  .value("CV_ADDRN", LIEF::assembly::riscv::OPCODE::CV_ADDRN)
  .value("CV_ADDRNR", LIEF::assembly::riscv::OPCODE::CV_ADDRNR)
  .value("CV_ADDUN", LIEF::assembly::riscv::OPCODE::CV_ADDUN)
  .value("CV_ADDUNR", LIEF::assembly::riscv::OPCODE::CV_ADDUNR)
  .value("CV_ADDURN", LIEF::assembly::riscv::OPCODE::CV_ADDURN)
  .value("CV_ADDURNR", LIEF::assembly::riscv::OPCODE::CV_ADDURNR)
  .value("CV_ADD_B", LIEF::assembly::riscv::OPCODE::CV_ADD_B)
  .value("CV_ADD_DIV2", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV2)
  .value("CV_ADD_DIV4", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV4)
  .value("CV_ADD_DIV8", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV8)
  .value("CV_ADD_H", LIEF::assembly::riscv::OPCODE::CV_ADD_H)
  .value("CV_ADD_SCI_B", LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_B)
  .value("CV_ADD_SCI_H", LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_H)
  .value("CV_ADD_SC_B", LIEF::assembly::riscv::OPCODE::CV_ADD_SC_B)
  .value("CV_ADD_SC_H", LIEF::assembly::riscv::OPCODE::CV_ADD_SC_H)
  .value("CV_AND_B", LIEF::assembly::riscv::OPCODE::CV_AND_B)
  .value("CV_AND_H", LIEF::assembly::riscv::OPCODE::CV_AND_H)
  .value("CV_AND_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AND_SCI_B)
  .value("CV_AND_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AND_SCI_H)
  .value("CV_AND_SC_B", LIEF::assembly::riscv::OPCODE::CV_AND_SC_B)
  .value("CV_AND_SC_H", LIEF::assembly::riscv::OPCODE::CV_AND_SC_H)
  .value("CV_AVGU_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_B)
  .value("CV_AVGU_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_H)
  .value("CV_AVGU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_B)
  .value("CV_AVGU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_H)
  .value("CV_AVGU_SC_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_B)
  .value("CV_AVGU_SC_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_H)
  .value("CV_AVG_B", LIEF::assembly::riscv::OPCODE::CV_AVG_B)
  .value("CV_AVG_H", LIEF::assembly::riscv::OPCODE::CV_AVG_H)
  .value("CV_AVG_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_B)
  .value("CV_AVG_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_H)
  .value("CV_AVG_SC_B", LIEF::assembly::riscv::OPCODE::CV_AVG_SC_B)
  .value("CV_AVG_SC_H", LIEF::assembly::riscv::OPCODE::CV_AVG_SC_H)
  .value("CV_BCLR", LIEF::assembly::riscv::OPCODE::CV_BCLR)
  .value("CV_BCLRR", LIEF::assembly::riscv::OPCODE::CV_BCLRR)
  .value("CV_BEQIMM", LIEF::assembly::riscv::OPCODE::CV_BEQIMM)
  .value("CV_BITREV", LIEF::assembly::riscv::OPCODE::CV_BITREV)
  .value("CV_BNEIMM", LIEF::assembly::riscv::OPCODE::CV_BNEIMM)
  .value("CV_BSET", LIEF::assembly::riscv::OPCODE::CV_BSET)
  .value("CV_BSETR", LIEF::assembly::riscv::OPCODE::CV_BSETR)
  .value("CV_CLB", LIEF::assembly::riscv::OPCODE::CV_CLB)
  .value("CV_CLIP", LIEF::assembly::riscv::OPCODE::CV_CLIP)
  .value("CV_CLIPR", LIEF::assembly::riscv::OPCODE::CV_CLIPR)
  .value("CV_CLIPU", LIEF::assembly::riscv::OPCODE::CV_CLIPU)
  .value("CV_CLIPUR", LIEF::assembly::riscv::OPCODE::CV_CLIPUR)
  .value("CV_CMPEQ_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_B)
  .value("CV_CMPEQ_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_H)
  .value("CV_CMPEQ_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_B)
  .value("CV_CMPEQ_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_H)
  .value("CV_CMPEQ_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_B)
  .value("CV_CMPEQ_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_H)
  .value("CV_CMPGEU_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_B)
  .value("CV_CMPGEU_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_H)
  .value("CV_CMPGEU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_B)
  .value("CV_CMPGEU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_H)
  .value("CV_CMPGEU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_B)
  .value("CV_CMPGEU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_H)
  .value("CV_CMPGE_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_B)
  .value("CV_CMPGE_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_H)
  .value("CV_CMPGE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_B)
  .value("CV_CMPGE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_H)
  .value("CV_CMPGE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_B)
  .value("CV_CMPGE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_H)
  .value("CV_CMPGTU_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_B)
  .value("CV_CMPGTU_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_H)
  .value("CV_CMPGTU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_B)
  .value("CV_CMPGTU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_H)
  .value("CV_CMPGTU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_B)
  .value("CV_CMPGTU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_H)
  .value("CV_CMPGT_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_B)
  .value("CV_CMPGT_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_H)
  .value("CV_CMPGT_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_B)
  .value("CV_CMPGT_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_H)
  .value("CV_CMPGT_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_B)
  .value("CV_CMPGT_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_H)
  .value("CV_CMPLEU_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_B)
  .value("CV_CMPLEU_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_H)
  .value("CV_CMPLEU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_B)
  .value("CV_CMPLEU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_H)
  .value("CV_CMPLEU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_B)
  .value("CV_CMPLEU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_H)
  .value("CV_CMPLE_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_B)
  .value("CV_CMPLE_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_H)
  .value("CV_CMPLE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_B)
  .value("CV_CMPLE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_H)
  .value("CV_CMPLE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_B)
  .value("CV_CMPLE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_H)
  .value("CV_CMPLTU_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_B)
  .value("CV_CMPLTU_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_H)
  .value("CV_CMPLTU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_B)
  .value("CV_CMPLTU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_H)
  .value("CV_CMPLTU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_B)
  .value("CV_CMPLTU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_H)
  .value("CV_CMPLT_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_B)
  .value("CV_CMPLT_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_H)
  .value("CV_CMPLT_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_B)
  .value("CV_CMPLT_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_H)
  .value("CV_CMPLT_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_B)
  .value("CV_CMPLT_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_H)
  .value("CV_CMPNE_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_B)
  .value("CV_CMPNE_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_H)
  .value("CV_CMPNE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_B)
  .value("CV_CMPNE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_H)
  .value("CV_CMPNE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_B)
  .value("CV_CMPNE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_H)
  .value("CV_CNT", LIEF::assembly::riscv::OPCODE::CV_CNT)
  .value("CV_CPLXCONJ", LIEF::assembly::riscv::OPCODE::CV_CPLXCONJ)
  .value("CV_CPLXMUL_I", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I)
  .value("CV_CPLXMUL_I_DIV2", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV2)
  .value("CV_CPLXMUL_I_DIV4", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV4)
  .value("CV_CPLXMUL_I_DIV8", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV8)
  .value("CV_CPLXMUL_R", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R)
  .value("CV_CPLXMUL_R_DIV2", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV2)
  .value("CV_CPLXMUL_R_DIV4", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV4)
  .value("CV_CPLXMUL_R_DIV8", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV8)
  .value("CV_DOTSP_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_B)
  .value("CV_DOTSP_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_H)
  .value("CV_DOTSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_B)
  .value("CV_DOTSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_H)
  .value("CV_DOTSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_B)
  .value("CV_DOTSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_H)
  .value("CV_DOTUP_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_B)
  .value("CV_DOTUP_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_H)
  .value("CV_DOTUP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_B)
  .value("CV_DOTUP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_H)
  .value("CV_DOTUP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_B)
  .value("CV_DOTUP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_H)
  .value("CV_DOTUSP_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_B)
  .value("CV_DOTUSP_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_H)
  .value("CV_DOTUSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_B)
  .value("CV_DOTUSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_H)
  .value("CV_DOTUSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_B)
  .value("CV_DOTUSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_H)
  .value("CV_ELW", LIEF::assembly::riscv::OPCODE::CV_ELW)
  .value("CV_EXTBS", LIEF::assembly::riscv::OPCODE::CV_EXTBS)
  .value("CV_EXTBZ", LIEF::assembly::riscv::OPCODE::CV_EXTBZ)
  .value("CV_EXTHS", LIEF::assembly::riscv::OPCODE::CV_EXTHS)
  .value("CV_EXTHZ", LIEF::assembly::riscv::OPCODE::CV_EXTHZ)
  .value("CV_EXTRACT", LIEF::assembly::riscv::OPCODE::CV_EXTRACT)
  .value("CV_EXTRACTR", LIEF::assembly::riscv::OPCODE::CV_EXTRACTR)
  .value("CV_EXTRACTU", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU)
  .value("CV_EXTRACTUR", LIEF::assembly::riscv::OPCODE::CV_EXTRACTUR)
  .value("CV_EXTRACTU_B", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_B)
  .value("CV_EXTRACTU_H", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_H)
  .value("CV_EXTRACT_B", LIEF::assembly::riscv::OPCODE::CV_EXTRACT_B)
  .value("CV_EXTRACT_H", LIEF::assembly::riscv::OPCODE::CV_EXTRACT_H)
  .value("CV_FF1", LIEF::assembly::riscv::OPCODE::CV_FF1)
  .value("CV_FL1", LIEF::assembly::riscv::OPCODE::CV_FL1)
  .value("CV_INSERT", LIEF::assembly::riscv::OPCODE::CV_INSERT)
  .value("CV_INSERTR", LIEF::assembly::riscv::OPCODE::CV_INSERTR)
  .value("CV_INSERT_B", LIEF::assembly::riscv::OPCODE::CV_INSERT_B)
  .value("CV_INSERT_H", LIEF::assembly::riscv::OPCODE::CV_INSERT_H)
  .value("CV_LBU_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LBU_ri_inc)
  .value("CV_LBU_rr", LIEF::assembly::riscv::OPCODE::CV_LBU_rr)
  .value("CV_LBU_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LBU_rr_inc)
  .value("CV_LB_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LB_ri_inc)
  .value("CV_LB_rr", LIEF::assembly::riscv::OPCODE::CV_LB_rr)
  .value("CV_LB_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LB_rr_inc);
  opcodes.value("CV_LHU_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LHU_ri_inc)
  .value("CV_LHU_rr", LIEF::assembly::riscv::OPCODE::CV_LHU_rr)
  .value("CV_LHU_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LHU_rr_inc)
  .value("CV_LH_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LH_ri_inc)
  .value("CV_LH_rr", LIEF::assembly::riscv::OPCODE::CV_LH_rr)
  .value("CV_LH_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LH_rr_inc)
  .value("CV_LW_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LW_ri_inc)
  .value("CV_LW_rr", LIEF::assembly::riscv::OPCODE::CV_LW_rr)
  .value("CV_LW_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LW_rr_inc)
  .value("CV_MAC", LIEF::assembly::riscv::OPCODE::CV_MAC)
  .value("CV_MACHHSN", LIEF::assembly::riscv::OPCODE::CV_MACHHSN)
  .value("CV_MACHHSRN", LIEF::assembly::riscv::OPCODE::CV_MACHHSRN)
  .value("CV_MACHHUN", LIEF::assembly::riscv::OPCODE::CV_MACHHUN)
  .value("CV_MACHHURN", LIEF::assembly::riscv::OPCODE::CV_MACHHURN)
  .value("CV_MACSN", LIEF::assembly::riscv::OPCODE::CV_MACSN)
  .value("CV_MACSRN", LIEF::assembly::riscv::OPCODE::CV_MACSRN)
  .value("CV_MACUN", LIEF::assembly::riscv::OPCODE::CV_MACUN)
  .value("CV_MACURN", LIEF::assembly::riscv::OPCODE::CV_MACURN)
  .value("CV_MAX", LIEF::assembly::riscv::OPCODE::CV_MAX)
  .value("CV_MAXU", LIEF::assembly::riscv::OPCODE::CV_MAXU)
  .value("CV_MAXU_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_B)
  .value("CV_MAXU_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_H)
  .value("CV_MAXU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_B)
  .value("CV_MAXU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_H)
  .value("CV_MAXU_SC_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_B)
  .value("CV_MAXU_SC_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_H)
  .value("CV_MAX_B", LIEF::assembly::riscv::OPCODE::CV_MAX_B)
  .value("CV_MAX_H", LIEF::assembly::riscv::OPCODE::CV_MAX_H)
  .value("CV_MAX_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_B)
  .value("CV_MAX_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_H)
  .value("CV_MAX_SC_B", LIEF::assembly::riscv::OPCODE::CV_MAX_SC_B)
  .value("CV_MAX_SC_H", LIEF::assembly::riscv::OPCODE::CV_MAX_SC_H)
  .value("CV_MIN", LIEF::assembly::riscv::OPCODE::CV_MIN)
  .value("CV_MINU", LIEF::assembly::riscv::OPCODE::CV_MINU)
  .value("CV_MINU_B", LIEF::assembly::riscv::OPCODE::CV_MINU_B)
  .value("CV_MINU_H", LIEF::assembly::riscv::OPCODE::CV_MINU_H)
  .value("CV_MINU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_B)
  .value("CV_MINU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_H)
  .value("CV_MINU_SC_B", LIEF::assembly::riscv::OPCODE::CV_MINU_SC_B)
  .value("CV_MINU_SC_H", LIEF::assembly::riscv::OPCODE::CV_MINU_SC_H)
  .value("CV_MIN_B", LIEF::assembly::riscv::OPCODE::CV_MIN_B)
  .value("CV_MIN_H", LIEF::assembly::riscv::OPCODE::CV_MIN_H)
  .value("CV_MIN_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_B)
  .value("CV_MIN_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_H)
  .value("CV_MIN_SC_B", LIEF::assembly::riscv::OPCODE::CV_MIN_SC_B)
  .value("CV_MIN_SC_H", LIEF::assembly::riscv::OPCODE::CV_MIN_SC_H)
  .value("CV_MSU", LIEF::assembly::riscv::OPCODE::CV_MSU)
  .value("CV_MULHHSN", LIEF::assembly::riscv::OPCODE::CV_MULHHSN)
  .value("CV_MULHHSRN", LIEF::assembly::riscv::OPCODE::CV_MULHHSRN)
  .value("CV_MULHHUN", LIEF::assembly::riscv::OPCODE::CV_MULHHUN)
  .value("CV_MULHHURN", LIEF::assembly::riscv::OPCODE::CV_MULHHURN)
  .value("CV_MULSN", LIEF::assembly::riscv::OPCODE::CV_MULSN)
  .value("CV_MULSRN", LIEF::assembly::riscv::OPCODE::CV_MULSRN)
  .value("CV_MULUN", LIEF::assembly::riscv::OPCODE::CV_MULUN)
  .value("CV_MULURN", LIEF::assembly::riscv::OPCODE::CV_MULURN)
  .value("CV_OR_B", LIEF::assembly::riscv::OPCODE::CV_OR_B)
  .value("CV_OR_H", LIEF::assembly::riscv::OPCODE::CV_OR_H)
  .value("CV_OR_SCI_B", LIEF::assembly::riscv::OPCODE::CV_OR_SCI_B)
  .value("CV_OR_SCI_H", LIEF::assembly::riscv::OPCODE::CV_OR_SCI_H)
  .value("CV_OR_SC_B", LIEF::assembly::riscv::OPCODE::CV_OR_SC_B)
  .value("CV_OR_SC_H", LIEF::assembly::riscv::OPCODE::CV_OR_SC_H)
  .value("CV_PACK", LIEF::assembly::riscv::OPCODE::CV_PACK)
  .value("CV_PACKHI_B", LIEF::assembly::riscv::OPCODE::CV_PACKHI_B)
  .value("CV_PACKLO_B", LIEF::assembly::riscv::OPCODE::CV_PACKLO_B)
  .value("CV_PACK_H", LIEF::assembly::riscv::OPCODE::CV_PACK_H)
  .value("CV_ROR", LIEF::assembly::riscv::OPCODE::CV_ROR)
  .value("CV_SB_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SB_ri_inc)
  .value("CV_SB_rr", LIEF::assembly::riscv::OPCODE::CV_SB_rr)
  .value("CV_SB_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SB_rr_inc)
  .value("CV_SDOTSP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_B)
  .value("CV_SDOTSP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_H)
  .value("CV_SDOTSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_B)
  .value("CV_SDOTSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_H)
  .value("CV_SDOTSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_B)
  .value("CV_SDOTSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_H)
  .value("CV_SDOTUP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_B)
  .value("CV_SDOTUP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_H)
  .value("CV_SDOTUP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_B)
  .value("CV_SDOTUP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_H)
  .value("CV_SDOTUP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_B)
  .value("CV_SDOTUP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_H)
  .value("CV_SDOTUSP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_B)
  .value("CV_SDOTUSP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_H)
  .value("CV_SDOTUSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_B)
  .value("CV_SDOTUSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_H)
  .value("CV_SDOTUSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_B)
  .value("CV_SDOTUSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_H)
  .value("CV_SHUFFLE2_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_B)
  .value("CV_SHUFFLE2_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_H)
  .value("CV_SHUFFLEI0_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI0_SCI_B)
  .value("CV_SHUFFLEI1_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI1_SCI_B)
  .value("CV_SHUFFLEI2_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI2_SCI_B)
  .value("CV_SHUFFLEI3_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI3_SCI_B)
  .value("CV_SHUFFLE_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_B)
  .value("CV_SHUFFLE_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_H)
  .value("CV_SHUFFLE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_SCI_H)
  .value("CV_SH_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SH_ri_inc)
  .value("CV_SH_rr", LIEF::assembly::riscv::OPCODE::CV_SH_rr)
  .value("CV_SH_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SH_rr_inc)
  .value("CV_SLET", LIEF::assembly::riscv::OPCODE::CV_SLET)
  .value("CV_SLETU", LIEF::assembly::riscv::OPCODE::CV_SLETU)
  .value("CV_SLL_B", LIEF::assembly::riscv::OPCODE::CV_SLL_B)
  .value("CV_SLL_H", LIEF::assembly::riscv::OPCODE::CV_SLL_H)
  .value("CV_SLL_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_B)
  .value("CV_SLL_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_H)
  .value("CV_SLL_SC_B", LIEF::assembly::riscv::OPCODE::CV_SLL_SC_B)
  .value("CV_SLL_SC_H", LIEF::assembly::riscv::OPCODE::CV_SLL_SC_H)
  .value("CV_SRA_B", LIEF::assembly::riscv::OPCODE::CV_SRA_B)
  .value("CV_SRA_H", LIEF::assembly::riscv::OPCODE::CV_SRA_H)
  .value("CV_SRA_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_B)
  .value("CV_SRA_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_H)
  .value("CV_SRA_SC_B", LIEF::assembly::riscv::OPCODE::CV_SRA_SC_B)
  .value("CV_SRA_SC_H", LIEF::assembly::riscv::OPCODE::CV_SRA_SC_H)
  .value("CV_SRL_B", LIEF::assembly::riscv::OPCODE::CV_SRL_B)
  .value("CV_SRL_H", LIEF::assembly::riscv::OPCODE::CV_SRL_H)
  .value("CV_SRL_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_B)
  .value("CV_SRL_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_H)
  .value("CV_SRL_SC_B", LIEF::assembly::riscv::OPCODE::CV_SRL_SC_B)
  .value("CV_SRL_SC_H", LIEF::assembly::riscv::OPCODE::CV_SRL_SC_H)
  .value("CV_SUBN", LIEF::assembly::riscv::OPCODE::CV_SUBN)
  .value("CV_SUBNR", LIEF::assembly::riscv::OPCODE::CV_SUBNR)
  .value("CV_SUBRN", LIEF::assembly::riscv::OPCODE::CV_SUBRN)
  .value("CV_SUBRNR", LIEF::assembly::riscv::OPCODE::CV_SUBRNR)
  .value("CV_SUBROTMJ", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ)
  .value("CV_SUBROTMJ_DIV2", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV2)
  .value("CV_SUBROTMJ_DIV4", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV4)
  .value("CV_SUBROTMJ_DIV8", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV8)
  .value("CV_SUBUN", LIEF::assembly::riscv::OPCODE::CV_SUBUN)
  .value("CV_SUBUNR", LIEF::assembly::riscv::OPCODE::CV_SUBUNR)
  .value("CV_SUBURN", LIEF::assembly::riscv::OPCODE::CV_SUBURN)
  .value("CV_SUBURNR", LIEF::assembly::riscv::OPCODE::CV_SUBURNR)
  .value("CV_SUB_B", LIEF::assembly::riscv::OPCODE::CV_SUB_B)
  .value("CV_SUB_DIV2", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV2)
  .value("CV_SUB_DIV4", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV4)
  .value("CV_SUB_DIV8", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV8)
  .value("CV_SUB_H", LIEF::assembly::riscv::OPCODE::CV_SUB_H)
  .value("CV_SUB_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_B)
  .value("CV_SUB_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_H)
  .value("CV_SUB_SC_B", LIEF::assembly::riscv::OPCODE::CV_SUB_SC_B)
  .value("CV_SUB_SC_H", LIEF::assembly::riscv::OPCODE::CV_SUB_SC_H)
  .value("CV_SW_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SW_ri_inc)
  .value("CV_SW_rr", LIEF::assembly::riscv::OPCODE::CV_SW_rr)
  .value("CV_SW_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SW_rr_inc)
  .value("CV_XOR_B", LIEF::assembly::riscv::OPCODE::CV_XOR_B)
  .value("CV_XOR_H", LIEF::assembly::riscv::OPCODE::CV_XOR_H)
  .value("CV_XOR_SCI_B", LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_B)
  .value("CV_XOR_SCI_H", LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_H)
  .value("CV_XOR_SC_B", LIEF::assembly::riscv::OPCODE::CV_XOR_SC_B)
  .value("CV_XOR_SC_H", LIEF::assembly::riscv::OPCODE::CV_XOR_SC_H)
  .value("CZERO_EQZ", LIEF::assembly::riscv::OPCODE::CZERO_EQZ)
  .value("CZERO_NEZ", LIEF::assembly::riscv::OPCODE::CZERO_NEZ)
  .value("C_ADD", LIEF::assembly::riscv::OPCODE::C_ADD)
  .value("C_ADDI", LIEF::assembly::riscv::OPCODE::C_ADDI)
  .value("C_ADDI16SP", LIEF::assembly::riscv::OPCODE::C_ADDI16SP)
  .value("C_ADDI4SPN", LIEF::assembly::riscv::OPCODE::C_ADDI4SPN)
  .value("C_ADDIW", LIEF::assembly::riscv::OPCODE::C_ADDIW)
  .value("C_ADDI_HINT_IMM_ZERO", LIEF::assembly::riscv::OPCODE::C_ADDI_HINT_IMM_ZERO)
  .value("C_ADDI_NOP", LIEF::assembly::riscv::OPCODE::C_ADDI_NOP)
  .value("C_ADDW", LIEF::assembly::riscv::OPCODE::C_ADDW)
  .value("C_ADD_HINT", LIEF::assembly::riscv::OPCODE::C_ADD_HINT)
  .value("C_AND", LIEF::assembly::riscv::OPCODE::C_AND)
  .value("C_ANDI", LIEF::assembly::riscv::OPCODE::C_ANDI)
  .value("C_BEQZ", LIEF::assembly::riscv::OPCODE::C_BEQZ)
  .value("C_BNEZ", LIEF::assembly::riscv::OPCODE::C_BNEZ)
  .value("C_EBREAK", LIEF::assembly::riscv::OPCODE::C_EBREAK)
  .value("C_FLD", LIEF::assembly::riscv::OPCODE::C_FLD)
  .value("C_FLDSP", LIEF::assembly::riscv::OPCODE::C_FLDSP)
  .value("C_FLW", LIEF::assembly::riscv::OPCODE::C_FLW)
  .value("C_FLWSP", LIEF::assembly::riscv::OPCODE::C_FLWSP)
  .value("C_FSD", LIEF::assembly::riscv::OPCODE::C_FSD)
  .value("C_FSDSP", LIEF::assembly::riscv::OPCODE::C_FSDSP)
  .value("C_FSW", LIEF::assembly::riscv::OPCODE::C_FSW)
  .value("C_FSWSP", LIEF::assembly::riscv::OPCODE::C_FSWSP)
  .value("C_J", LIEF::assembly::riscv::OPCODE::C_J)
  .value("C_JAL", LIEF::assembly::riscv::OPCODE::C_JAL)
  .value("C_JALR", LIEF::assembly::riscv::OPCODE::C_JALR)
  .value("C_JR", LIEF::assembly::riscv::OPCODE::C_JR)
  .value("C_LBU", LIEF::assembly::riscv::OPCODE::C_LBU)
  .value("C_LD", LIEF::assembly::riscv::OPCODE::C_LD)
  .value("C_LDSP", LIEF::assembly::riscv::OPCODE::C_LDSP)
  .value("C_LH", LIEF::assembly::riscv::OPCODE::C_LH)
  .value("C_LHU", LIEF::assembly::riscv::OPCODE::C_LHU)
  .value("C_LI", LIEF::assembly::riscv::OPCODE::C_LI)
  .value("C_LI_HINT", LIEF::assembly::riscv::OPCODE::C_LI_HINT)
  .value("C_LUI", LIEF::assembly::riscv::OPCODE::C_LUI)
  .value("C_LUI_HINT", LIEF::assembly::riscv::OPCODE::C_LUI_HINT)
  .value("C_LW", LIEF::assembly::riscv::OPCODE::C_LW)
  .value("C_LWSP", LIEF::assembly::riscv::OPCODE::C_LWSP)
  .value("C_MOP1", LIEF::assembly::riscv::OPCODE::C_MOP1)
  .value("C_MOP11", LIEF::assembly::riscv::OPCODE::C_MOP11)
  .value("C_MOP13", LIEF::assembly::riscv::OPCODE::C_MOP13)
  .value("C_MOP15", LIEF::assembly::riscv::OPCODE::C_MOP15)
  .value("C_MOP3", LIEF::assembly::riscv::OPCODE::C_MOP3)
  .value("C_MOP5", LIEF::assembly::riscv::OPCODE::C_MOP5)
  .value("C_MOP7", LIEF::assembly::riscv::OPCODE::C_MOP7)
  .value("C_MOP9", LIEF::assembly::riscv::OPCODE::C_MOP9)
  .value("C_MUL", LIEF::assembly::riscv::OPCODE::C_MUL)
  .value("C_MV", LIEF::assembly::riscv::OPCODE::C_MV)
  .value("C_MV_HINT", LIEF::assembly::riscv::OPCODE::C_MV_HINT)
  .value("C_NOP", LIEF::assembly::riscv::OPCODE::C_NOP)
  .value("C_NOP_HINT", LIEF::assembly::riscv::OPCODE::C_NOP_HINT)
  .value("C_NOT", LIEF::assembly::riscv::OPCODE::C_NOT)
  .value("C_OR", LIEF::assembly::riscv::OPCODE::C_OR)
  .value("C_SB", LIEF::assembly::riscv::OPCODE::C_SB)
  .value("C_SD", LIEF::assembly::riscv::OPCODE::C_SD)
  .value("C_SDSP", LIEF::assembly::riscv::OPCODE::C_SDSP)
  .value("C_SEXT_B", LIEF::assembly::riscv::OPCODE::C_SEXT_B)
  .value("C_SEXT_H", LIEF::assembly::riscv::OPCODE::C_SEXT_H)
  .value("C_SH", LIEF::assembly::riscv::OPCODE::C_SH)
  .value("C_SLLI", LIEF::assembly::riscv::OPCODE::C_SLLI)
  .value("C_SLLI64_HINT", LIEF::assembly::riscv::OPCODE::C_SLLI64_HINT)
  .value("C_SLLI_HINT", LIEF::assembly::riscv::OPCODE::C_SLLI_HINT)
  .value("C_SRAI", LIEF::assembly::riscv::OPCODE::C_SRAI)
  .value("C_SRAI64_HINT", LIEF::assembly::riscv::OPCODE::C_SRAI64_HINT)
  .value("C_SRLI", LIEF::assembly::riscv::OPCODE::C_SRLI)
  .value("C_SRLI64_HINT", LIEF::assembly::riscv::OPCODE::C_SRLI64_HINT)
  .value("C_SSPOPCHK", LIEF::assembly::riscv::OPCODE::C_SSPOPCHK)
  .value("C_SSPUSH", LIEF::assembly::riscv::OPCODE::C_SSPUSH)
  .value("C_SUB", LIEF::assembly::riscv::OPCODE::C_SUB)
  .value("C_SUBW", LIEF::assembly::riscv::OPCODE::C_SUBW)
  .value("C_SW", LIEF::assembly::riscv::OPCODE::C_SW)
  .value("C_SWSP", LIEF::assembly::riscv::OPCODE::C_SWSP)
  .value("C_UNIMP", LIEF::assembly::riscv::OPCODE::C_UNIMP)
  .value("C_XOR", LIEF::assembly::riscv::OPCODE::C_XOR)
  .value("C_ZEXT_B", LIEF::assembly::riscv::OPCODE::C_ZEXT_B)
  .value("C_ZEXT_H", LIEF::assembly::riscv::OPCODE::C_ZEXT_H)
  .value("C_ZEXT_W", LIEF::assembly::riscv::OPCODE::C_ZEXT_W)
  .value("DIV", LIEF::assembly::riscv::OPCODE::DIV)
  .value("DIVU", LIEF::assembly::riscv::OPCODE::DIVU)
  .value("DIVUW", LIEF::assembly::riscv::OPCODE::DIVUW)
  .value("DIVW", LIEF::assembly::riscv::OPCODE::DIVW)
  .value("DRET", LIEF::assembly::riscv::OPCODE::DRET)
  .value("EBREAK", LIEF::assembly::riscv::OPCODE::EBREAK)
  .value("ECALL", LIEF::assembly::riscv::OPCODE::ECALL)
  .value("FADD_D", LIEF::assembly::riscv::OPCODE::FADD_D)
  .value("FADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FADD_D_IN32X)
  .value("FADD_D_INX", LIEF::assembly::riscv::OPCODE::FADD_D_INX)
  .value("FADD_H", LIEF::assembly::riscv::OPCODE::FADD_H)
  .value("FADD_H_INX", LIEF::assembly::riscv::OPCODE::FADD_H_INX)
  .value("FADD_S", LIEF::assembly::riscv::OPCODE::FADD_S)
  .value("FADD_S_INX", LIEF::assembly::riscv::OPCODE::FADD_S_INX)
  .value("FCLASS_D", LIEF::assembly::riscv::OPCODE::FCLASS_D)
  .value("FCLASS_D_IN32X", LIEF::assembly::riscv::OPCODE::FCLASS_D_IN32X)
  .value("FCLASS_D_INX", LIEF::assembly::riscv::OPCODE::FCLASS_D_INX)
  .value("FCLASS_H", LIEF::assembly::riscv::OPCODE::FCLASS_H)
  .value("FCLASS_H_INX", LIEF::assembly::riscv::OPCODE::FCLASS_H_INX)
  .value("FCLASS_S", LIEF::assembly::riscv::OPCODE::FCLASS_S)
  .value("FCLASS_S_INX", LIEF::assembly::riscv::OPCODE::FCLASS_S_INX)
  .value("FCVTMOD_W_D", LIEF::assembly::riscv::OPCODE::FCVTMOD_W_D)
  .value("FCVT_BF16_S", LIEF::assembly::riscv::OPCODE::FCVT_BF16_S)
  .value("FCVT_D_H", LIEF::assembly::riscv::OPCODE::FCVT_D_H)
  .value("FCVT_D_H_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_H_IN32X)
  .value("FCVT_D_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_H_INX)
  .value("FCVT_D_L", LIEF::assembly::riscv::OPCODE::FCVT_D_L)
  .value("FCVT_D_LU", LIEF::assembly::riscv::OPCODE::FCVT_D_LU)
  .value("FCVT_D_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_LU_INX)
  .value("FCVT_D_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_L_INX)
  .value("FCVT_D_S", LIEF::assembly::riscv::OPCODE::FCVT_D_S)
  .value("FCVT_D_S_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_S_IN32X)
  .value("FCVT_D_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_S_INX)
  .value("FCVT_D_W", LIEF::assembly::riscv::OPCODE::FCVT_D_W)
  .value("FCVT_D_WU", LIEF::assembly::riscv::OPCODE::FCVT_D_WU)
  .value("FCVT_D_WU_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_WU_IN32X)
  .value("FCVT_D_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_WU_INX)
  .value("FCVT_D_W_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_W_IN32X)
  .value("FCVT_D_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_W_INX)
  .value("FCVT_H_D", LIEF::assembly::riscv::OPCODE::FCVT_H_D)
  .value("FCVT_H_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_H_D_IN32X)
  .value("FCVT_H_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_D_INX)
  .value("FCVT_H_L", LIEF::assembly::riscv::OPCODE::FCVT_H_L)
  .value("FCVT_H_LU", LIEF::assembly::riscv::OPCODE::FCVT_H_LU)
  .value("FCVT_H_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_LU_INX)
  .value("FCVT_H_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_L_INX)
  .value("FCVT_H_S", LIEF::assembly::riscv::OPCODE::FCVT_H_S)
  .value("FCVT_H_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_S_INX)
  .value("FCVT_H_W", LIEF::assembly::riscv::OPCODE::FCVT_H_W)
  .value("FCVT_H_WU", LIEF::assembly::riscv::OPCODE::FCVT_H_WU)
  .value("FCVT_H_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_WU_INX)
  .value("FCVT_H_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_W_INX)
  .value("FCVT_LU_D", LIEF::assembly::riscv::OPCODE::FCVT_LU_D)
  .value("FCVT_LU_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_D_INX)
  .value("FCVT_LU_H", LIEF::assembly::riscv::OPCODE::FCVT_LU_H)
  .value("FCVT_LU_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_H_INX)
  .value("FCVT_LU_S", LIEF::assembly::riscv::OPCODE::FCVT_LU_S)
  .value("FCVT_LU_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_S_INX)
  .value("FCVT_L_D", LIEF::assembly::riscv::OPCODE::FCVT_L_D)
  .value("FCVT_L_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_D_INX)
  .value("FCVT_L_H", LIEF::assembly::riscv::OPCODE::FCVT_L_H)
  .value("FCVT_L_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_H_INX)
  .value("FCVT_L_S", LIEF::assembly::riscv::OPCODE::FCVT_L_S)
  .value("FCVT_L_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_S_INX)
  .value("FCVT_S_BF16", LIEF::assembly::riscv::OPCODE::FCVT_S_BF16)
  .value("FCVT_S_D", LIEF::assembly::riscv::OPCODE::FCVT_S_D)
  .value("FCVT_S_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_S_D_IN32X)
  .value("FCVT_S_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_D_INX)
  .value("FCVT_S_H", LIEF::assembly::riscv::OPCODE::FCVT_S_H)
  .value("FCVT_S_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_H_INX)
  .value("FCVT_S_L", LIEF::assembly::riscv::OPCODE::FCVT_S_L)
  .value("FCVT_S_LU", LIEF::assembly::riscv::OPCODE::FCVT_S_LU)
  .value("FCVT_S_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_LU_INX);
  opcodes.value("FCVT_S_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_L_INX)
  .value("FCVT_S_W", LIEF::assembly::riscv::OPCODE::FCVT_S_W)
  .value("FCVT_S_WU", LIEF::assembly::riscv::OPCODE::FCVT_S_WU)
  .value("FCVT_S_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_WU_INX)
  .value("FCVT_S_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_W_INX)
  .value("FCVT_WU_D", LIEF::assembly::riscv::OPCODE::FCVT_WU_D)
  .value("FCVT_WU_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_WU_D_IN32X)
  .value("FCVT_WU_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_D_INX)
  .value("FCVT_WU_H", LIEF::assembly::riscv::OPCODE::FCVT_WU_H)
  .value("FCVT_WU_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_H_INX)
  .value("FCVT_WU_S", LIEF::assembly::riscv::OPCODE::FCVT_WU_S)
  .value("FCVT_WU_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_S_INX)
  .value("FCVT_W_D", LIEF::assembly::riscv::OPCODE::FCVT_W_D)
  .value("FCVT_W_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_W_D_IN32X)
  .value("FCVT_W_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_D_INX)
  .value("FCVT_W_H", LIEF::assembly::riscv::OPCODE::FCVT_W_H)
  .value("FCVT_W_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_H_INX)
  .value("FCVT_W_S", LIEF::assembly::riscv::OPCODE::FCVT_W_S)
  .value("FCVT_W_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_S_INX)
  .value("FDIV_D", LIEF::assembly::riscv::OPCODE::FDIV_D)
  .value("FDIV_D_IN32X", LIEF::assembly::riscv::OPCODE::FDIV_D_IN32X)
  .value("FDIV_D_INX", LIEF::assembly::riscv::OPCODE::FDIV_D_INX)
  .value("FDIV_H", LIEF::assembly::riscv::OPCODE::FDIV_H)
  .value("FDIV_H_INX", LIEF::assembly::riscv::OPCODE::FDIV_H_INX)
  .value("FDIV_S", LIEF::assembly::riscv::OPCODE::FDIV_S)
  .value("FDIV_S_INX", LIEF::assembly::riscv::OPCODE::FDIV_S_INX)
  .value("FENCE", LIEF::assembly::riscv::OPCODE::FENCE)
  .value("FENCE_I", LIEF::assembly::riscv::OPCODE::FENCE_I)
  .value("FENCE_TSO", LIEF::assembly::riscv::OPCODE::FENCE_TSO)
  .value("FEQ_D", LIEF::assembly::riscv::OPCODE::FEQ_D)
  .value("FEQ_D_IN32X", LIEF::assembly::riscv::OPCODE::FEQ_D_IN32X)
  .value("FEQ_D_INX", LIEF::assembly::riscv::OPCODE::FEQ_D_INX)
  .value("FEQ_H", LIEF::assembly::riscv::OPCODE::FEQ_H)
  .value("FEQ_H_INX", LIEF::assembly::riscv::OPCODE::FEQ_H_INX)
  .value("FEQ_S", LIEF::assembly::riscv::OPCODE::FEQ_S)
  .value("FEQ_S_INX", LIEF::assembly::riscv::OPCODE::FEQ_S_INX)
  .value("FLD", LIEF::assembly::riscv::OPCODE::FLD)
  .value("FLEQ_D", LIEF::assembly::riscv::OPCODE::FLEQ_D)
  .value("FLEQ_H", LIEF::assembly::riscv::OPCODE::FLEQ_H)
  .value("FLEQ_S", LIEF::assembly::riscv::OPCODE::FLEQ_S)
  .value("FLE_D", LIEF::assembly::riscv::OPCODE::FLE_D)
  .value("FLE_D_IN32X", LIEF::assembly::riscv::OPCODE::FLE_D_IN32X)
  .value("FLE_D_INX", LIEF::assembly::riscv::OPCODE::FLE_D_INX)
  .value("FLE_H", LIEF::assembly::riscv::OPCODE::FLE_H)
  .value("FLE_H_INX", LIEF::assembly::riscv::OPCODE::FLE_H_INX)
  .value("FLE_S", LIEF::assembly::riscv::OPCODE::FLE_S)
  .value("FLE_S_INX", LIEF::assembly::riscv::OPCODE::FLE_S_INX)
  .value("FLH", LIEF::assembly::riscv::OPCODE::FLH)
  .value("FLI_D", LIEF::assembly::riscv::OPCODE::FLI_D)
  .value("FLI_H", LIEF::assembly::riscv::OPCODE::FLI_H)
  .value("FLI_S", LIEF::assembly::riscv::OPCODE::FLI_S)
  .value("FLTQ_D", LIEF::assembly::riscv::OPCODE::FLTQ_D)
  .value("FLTQ_H", LIEF::assembly::riscv::OPCODE::FLTQ_H)
  .value("FLTQ_S", LIEF::assembly::riscv::OPCODE::FLTQ_S)
  .value("FLT_D", LIEF::assembly::riscv::OPCODE::FLT_D)
  .value("FLT_D_IN32X", LIEF::assembly::riscv::OPCODE::FLT_D_IN32X)
  .value("FLT_D_INX", LIEF::assembly::riscv::OPCODE::FLT_D_INX)
  .value("FLT_H", LIEF::assembly::riscv::OPCODE::FLT_H)
  .value("FLT_H_INX", LIEF::assembly::riscv::OPCODE::FLT_H_INX)
  .value("FLT_S", LIEF::assembly::riscv::OPCODE::FLT_S)
  .value("FLT_S_INX", LIEF::assembly::riscv::OPCODE::FLT_S_INX)
  .value("FLW", LIEF::assembly::riscv::OPCODE::FLW)
  .value("FMADD_D", LIEF::assembly::riscv::OPCODE::FMADD_D)
  .value("FMADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FMADD_D_IN32X)
  .value("FMADD_D_INX", LIEF::assembly::riscv::OPCODE::FMADD_D_INX)
  .value("FMADD_H", LIEF::assembly::riscv::OPCODE::FMADD_H)
  .value("FMADD_H_INX", LIEF::assembly::riscv::OPCODE::FMADD_H_INX)
  .value("FMADD_S", LIEF::assembly::riscv::OPCODE::FMADD_S)
  .value("FMADD_S_INX", LIEF::assembly::riscv::OPCODE::FMADD_S_INX)
  .value("FMAXM_D", LIEF::assembly::riscv::OPCODE::FMAXM_D)
  .value("FMAXM_H", LIEF::assembly::riscv::OPCODE::FMAXM_H)
  .value("FMAXM_S", LIEF::assembly::riscv::OPCODE::FMAXM_S)
  .value("FMAX_D", LIEF::assembly::riscv::OPCODE::FMAX_D)
  .value("FMAX_D_IN32X", LIEF::assembly::riscv::OPCODE::FMAX_D_IN32X)
  .value("FMAX_D_INX", LIEF::assembly::riscv::OPCODE::FMAX_D_INX)
  .value("FMAX_H", LIEF::assembly::riscv::OPCODE::FMAX_H)
  .value("FMAX_H_INX", LIEF::assembly::riscv::OPCODE::FMAX_H_INX)
  .value("FMAX_S", LIEF::assembly::riscv::OPCODE::FMAX_S)
  .value("FMAX_S_INX", LIEF::assembly::riscv::OPCODE::FMAX_S_INX)
  .value("FMINM_D", LIEF::assembly::riscv::OPCODE::FMINM_D)
  .value("FMINM_H", LIEF::assembly::riscv::OPCODE::FMINM_H)
  .value("FMINM_S", LIEF::assembly::riscv::OPCODE::FMINM_S)
  .value("FMIN_D", LIEF::assembly::riscv::OPCODE::FMIN_D)
  .value("FMIN_D_IN32X", LIEF::assembly::riscv::OPCODE::FMIN_D_IN32X)
  .value("FMIN_D_INX", LIEF::assembly::riscv::OPCODE::FMIN_D_INX)
  .value("FMIN_H", LIEF::assembly::riscv::OPCODE::FMIN_H)
  .value("FMIN_H_INX", LIEF::assembly::riscv::OPCODE::FMIN_H_INX)
  .value("FMIN_S", LIEF::assembly::riscv::OPCODE::FMIN_S)
  .value("FMIN_S_INX", LIEF::assembly::riscv::OPCODE::FMIN_S_INX)
  .value("FMSUB_D", LIEF::assembly::riscv::OPCODE::FMSUB_D)
  .value("FMSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FMSUB_D_IN32X)
  .value("FMSUB_D_INX", LIEF::assembly::riscv::OPCODE::FMSUB_D_INX)
  .value("FMSUB_H", LIEF::assembly::riscv::OPCODE::FMSUB_H)
  .value("FMSUB_H_INX", LIEF::assembly::riscv::OPCODE::FMSUB_H_INX)
  .value("FMSUB_S", LIEF::assembly::riscv::OPCODE::FMSUB_S)
  .value("FMSUB_S_INX", LIEF::assembly::riscv::OPCODE::FMSUB_S_INX)
  .value("FMUL_D", LIEF::assembly::riscv::OPCODE::FMUL_D)
  .value("FMUL_D_IN32X", LIEF::assembly::riscv::OPCODE::FMUL_D_IN32X)
  .value("FMUL_D_INX", LIEF::assembly::riscv::OPCODE::FMUL_D_INX)
  .value("FMUL_H", LIEF::assembly::riscv::OPCODE::FMUL_H)
  .value("FMUL_H_INX", LIEF::assembly::riscv::OPCODE::FMUL_H_INX)
  .value("FMUL_S", LIEF::assembly::riscv::OPCODE::FMUL_S)
  .value("FMUL_S_INX", LIEF::assembly::riscv::OPCODE::FMUL_S_INX)
  .value("FMVH_X_D", LIEF::assembly::riscv::OPCODE::FMVH_X_D)
  .value("FMVP_D_X", LIEF::assembly::riscv::OPCODE::FMVP_D_X)
  .value("FMV_D_X", LIEF::assembly::riscv::OPCODE::FMV_D_X)
  .value("FMV_H_X", LIEF::assembly::riscv::OPCODE::FMV_H_X)
  .value("FMV_W_X", LIEF::assembly::riscv::OPCODE::FMV_W_X)
  .value("FMV_X_D", LIEF::assembly::riscv::OPCODE::FMV_X_D)
  .value("FMV_X_H", LIEF::assembly::riscv::OPCODE::FMV_X_H)
  .value("FMV_X_W", LIEF::assembly::riscv::OPCODE::FMV_X_W)
  .value("FMV_X_W_FPR64", LIEF::assembly::riscv::OPCODE::FMV_X_W_FPR64)
  .value("FNMADD_D", LIEF::assembly::riscv::OPCODE::FNMADD_D)
  .value("FNMADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FNMADD_D_IN32X)
  .value("FNMADD_D_INX", LIEF::assembly::riscv::OPCODE::FNMADD_D_INX)
  .value("FNMADD_H", LIEF::assembly::riscv::OPCODE::FNMADD_H)
  .value("FNMADD_H_INX", LIEF::assembly::riscv::OPCODE::FNMADD_H_INX)
  .value("FNMADD_S", LIEF::assembly::riscv::OPCODE::FNMADD_S)
  .value("FNMADD_S_INX", LIEF::assembly::riscv::OPCODE::FNMADD_S_INX)
  .value("FNMSUB_D", LIEF::assembly::riscv::OPCODE::FNMSUB_D)
  .value("FNMSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FNMSUB_D_IN32X)
  .value("FNMSUB_D_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_D_INX)
  .value("FNMSUB_H", LIEF::assembly::riscv::OPCODE::FNMSUB_H)
  .value("FNMSUB_H_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_H_INX)
  .value("FNMSUB_S", LIEF::assembly::riscv::OPCODE::FNMSUB_S)
  .value("FNMSUB_S_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_S_INX)
  .value("FROUNDNX_D", LIEF::assembly::riscv::OPCODE::FROUNDNX_D)
  .value("FROUNDNX_H", LIEF::assembly::riscv::OPCODE::FROUNDNX_H)
  .value("FROUNDNX_S", LIEF::assembly::riscv::OPCODE::FROUNDNX_S)
  .value("FROUND_D", LIEF::assembly::riscv::OPCODE::FROUND_D)
  .value("FROUND_H", LIEF::assembly::riscv::OPCODE::FROUND_H)
  .value("FROUND_S", LIEF::assembly::riscv::OPCODE::FROUND_S)
  .value("FSD", LIEF::assembly::riscv::OPCODE::FSD)
  .value("FSGNJN_D", LIEF::assembly::riscv::OPCODE::FSGNJN_D)
  .value("FSGNJN_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJN_D_IN32X)
  .value("FSGNJN_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_D_INX)
  .value("FSGNJN_H", LIEF::assembly::riscv::OPCODE::FSGNJN_H)
  .value("FSGNJN_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_H_INX)
  .value("FSGNJN_S", LIEF::assembly::riscv::OPCODE::FSGNJN_S)
  .value("FSGNJN_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_S_INX)
  .value("FSGNJX_D", LIEF::assembly::riscv::OPCODE::FSGNJX_D)
  .value("FSGNJX_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJX_D_IN32X)
  .value("FSGNJX_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_D_INX)
  .value("FSGNJX_H", LIEF::assembly::riscv::OPCODE::FSGNJX_H)
  .value("FSGNJX_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_H_INX)
  .value("FSGNJX_S", LIEF::assembly::riscv::OPCODE::FSGNJX_S)
  .value("FSGNJX_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_S_INX)
  .value("FSGNJ_D", LIEF::assembly::riscv::OPCODE::FSGNJ_D)
  .value("FSGNJ_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJ_D_IN32X)
  .value("FSGNJ_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_D_INX)
  .value("FSGNJ_H", LIEF::assembly::riscv::OPCODE::FSGNJ_H)
  .value("FSGNJ_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_H_INX)
  .value("FSGNJ_S", LIEF::assembly::riscv::OPCODE::FSGNJ_S)
  .value("FSGNJ_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_S_INX)
  .value("FSH", LIEF::assembly::riscv::OPCODE::FSH)
  .value("FSQRT_D", LIEF::assembly::riscv::OPCODE::FSQRT_D)
  .value("FSQRT_D_IN32X", LIEF::assembly::riscv::OPCODE::FSQRT_D_IN32X)
  .value("FSQRT_D_INX", LIEF::assembly::riscv::OPCODE::FSQRT_D_INX)
  .value("FSQRT_H", LIEF::assembly::riscv::OPCODE::FSQRT_H)
  .value("FSQRT_H_INX", LIEF::assembly::riscv::OPCODE::FSQRT_H_INX)
  .value("FSQRT_S", LIEF::assembly::riscv::OPCODE::FSQRT_S)
  .value("FSQRT_S_INX", LIEF::assembly::riscv::OPCODE::FSQRT_S_INX)
  .value("FSUB_D", LIEF::assembly::riscv::OPCODE::FSUB_D)
  .value("FSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FSUB_D_IN32X)
  .value("FSUB_D_INX", LIEF::assembly::riscv::OPCODE::FSUB_D_INX)
  .value("FSUB_H", LIEF::assembly::riscv::OPCODE::FSUB_H)
  .value("FSUB_H_INX", LIEF::assembly::riscv::OPCODE::FSUB_H_INX)
  .value("FSUB_S", LIEF::assembly::riscv::OPCODE::FSUB_S)
  .value("FSUB_S_INX", LIEF::assembly::riscv::OPCODE::FSUB_S_INX)
  .value("FSW", LIEF::assembly::riscv::OPCODE::FSW)
  .value("HFENCE_GVMA", LIEF::assembly::riscv::OPCODE::HFENCE_GVMA)
  .value("HFENCE_VVMA", LIEF::assembly::riscv::OPCODE::HFENCE_VVMA)
  .value("HINVAL_GVMA", LIEF::assembly::riscv::OPCODE::HINVAL_GVMA)
  .value("HINVAL_VVMA", LIEF::assembly::riscv::OPCODE::HINVAL_VVMA)
  .value("HLVX_HU", LIEF::assembly::riscv::OPCODE::HLVX_HU)
  .value("HLVX_WU", LIEF::assembly::riscv::OPCODE::HLVX_WU)
  .value("HLV_B", LIEF::assembly::riscv::OPCODE::HLV_B)
  .value("HLV_BU", LIEF::assembly::riscv::OPCODE::HLV_BU)
  .value("HLV_D", LIEF::assembly::riscv::OPCODE::HLV_D)
  .value("HLV_H", LIEF::assembly::riscv::OPCODE::HLV_H)
  .value("HLV_HU", LIEF::assembly::riscv::OPCODE::HLV_HU)
  .value("HLV_W", LIEF::assembly::riscv::OPCODE::HLV_W)
  .value("HLV_WU", LIEF::assembly::riscv::OPCODE::HLV_WU)
  .value("HSV_B", LIEF::assembly::riscv::OPCODE::HSV_B)
  .value("HSV_D", LIEF::assembly::riscv::OPCODE::HSV_D)
  .value("HSV_H", LIEF::assembly::riscv::OPCODE::HSV_H)
  .value("HSV_W", LIEF::assembly::riscv::OPCODE::HSV_W)
  .value("Insn16", LIEF::assembly::riscv::OPCODE::Insn16)
  .value("Insn32", LIEF::assembly::riscv::OPCODE::Insn32)
  .value("InsnB", LIEF::assembly::riscv::OPCODE::InsnB)
  .value("InsnCA", LIEF::assembly::riscv::OPCODE::InsnCA)
  .value("InsnCB", LIEF::assembly::riscv::OPCODE::InsnCB)
  .value("InsnCI", LIEF::assembly::riscv::OPCODE::InsnCI)
  .value("InsnCIW", LIEF::assembly::riscv::OPCODE::InsnCIW)
  .value("InsnCJ", LIEF::assembly::riscv::OPCODE::InsnCJ)
  .value("InsnCL", LIEF::assembly::riscv::OPCODE::InsnCL)
  .value("InsnCR", LIEF::assembly::riscv::OPCODE::InsnCR)
  .value("InsnCS", LIEF::assembly::riscv::OPCODE::InsnCS)
  .value("InsnCSS", LIEF::assembly::riscv::OPCODE::InsnCSS)
  .value("InsnI", LIEF::assembly::riscv::OPCODE::InsnI)
  .value("InsnI_Mem", LIEF::assembly::riscv::OPCODE::InsnI_Mem)
  .value("InsnJ", LIEF::assembly::riscv::OPCODE::InsnJ)
  .value("InsnR", LIEF::assembly::riscv::OPCODE::InsnR)
  .value("InsnR4", LIEF::assembly::riscv::OPCODE::InsnR4)
  .value("InsnS", LIEF::assembly::riscv::OPCODE::InsnS)
  .value("InsnU", LIEF::assembly::riscv::OPCODE::InsnU)
  .value("JAL", LIEF::assembly::riscv::OPCODE::JAL)
  .value("JALR", LIEF::assembly::riscv::OPCODE::JALR)
  .value("LB", LIEF::assembly::riscv::OPCODE::LB)
  .value("LBU", LIEF::assembly::riscv::OPCODE::LBU)
  .value("LB_AQ", LIEF::assembly::riscv::OPCODE::LB_AQ)
  .value("LB_AQ_RL", LIEF::assembly::riscv::OPCODE::LB_AQ_RL)
  .value("LD", LIEF::assembly::riscv::OPCODE::LD)
  .value("LD_AQ", LIEF::assembly::riscv::OPCODE::LD_AQ)
  .value("LD_AQ_RL", LIEF::assembly::riscv::OPCODE::LD_AQ_RL)
  .value("LH", LIEF::assembly::riscv::OPCODE::LH)
  .value("LHU", LIEF::assembly::riscv::OPCODE::LHU)
  .value("LH_AQ", LIEF::assembly::riscv::OPCODE::LH_AQ)
  .value("LH_AQ_RL", LIEF::assembly::riscv::OPCODE::LH_AQ_RL)
  .value("LR_D", LIEF::assembly::riscv::OPCODE::LR_D)
  .value("LR_D_AQ", LIEF::assembly::riscv::OPCODE::LR_D_AQ)
  .value("LR_D_AQ_RL", LIEF::assembly::riscv::OPCODE::LR_D_AQ_RL)
  .value("LR_D_RL", LIEF::assembly::riscv::OPCODE::LR_D_RL)
  .value("LR_W", LIEF::assembly::riscv::OPCODE::LR_W)
  .value("LR_W_AQ", LIEF::assembly::riscv::OPCODE::LR_W_AQ)
  .value("LR_W_AQ_RL", LIEF::assembly::riscv::OPCODE::LR_W_AQ_RL)
  .value("LR_W_RL", LIEF::assembly::riscv::OPCODE::LR_W_RL)
  .value("LUI", LIEF::assembly::riscv::OPCODE::LUI)
  .value("LW", LIEF::assembly::riscv::OPCODE::LW)
  .value("LWU", LIEF::assembly::riscv::OPCODE::LWU)
  .value("LW_AQ", LIEF::assembly::riscv::OPCODE::LW_AQ)
  .value("LW_AQ_RL", LIEF::assembly::riscv::OPCODE::LW_AQ_RL)
  .value("MAX", LIEF::assembly::riscv::OPCODE::MAX)
  .value("MAXU", LIEF::assembly::riscv::OPCODE::MAXU)
  .value("MIN", LIEF::assembly::riscv::OPCODE::MIN)
  .value("MINU", LIEF::assembly::riscv::OPCODE::MINU)
  .value("MOPR0", LIEF::assembly::riscv::OPCODE::MOPR0)
  .value("MOPR1", LIEF::assembly::riscv::OPCODE::MOPR1)
  .value("MOPR10", LIEF::assembly::riscv::OPCODE::MOPR10)
  .value("MOPR11", LIEF::assembly::riscv::OPCODE::MOPR11)
  .value("MOPR12", LIEF::assembly::riscv::OPCODE::MOPR12)
  .value("MOPR13", LIEF::assembly::riscv::OPCODE::MOPR13)
  .value("MOPR14", LIEF::assembly::riscv::OPCODE::MOPR14)
  .value("MOPR15", LIEF::assembly::riscv::OPCODE::MOPR15)
  .value("MOPR16", LIEF::assembly::riscv::OPCODE::MOPR16)
  .value("MOPR17", LIEF::assembly::riscv::OPCODE::MOPR17)
  .value("MOPR18", LIEF::assembly::riscv::OPCODE::MOPR18)
  .value("MOPR19", LIEF::assembly::riscv::OPCODE::MOPR19)
  .value("MOPR2", LIEF::assembly::riscv::OPCODE::MOPR2)
  .value("MOPR20", LIEF::assembly::riscv::OPCODE::MOPR20)
  .value("MOPR21", LIEF::assembly::riscv::OPCODE::MOPR21)
  .value("MOPR22", LIEF::assembly::riscv::OPCODE::MOPR22)
  .value("MOPR23", LIEF::assembly::riscv::OPCODE::MOPR23)
  .value("MOPR24", LIEF::assembly::riscv::OPCODE::MOPR24)
  .value("MOPR25", LIEF::assembly::riscv::OPCODE::MOPR25)
  .value("MOPR26", LIEF::assembly::riscv::OPCODE::MOPR26)
  .value("MOPR27", LIEF::assembly::riscv::OPCODE::MOPR27)
  .value("MOPR28", LIEF::assembly::riscv::OPCODE::MOPR28)
  .value("MOPR29", LIEF::assembly::riscv::OPCODE::MOPR29)
  .value("MOPR3", LIEF::assembly::riscv::OPCODE::MOPR3)
  .value("MOPR30", LIEF::assembly::riscv::OPCODE::MOPR30)
  .value("MOPR31", LIEF::assembly::riscv::OPCODE::MOPR31)
  .value("MOPR4", LIEF::assembly::riscv::OPCODE::MOPR4)
  .value("MOPR5", LIEF::assembly::riscv::OPCODE::MOPR5)
  .value("MOPR6", LIEF::assembly::riscv::OPCODE::MOPR6)
  .value("MOPR7", LIEF::assembly::riscv::OPCODE::MOPR7)
  .value("MOPR8", LIEF::assembly::riscv::OPCODE::MOPR8)
  .value("MOPR9", LIEF::assembly::riscv::OPCODE::MOPR9)
  .value("MOPRR0", LIEF::assembly::riscv::OPCODE::MOPRR0)
  .value("MOPRR1", LIEF::assembly::riscv::OPCODE::MOPRR1)
  .value("MOPRR2", LIEF::assembly::riscv::OPCODE::MOPRR2)
  .value("MOPRR3", LIEF::assembly::riscv::OPCODE::MOPRR3)
  .value("MOPRR4", LIEF::assembly::riscv::OPCODE::MOPRR4)
  .value("MOPRR5", LIEF::assembly::riscv::OPCODE::MOPRR5)
  .value("MOPRR6", LIEF::assembly::riscv::OPCODE::MOPRR6)
  .value("MOPRR7", LIEF::assembly::riscv::OPCODE::MOPRR7)
  .value("MRET", LIEF::assembly::riscv::OPCODE::MRET)
  .value("MUL", LIEF::assembly::riscv::OPCODE::MUL)
  .value("MULH", LIEF::assembly::riscv::OPCODE::MULH)
  .value("MULHSU", LIEF::assembly::riscv::OPCODE::MULHSU)
  .value("MULHU", LIEF::assembly::riscv::OPCODE::MULHU)
  .value("MULW", LIEF::assembly::riscv::OPCODE::MULW)
  .value("OR", LIEF::assembly::riscv::OPCODE::OR)
  .value("ORC_B", LIEF::assembly::riscv::OPCODE::ORC_B)
  .value("ORI", LIEF::assembly::riscv::OPCODE::ORI)
  .value("ORN", LIEF::assembly::riscv::OPCODE::ORN)
  .value("PACK", LIEF::assembly::riscv::OPCODE::PACK)
  .value("PACKH", LIEF::assembly::riscv::OPCODE::PACKH)
  .value("PACKW", LIEF::assembly::riscv::OPCODE::PACKW)
  .value("PREFETCH_I", LIEF::assembly::riscv::OPCODE::PREFETCH_I)
  .value("PREFETCH_R", LIEF::assembly::riscv::OPCODE::PREFETCH_R)
  .value("PREFETCH_W", LIEF::assembly::riscv::OPCODE::PREFETCH_W)
  .value("QK_C_LBU", LIEF::assembly::riscv::OPCODE::QK_C_LBU)
  .value("QK_C_LBUSP", LIEF::assembly::riscv::OPCODE::QK_C_LBUSP)
  .value("QK_C_LHU", LIEF::assembly::riscv::OPCODE::QK_C_LHU)
  .value("QK_C_LHUSP", LIEF::assembly::riscv::OPCODE::QK_C_LHUSP)
  .value("QK_C_SB", LIEF::assembly::riscv::OPCODE::QK_C_SB)
  .value("QK_C_SBSP", LIEF::assembly::riscv::OPCODE::QK_C_SBSP)
  .value("QK_C_SH", LIEF::assembly::riscv::OPCODE::QK_C_SH)
  .value("QK_C_SHSP", LIEF::assembly::riscv::OPCODE::QK_C_SHSP);
  opcodes.value("REM", LIEF::assembly::riscv::OPCODE::REM)
  .value("REMU", LIEF::assembly::riscv::OPCODE::REMU)
  .value("REMUW", LIEF::assembly::riscv::OPCODE::REMUW)
  .value("REMW", LIEF::assembly::riscv::OPCODE::REMW)
  .value("REV8_RV32", LIEF::assembly::riscv::OPCODE::REV8_RV32)
  .value("REV8_RV64", LIEF::assembly::riscv::OPCODE::REV8_RV64)
  .value("ROL", LIEF::assembly::riscv::OPCODE::ROL)
  .value("ROLW", LIEF::assembly::riscv::OPCODE::ROLW)
  .value("ROR", LIEF::assembly::riscv::OPCODE::ROR)
  .value("RORI", LIEF::assembly::riscv::OPCODE::RORI)
  .value("RORIW", LIEF::assembly::riscv::OPCODE::RORIW)
  .value("RORW", LIEF::assembly::riscv::OPCODE::RORW)
  .value("SB", LIEF::assembly::riscv::OPCODE::SB)
  .value("SB_AQ_RL", LIEF::assembly::riscv::OPCODE::SB_AQ_RL)
  .value("SB_RL", LIEF::assembly::riscv::OPCODE::SB_RL)
  .value("SC_D", LIEF::assembly::riscv::OPCODE::SC_D)
  .value("SC_D_AQ", LIEF::assembly::riscv::OPCODE::SC_D_AQ)
  .value("SC_D_AQ_RL", LIEF::assembly::riscv::OPCODE::SC_D_AQ_RL)
  .value("SC_D_RL", LIEF::assembly::riscv::OPCODE::SC_D_RL)
  .value("SC_W", LIEF::assembly::riscv::OPCODE::SC_W)
  .value("SC_W_AQ", LIEF::assembly::riscv::OPCODE::SC_W_AQ)
  .value("SC_W_AQ_RL", LIEF::assembly::riscv::OPCODE::SC_W_AQ_RL)
  .value("SC_W_RL", LIEF::assembly::riscv::OPCODE::SC_W_RL)
  .value("SD", LIEF::assembly::riscv::OPCODE::SD)
  .value("SD_AQ_RL", LIEF::assembly::riscv::OPCODE::SD_AQ_RL)
  .value("SD_RL", LIEF::assembly::riscv::OPCODE::SD_RL)
  .value("SEXT_B", LIEF::assembly::riscv::OPCODE::SEXT_B)
  .value("SEXT_H", LIEF::assembly::riscv::OPCODE::SEXT_H)
  .value("SFENCE_INVAL_IR", LIEF::assembly::riscv::OPCODE::SFENCE_INVAL_IR)
  .value("SFENCE_VMA", LIEF::assembly::riscv::OPCODE::SFENCE_VMA)
  .value("SFENCE_W_INVAL", LIEF::assembly::riscv::OPCODE::SFENCE_W_INVAL)
  .value("SF_CDISCARD_D_L1", LIEF::assembly::riscv::OPCODE::SF_CDISCARD_D_L1)
  .value("SF_CEASE", LIEF::assembly::riscv::OPCODE::SF_CEASE)
  .value("SF_CFLUSH_D_L1", LIEF::assembly::riscv::OPCODE::SF_CFLUSH_D_L1)
  .value("SH", LIEF::assembly::riscv::OPCODE::SH)
  .value("SH1ADD", LIEF::assembly::riscv::OPCODE::SH1ADD)
  .value("SH1ADD_UW", LIEF::assembly::riscv::OPCODE::SH1ADD_UW)
  .value("SH2ADD", LIEF::assembly::riscv::OPCODE::SH2ADD)
  .value("SH2ADD_UW", LIEF::assembly::riscv::OPCODE::SH2ADD_UW)
  .value("SH3ADD", LIEF::assembly::riscv::OPCODE::SH3ADD)
  .value("SH3ADD_UW", LIEF::assembly::riscv::OPCODE::SH3ADD_UW)
  .value("SHA256SIG0", LIEF::assembly::riscv::OPCODE::SHA256SIG0)
  .value("SHA256SIG1", LIEF::assembly::riscv::OPCODE::SHA256SIG1)
  .value("SHA256SUM0", LIEF::assembly::riscv::OPCODE::SHA256SUM0)
  .value("SHA256SUM1", LIEF::assembly::riscv::OPCODE::SHA256SUM1)
  .value("SHA512SIG0", LIEF::assembly::riscv::OPCODE::SHA512SIG0)
  .value("SHA512SIG0H", LIEF::assembly::riscv::OPCODE::SHA512SIG0H)
  .value("SHA512SIG0L", LIEF::assembly::riscv::OPCODE::SHA512SIG0L)
  .value("SHA512SIG1", LIEF::assembly::riscv::OPCODE::SHA512SIG1)
  .value("SHA512SIG1H", LIEF::assembly::riscv::OPCODE::SHA512SIG1H)
  .value("SHA512SIG1L", LIEF::assembly::riscv::OPCODE::SHA512SIG1L)
  .value("SHA512SUM0", LIEF::assembly::riscv::OPCODE::SHA512SUM0)
  .value("SHA512SUM0R", LIEF::assembly::riscv::OPCODE::SHA512SUM0R)
  .value("SHA512SUM1", LIEF::assembly::riscv::OPCODE::SHA512SUM1)
  .value("SHA512SUM1R", LIEF::assembly::riscv::OPCODE::SHA512SUM1R)
  .value("SH_AQ_RL", LIEF::assembly::riscv::OPCODE::SH_AQ_RL)
  .value("SH_RL", LIEF::assembly::riscv::OPCODE::SH_RL)
  .value("SINVAL_VMA", LIEF::assembly::riscv::OPCODE::SINVAL_VMA)
  .value("SLL", LIEF::assembly::riscv::OPCODE::SLL)
  .value("SLLI", LIEF::assembly::riscv::OPCODE::SLLI)
  .value("SLLIW", LIEF::assembly::riscv::OPCODE::SLLIW)
  .value("SLLI_UW", LIEF::assembly::riscv::OPCODE::SLLI_UW)
  .value("SLLW", LIEF::assembly::riscv::OPCODE::SLLW)
  .value("SLT", LIEF::assembly::riscv::OPCODE::SLT)
  .value("SLTI", LIEF::assembly::riscv::OPCODE::SLTI)
  .value("SLTIU", LIEF::assembly::riscv::OPCODE::SLTIU)
  .value("SLTU", LIEF::assembly::riscv::OPCODE::SLTU)
  .value("SM3P0", LIEF::assembly::riscv::OPCODE::SM3P0)
  .value("SM3P1", LIEF::assembly::riscv::OPCODE::SM3P1)
  .value("SM4ED", LIEF::assembly::riscv::OPCODE::SM4ED)
  .value("SM4KS", LIEF::assembly::riscv::OPCODE::SM4KS)
  .value("SRA", LIEF::assembly::riscv::OPCODE::SRA)
  .value("SRAI", LIEF::assembly::riscv::OPCODE::SRAI)
  .value("SRAIW", LIEF::assembly::riscv::OPCODE::SRAIW)
  .value("SRAW", LIEF::assembly::riscv::OPCODE::SRAW)
  .value("SRET", LIEF::assembly::riscv::OPCODE::SRET)
  .value("SRL", LIEF::assembly::riscv::OPCODE::SRL)
  .value("SRLI", LIEF::assembly::riscv::OPCODE::SRLI)
  .value("SRLIW", LIEF::assembly::riscv::OPCODE::SRLIW)
  .value("SRLW", LIEF::assembly::riscv::OPCODE::SRLW)
  .value("SSAMOSWAP_D", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D)
  .value("SSAMOSWAP_D_AQ", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQ)
  .value("SSAMOSWAP_D_AQ_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQ_RL)
  .value("SSAMOSWAP_D_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_RL)
  .value("SSAMOSWAP_W", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W)
  .value("SSAMOSWAP_W_AQ", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQ)
  .value("SSAMOSWAP_W_AQ_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQ_RL)
  .value("SSAMOSWAP_W_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_RL)
  .value("SSPOPCHK", LIEF::assembly::riscv::OPCODE::SSPOPCHK)
  .value("SSPUSH", LIEF::assembly::riscv::OPCODE::SSPUSH)
  .value("SSRDP", LIEF::assembly::riscv::OPCODE::SSRDP)
  .value("SUB", LIEF::assembly::riscv::OPCODE::SUB)
  .value("SUBW", LIEF::assembly::riscv::OPCODE::SUBW)
  .value("SW", LIEF::assembly::riscv::OPCODE::SW)
  .value("SW_AQ_RL", LIEF::assembly::riscv::OPCODE::SW_AQ_RL)
  .value("SW_RL", LIEF::assembly::riscv::OPCODE::SW_RL)
  .value("THVdotVMAQASU_VV", LIEF::assembly::riscv::OPCODE::THVdotVMAQASU_VV)
  .value("THVdotVMAQASU_VX", LIEF::assembly::riscv::OPCODE::THVdotVMAQASU_VX)
  .value("THVdotVMAQAUS_VX", LIEF::assembly::riscv::OPCODE::THVdotVMAQAUS_VX)
  .value("THVdotVMAQAU_VV", LIEF::assembly::riscv::OPCODE::THVdotVMAQAU_VV)
  .value("THVdotVMAQAU_VX", LIEF::assembly::riscv::OPCODE::THVdotVMAQAU_VX)
  .value("THVdotVMAQA_VV", LIEF::assembly::riscv::OPCODE::THVdotVMAQA_VV)
  .value("THVdotVMAQA_VX", LIEF::assembly::riscv::OPCODE::THVdotVMAQA_VX)
  .value("TH_ADDSL", LIEF::assembly::riscv::OPCODE::TH_ADDSL)
  .value("TH_DCACHE_CALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CALL)
  .value("TH_DCACHE_CIALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIALL)
  .value("TH_DCACHE_CIPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIPA)
  .value("TH_DCACHE_CISW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CISW)
  .value("TH_DCACHE_CIVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIVA)
  .value("TH_DCACHE_CPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPA)
  .value("TH_DCACHE_CPAL1", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPAL1)
  .value("TH_DCACHE_CSW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CSW)
  .value("TH_DCACHE_CVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVA)
  .value("TH_DCACHE_CVAL1", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVAL1)
  .value("TH_DCACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IALL)
  .value("TH_DCACHE_IPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IPA)
  .value("TH_DCACHE_ISW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_ISW)
  .value("TH_DCACHE_IVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IVA)
  .value("TH_EXT", LIEF::assembly::riscv::OPCODE::TH_EXT)
  .value("TH_EXTU", LIEF::assembly::riscv::OPCODE::TH_EXTU)
  .value("TH_FF0", LIEF::assembly::riscv::OPCODE::TH_FF0)
  .value("TH_FF1", LIEF::assembly::riscv::OPCODE::TH_FF1)
  .value("TH_FLRD", LIEF::assembly::riscv::OPCODE::TH_FLRD)
  .value("TH_FLRW", LIEF::assembly::riscv::OPCODE::TH_FLRW)
  .value("TH_FLURD", LIEF::assembly::riscv::OPCODE::TH_FLURD)
  .value("TH_FLURW", LIEF::assembly::riscv::OPCODE::TH_FLURW)
  .value("TH_FSRD", LIEF::assembly::riscv::OPCODE::TH_FSRD)
  .value("TH_FSRW", LIEF::assembly::riscv::OPCODE::TH_FSRW)
  .value("TH_FSURD", LIEF::assembly::riscv::OPCODE::TH_FSURD)
  .value("TH_FSURW", LIEF::assembly::riscv::OPCODE::TH_FSURW)
  .value("TH_ICACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALL)
  .value("TH_ICACHE_IALLS", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALLS)
  .value("TH_ICACHE_IPA", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IPA)
  .value("TH_ICACHE_IVA", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IVA)
  .value("TH_L2CACHE_CALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CALL)
  .value("TH_L2CACHE_CIALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CIALL)
  .value("TH_L2CACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_IALL)
  .value("TH_LBIA", LIEF::assembly::riscv::OPCODE::TH_LBIA)
  .value("TH_LBIB", LIEF::assembly::riscv::OPCODE::TH_LBIB)
  .value("TH_LBUIA", LIEF::assembly::riscv::OPCODE::TH_LBUIA)
  .value("TH_LBUIB", LIEF::assembly::riscv::OPCODE::TH_LBUIB)
  .value("TH_LDD", LIEF::assembly::riscv::OPCODE::TH_LDD)
  .value("TH_LDIA", LIEF::assembly::riscv::OPCODE::TH_LDIA)
  .value("TH_LDIB", LIEF::assembly::riscv::OPCODE::TH_LDIB)
  .value("TH_LHIA", LIEF::assembly::riscv::OPCODE::TH_LHIA)
  .value("TH_LHIB", LIEF::assembly::riscv::OPCODE::TH_LHIB)
  .value("TH_LHUIA", LIEF::assembly::riscv::OPCODE::TH_LHUIA)
  .value("TH_LHUIB", LIEF::assembly::riscv::OPCODE::TH_LHUIB)
  .value("TH_LRB", LIEF::assembly::riscv::OPCODE::TH_LRB)
  .value("TH_LRBU", LIEF::assembly::riscv::OPCODE::TH_LRBU)
  .value("TH_LRD", LIEF::assembly::riscv::OPCODE::TH_LRD)
  .value("TH_LRH", LIEF::assembly::riscv::OPCODE::TH_LRH)
  .value("TH_LRHU", LIEF::assembly::riscv::OPCODE::TH_LRHU)
  .value("TH_LRW", LIEF::assembly::riscv::OPCODE::TH_LRW)
  .value("TH_LRWU", LIEF::assembly::riscv::OPCODE::TH_LRWU)
  .value("TH_LURB", LIEF::assembly::riscv::OPCODE::TH_LURB)
  .value("TH_LURBU", LIEF::assembly::riscv::OPCODE::TH_LURBU)
  .value("TH_LURD", LIEF::assembly::riscv::OPCODE::TH_LURD)
  .value("TH_LURH", LIEF::assembly::riscv::OPCODE::TH_LURH)
  .value("TH_LURHU", LIEF::assembly::riscv::OPCODE::TH_LURHU)
  .value("TH_LURW", LIEF::assembly::riscv::OPCODE::TH_LURW)
  .value("TH_LURWU", LIEF::assembly::riscv::OPCODE::TH_LURWU)
  .value("TH_LWD", LIEF::assembly::riscv::OPCODE::TH_LWD)
  .value("TH_LWIA", LIEF::assembly::riscv::OPCODE::TH_LWIA)
  .value("TH_LWIB", LIEF::assembly::riscv::OPCODE::TH_LWIB)
  .value("TH_LWUD", LIEF::assembly::riscv::OPCODE::TH_LWUD)
  .value("TH_LWUIA", LIEF::assembly::riscv::OPCODE::TH_LWUIA)
  .value("TH_LWUIB", LIEF::assembly::riscv::OPCODE::TH_LWUIB)
  .value("TH_MULA", LIEF::assembly::riscv::OPCODE::TH_MULA)
  .value("TH_MULAH", LIEF::assembly::riscv::OPCODE::TH_MULAH)
  .value("TH_MULAW", LIEF::assembly::riscv::OPCODE::TH_MULAW)
  .value("TH_MULS", LIEF::assembly::riscv::OPCODE::TH_MULS)
  .value("TH_MULSH", LIEF::assembly::riscv::OPCODE::TH_MULSH)
  .value("TH_MULSW", LIEF::assembly::riscv::OPCODE::TH_MULSW)
  .value("TH_MVEQZ", LIEF::assembly::riscv::OPCODE::TH_MVEQZ)
  .value("TH_MVNEZ", LIEF::assembly::riscv::OPCODE::TH_MVNEZ)
  .value("TH_REV", LIEF::assembly::riscv::OPCODE::TH_REV)
  .value("TH_REVW", LIEF::assembly::riscv::OPCODE::TH_REVW)
  .value("TH_SBIA", LIEF::assembly::riscv::OPCODE::TH_SBIA)
  .value("TH_SBIB", LIEF::assembly::riscv::OPCODE::TH_SBIB)
  .value("TH_SDD", LIEF::assembly::riscv::OPCODE::TH_SDD)
  .value("TH_SDIA", LIEF::assembly::riscv::OPCODE::TH_SDIA)
  .value("TH_SDIB", LIEF::assembly::riscv::OPCODE::TH_SDIB)
  .value("TH_SFENCE_VMAS", LIEF::assembly::riscv::OPCODE::TH_SFENCE_VMAS)
  .value("TH_SHIA", LIEF::assembly::riscv::OPCODE::TH_SHIA)
  .value("TH_SHIB", LIEF::assembly::riscv::OPCODE::TH_SHIB)
  .value("TH_SRB", LIEF::assembly::riscv::OPCODE::TH_SRB)
  .value("TH_SRD", LIEF::assembly::riscv::OPCODE::TH_SRD)
  .value("TH_SRH", LIEF::assembly::riscv::OPCODE::TH_SRH)
  .value("TH_SRRI", LIEF::assembly::riscv::OPCODE::TH_SRRI)
  .value("TH_SRRIW", LIEF::assembly::riscv::OPCODE::TH_SRRIW)
  .value("TH_SRW", LIEF::assembly::riscv::OPCODE::TH_SRW)
  .value("TH_SURB", LIEF::assembly::riscv::OPCODE::TH_SURB)
  .value("TH_SURD", LIEF::assembly::riscv::OPCODE::TH_SURD)
  .value("TH_SURH", LIEF::assembly::riscv::OPCODE::TH_SURH)
  .value("TH_SURW", LIEF::assembly::riscv::OPCODE::TH_SURW)
  .value("TH_SWD", LIEF::assembly::riscv::OPCODE::TH_SWD)
  .value("TH_SWIA", LIEF::assembly::riscv::OPCODE::TH_SWIA)
  .value("TH_SWIB", LIEF::assembly::riscv::OPCODE::TH_SWIB)
  .value("TH_SYNC", LIEF::assembly::riscv::OPCODE::TH_SYNC)
  .value("TH_SYNC_I", LIEF::assembly::riscv::OPCODE::TH_SYNC_I)
  .value("TH_SYNC_IS", LIEF::assembly::riscv::OPCODE::TH_SYNC_IS)
  .value("TH_SYNC_S", LIEF::assembly::riscv::OPCODE::TH_SYNC_S)
  .value("TH_TST", LIEF::assembly::riscv::OPCODE::TH_TST)
  .value("TH_TSTNBZ", LIEF::assembly::riscv::OPCODE::TH_TSTNBZ)
  .value("UNIMP", LIEF::assembly::riscv::OPCODE::UNIMP)
  .value("UNZIP_RV32", LIEF::assembly::riscv::OPCODE::UNZIP_RV32)
  .value("VAADDU_VV", LIEF::assembly::riscv::OPCODE::VAADDU_VV)
  .value("VAADDU_VX", LIEF::assembly::riscv::OPCODE::VAADDU_VX)
  .value("VAADD_VV", LIEF::assembly::riscv::OPCODE::VAADD_VV)
  .value("VAADD_VX", LIEF::assembly::riscv::OPCODE::VAADD_VX)
  .value("VADC_VIM", LIEF::assembly::riscv::OPCODE::VADC_VIM)
  .value("VADC_VVM", LIEF::assembly::riscv::OPCODE::VADC_VVM)
  .value("VADC_VXM", LIEF::assembly::riscv::OPCODE::VADC_VXM)
  .value("VADD_VI", LIEF::assembly::riscv::OPCODE::VADD_VI)
  .value("VADD_VV", LIEF::assembly::riscv::OPCODE::VADD_VV)
  .value("VADD_VX", LIEF::assembly::riscv::OPCODE::VADD_VX)
  .value("VAESDF_VS", LIEF::assembly::riscv::OPCODE::VAESDF_VS)
  .value("VAESDF_VV", LIEF::assembly::riscv::OPCODE::VAESDF_VV)
  .value("VAESDM_VS", LIEF::assembly::riscv::OPCODE::VAESDM_VS)
  .value("VAESDM_VV", LIEF::assembly::riscv::OPCODE::VAESDM_VV)
  .value("VAESEF_VS", LIEF::assembly::riscv::OPCODE::VAESEF_VS)
  .value("VAESEF_VV", LIEF::assembly::riscv::OPCODE::VAESEF_VV)
  .value("VAESEM_VS", LIEF::assembly::riscv::OPCODE::VAESEM_VS)
  .value("VAESEM_VV", LIEF::assembly::riscv::OPCODE::VAESEM_VV)
  .value("VAESKF1_VI", LIEF::assembly::riscv::OPCODE::VAESKF1_VI)
  .value("VAESKF2_VI", LIEF::assembly::riscv::OPCODE::VAESKF2_VI)
  .value("VAESZ_VS", LIEF::assembly::riscv::OPCODE::VAESZ_VS)
  .value("VANDN_VV", LIEF::assembly::riscv::OPCODE::VANDN_VV)
  .value("VANDN_VX", LIEF::assembly::riscv::OPCODE::VANDN_VX)
  .value("VAND_VI", LIEF::assembly::riscv::OPCODE::VAND_VI)
  .value("VAND_VV", LIEF::assembly::riscv::OPCODE::VAND_VV)
  .value("VAND_VX", LIEF::assembly::riscv::OPCODE::VAND_VX)
  .value("VASUBU_VV", LIEF::assembly::riscv::OPCODE::VASUBU_VV)
  .value("VASUBU_VX", LIEF::assembly::riscv::OPCODE::VASUBU_VX)
  .value("VASUB_VV", LIEF::assembly::riscv::OPCODE::VASUB_VV)
  .value("VASUB_VX", LIEF::assembly::riscv::OPCODE::VASUB_VX)
  .value("VBREV8_V", LIEF::assembly::riscv::OPCODE::VBREV8_V)
  .value("VBREV_V", LIEF::assembly::riscv::OPCODE::VBREV_V)
  .value("VCLMULH_VV", LIEF::assembly::riscv::OPCODE::VCLMULH_VV)
  .value("VCLMULH_VX", LIEF::assembly::riscv::OPCODE::VCLMULH_VX)
  .value("VCLMUL_VV", LIEF::assembly::riscv::OPCODE::VCLMUL_VV)
  .value("VCLMUL_VX", LIEF::assembly::riscv::OPCODE::VCLMUL_VX)
  .value("VCLZ_V", LIEF::assembly::riscv::OPCODE::VCLZ_V)
  .value("VCOMPRESS_VM", LIEF::assembly::riscv::OPCODE::VCOMPRESS_VM)
  .value("VCPOP_M", LIEF::assembly::riscv::OPCODE::VCPOP_M)
  .value("VCPOP_V", LIEF::assembly::riscv::OPCODE::VCPOP_V)
  .value("VCTZ_V", LIEF::assembly::riscv::OPCODE::VCTZ_V)
  .value("VC_FV", LIEF::assembly::riscv::OPCODE::VC_FV)
  .value("VC_FVV", LIEF::assembly::riscv::OPCODE::VC_FVV)
  .value("VC_FVW", LIEF::assembly::riscv::OPCODE::VC_FVW)
  .value("VC_I", LIEF::assembly::riscv::OPCODE::VC_I)
  .value("VC_IV", LIEF::assembly::riscv::OPCODE::VC_IV)
  .value("VC_IVV", LIEF::assembly::riscv::OPCODE::VC_IVV)
  .value("VC_IVW", LIEF::assembly::riscv::OPCODE::VC_IVW)
  .value("VC_VV", LIEF::assembly::riscv::OPCODE::VC_VV)
  .value("VC_VVV", LIEF::assembly::riscv::OPCODE::VC_VVV)
  .value("VC_VVW", LIEF::assembly::riscv::OPCODE::VC_VVW)
  .value("VC_V_FV", LIEF::assembly::riscv::OPCODE::VC_V_FV)
  .value("VC_V_FVV", LIEF::assembly::riscv::OPCODE::VC_V_FVV)
  .value("VC_V_FVW", LIEF::assembly::riscv::OPCODE::VC_V_FVW)
  .value("VC_V_I", LIEF::assembly::riscv::OPCODE::VC_V_I)
  .value("VC_V_IV", LIEF::assembly::riscv::OPCODE::VC_V_IV)
  .value("VC_V_IVV", LIEF::assembly::riscv::OPCODE::VC_V_IVV)
  .value("VC_V_IVW", LIEF::assembly::riscv::OPCODE::VC_V_IVW)
  .value("VC_V_VV", LIEF::assembly::riscv::OPCODE::VC_V_VV)
  .value("VC_V_VVV", LIEF::assembly::riscv::OPCODE::VC_V_VVV)
  .value("VC_V_VVW", LIEF::assembly::riscv::OPCODE::VC_V_VVW)
  .value("VC_V_X", LIEF::assembly::riscv::OPCODE::VC_V_X)
  .value("VC_V_XV", LIEF::assembly::riscv::OPCODE::VC_V_XV)
  .value("VC_V_XVV", LIEF::assembly::riscv::OPCODE::VC_V_XVV)
  .value("VC_V_XVW", LIEF::assembly::riscv::OPCODE::VC_V_XVW)
  .value("VC_X", LIEF::assembly::riscv::OPCODE::VC_X)
  .value("VC_XV", LIEF::assembly::riscv::OPCODE::VC_XV)
  .value("VC_XVV", LIEF::assembly::riscv::OPCODE::VC_XVV)
  .value("VC_XVW", LIEF::assembly::riscv::OPCODE::VC_XVW)
  .value("VDIVU_VV", LIEF::assembly::riscv::OPCODE::VDIVU_VV)
  .value("VDIVU_VX", LIEF::assembly::riscv::OPCODE::VDIVU_VX)
  .value("VDIV_VV", LIEF::assembly::riscv::OPCODE::VDIV_VV)
  .value("VDIV_VX", LIEF::assembly::riscv::OPCODE::VDIV_VX)
  .value("VFADD_VF", LIEF::assembly::riscv::OPCODE::VFADD_VF)
  .value("VFADD_VV", LIEF::assembly::riscv::OPCODE::VFADD_VV)
  .value("VFCLASS_V", LIEF::assembly::riscv::OPCODE::VFCLASS_V)
  .value("VFCVT_F_XU_V", LIEF::assembly::riscv::OPCODE::VFCVT_F_XU_V)
  .value("VFCVT_F_X_V", LIEF::assembly::riscv::OPCODE::VFCVT_F_X_V)
  .value("VFCVT_RTZ_XU_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_XU_F_V)
  .value("VFCVT_RTZ_X_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_X_F_V)
  .value("VFCVT_XU_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_XU_F_V)
  .value("VFCVT_X_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_X_F_V)
  .value("VFDIV_VF", LIEF::assembly::riscv::OPCODE::VFDIV_VF)
  .value("VFDIV_VV", LIEF::assembly::riscv::OPCODE::VFDIV_VV)
  .value("VFIRST_M", LIEF::assembly::riscv::OPCODE::VFIRST_M)
  .value("VFMACC_VF", LIEF::assembly::riscv::OPCODE::VFMACC_VF)
  .value("VFMACC_VV", LIEF::assembly::riscv::OPCODE::VFMACC_VV)
  .value("VFMADD_VF", LIEF::assembly::riscv::OPCODE::VFMADD_VF)
  .value("VFMADD_VV", LIEF::assembly::riscv::OPCODE::VFMADD_VV)
  .value("VFMAX_VF", LIEF::assembly::riscv::OPCODE::VFMAX_VF)
  .value("VFMAX_VV", LIEF::assembly::riscv::OPCODE::VFMAX_VV)
  .value("VFMERGE_VFM", LIEF::assembly::riscv::OPCODE::VFMERGE_VFM)
  .value("VFMIN_VF", LIEF::assembly::riscv::OPCODE::VFMIN_VF);
  opcodes.value("VFMIN_VV", LIEF::assembly::riscv::OPCODE::VFMIN_VV)
  .value("VFMSAC_VF", LIEF::assembly::riscv::OPCODE::VFMSAC_VF)
  .value("VFMSAC_VV", LIEF::assembly::riscv::OPCODE::VFMSAC_VV)
  .value("VFMSUB_VF", LIEF::assembly::riscv::OPCODE::VFMSUB_VF)
  .value("VFMSUB_VV", LIEF::assembly::riscv::OPCODE::VFMSUB_VV)
  .value("VFMUL_VF", LIEF::assembly::riscv::OPCODE::VFMUL_VF)
  .value("VFMUL_VV", LIEF::assembly::riscv::OPCODE::VFMUL_VV)
  .value("VFMV_F_S", LIEF::assembly::riscv::OPCODE::VFMV_F_S)
  .value("VFMV_S_F", LIEF::assembly::riscv::OPCODE::VFMV_S_F)
  .value("VFMV_V_F", LIEF::assembly::riscv::OPCODE::VFMV_V_F)
  .value("VFNCVTBF16_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVTBF16_F_F_W)
  .value("VFNCVT_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_F_W)
  .value("VFNCVT_F_XU_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_XU_W)
  .value("VFNCVT_F_X_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_X_W)
  .value("VFNCVT_ROD_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_ROD_F_F_W)
  .value("VFNCVT_RTZ_XU_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_XU_F_W)
  .value("VFNCVT_RTZ_X_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_X_F_W)
  .value("VFNCVT_XU_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_XU_F_W)
  .value("VFNCVT_X_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_X_F_W)
  .value("VFNMACC_VF", LIEF::assembly::riscv::OPCODE::VFNMACC_VF)
  .value("VFNMACC_VV", LIEF::assembly::riscv::OPCODE::VFNMACC_VV)
  .value("VFNMADD_VF", LIEF::assembly::riscv::OPCODE::VFNMADD_VF)
  .value("VFNMADD_VV", LIEF::assembly::riscv::OPCODE::VFNMADD_VV)
  .value("VFNMSAC_VF", LIEF::assembly::riscv::OPCODE::VFNMSAC_VF)
  .value("VFNMSAC_VV", LIEF::assembly::riscv::OPCODE::VFNMSAC_VV)
  .value("VFNMSUB_VF", LIEF::assembly::riscv::OPCODE::VFNMSUB_VF)
  .value("VFNMSUB_VV", LIEF::assembly::riscv::OPCODE::VFNMSUB_VV)
  .value("VFNRCLIP_XU_F_QF", LIEF::assembly::riscv::OPCODE::VFNRCLIP_XU_F_QF)
  .value("VFNRCLIP_X_F_QF", LIEF::assembly::riscv::OPCODE::VFNRCLIP_X_F_QF)
  .value("VFRDIV_VF", LIEF::assembly::riscv::OPCODE::VFRDIV_VF)
  .value("VFREC7_V", LIEF::assembly::riscv::OPCODE::VFREC7_V)
  .value("VFREDMAX_VS", LIEF::assembly::riscv::OPCODE::VFREDMAX_VS)
  .value("VFREDMIN_VS", LIEF::assembly::riscv::OPCODE::VFREDMIN_VS)
  .value("VFREDOSUM_VS", LIEF::assembly::riscv::OPCODE::VFREDOSUM_VS)
  .value("VFREDUSUM_VS", LIEF::assembly::riscv::OPCODE::VFREDUSUM_VS)
  .value("VFRSQRT7_V", LIEF::assembly::riscv::OPCODE::VFRSQRT7_V)
  .value("VFRSUB_VF", LIEF::assembly::riscv::OPCODE::VFRSUB_VF)
  .value("VFSGNJN_VF", LIEF::assembly::riscv::OPCODE::VFSGNJN_VF)
  .value("VFSGNJN_VV", LIEF::assembly::riscv::OPCODE::VFSGNJN_VV)
  .value("VFSGNJX_VF", LIEF::assembly::riscv::OPCODE::VFSGNJX_VF)
  .value("VFSGNJX_VV", LIEF::assembly::riscv::OPCODE::VFSGNJX_VV)
  .value("VFSGNJ_VF", LIEF::assembly::riscv::OPCODE::VFSGNJ_VF)
  .value("VFSGNJ_VV", LIEF::assembly::riscv::OPCODE::VFSGNJ_VV)
  .value("VFSLIDE1DOWN_VF", LIEF::assembly::riscv::OPCODE::VFSLIDE1DOWN_VF)
  .value("VFSLIDE1UP_VF", LIEF::assembly::riscv::OPCODE::VFSLIDE1UP_VF)
  .value("VFSQRT_V", LIEF::assembly::riscv::OPCODE::VFSQRT_V)
  .value("VFSUB_VF", LIEF::assembly::riscv::OPCODE::VFSUB_VF)
  .value("VFSUB_VV", LIEF::assembly::riscv::OPCODE::VFSUB_VV)
  .value("VFWADD_VF", LIEF::assembly::riscv::OPCODE::VFWADD_VF)
  .value("VFWADD_VV", LIEF::assembly::riscv::OPCODE::VFWADD_VV)
  .value("VFWADD_WF", LIEF::assembly::riscv::OPCODE::VFWADD_WF)
  .value("VFWADD_WV", LIEF::assembly::riscv::OPCODE::VFWADD_WV)
  .value("VFWCVTBF16_F_F_V", LIEF::assembly::riscv::OPCODE::VFWCVTBF16_F_F_V)
  .value("VFWCVT_F_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_F_V)
  .value("VFWCVT_F_XU_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_XU_V)
  .value("VFWCVT_F_X_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_X_V)
  .value("VFWCVT_RTZ_XU_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_XU_F_V)
  .value("VFWCVT_RTZ_X_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_X_F_V)
  .value("VFWCVT_XU_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_XU_F_V)
  .value("VFWCVT_X_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_X_F_V)
  .value("VFWMACCBF16_VF", LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VF)
  .value("VFWMACCBF16_VV", LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VV)
  .value("VFWMACC_4x4x4", LIEF::assembly::riscv::OPCODE::VFWMACC_4x4x4)
  .value("VFWMACC_VF", LIEF::assembly::riscv::OPCODE::VFWMACC_VF)
  .value("VFWMACC_VV", LIEF::assembly::riscv::OPCODE::VFWMACC_VV)
  .value("VFWMSAC_VF", LIEF::assembly::riscv::OPCODE::VFWMSAC_VF)
  .value("VFWMSAC_VV", LIEF::assembly::riscv::OPCODE::VFWMSAC_VV)
  .value("VFWMUL_VF", LIEF::assembly::riscv::OPCODE::VFWMUL_VF)
  .value("VFWMUL_VV", LIEF::assembly::riscv::OPCODE::VFWMUL_VV)
  .value("VFWNMACC_VF", LIEF::assembly::riscv::OPCODE::VFWNMACC_VF)
  .value("VFWNMACC_VV", LIEF::assembly::riscv::OPCODE::VFWNMACC_VV)
  .value("VFWNMSAC_VF", LIEF::assembly::riscv::OPCODE::VFWNMSAC_VF)
  .value("VFWNMSAC_VV", LIEF::assembly::riscv::OPCODE::VFWNMSAC_VV)
  .value("VFWREDOSUM_VS", LIEF::assembly::riscv::OPCODE::VFWREDOSUM_VS)
  .value("VFWREDUSUM_VS", LIEF::assembly::riscv::OPCODE::VFWREDUSUM_VS)
  .value("VFWSUB_VF", LIEF::assembly::riscv::OPCODE::VFWSUB_VF)
  .value("VFWSUB_VV", LIEF::assembly::riscv::OPCODE::VFWSUB_VV)
  .value("VFWSUB_WF", LIEF::assembly::riscv::OPCODE::VFWSUB_WF)
  .value("VFWSUB_WV", LIEF::assembly::riscv::OPCODE::VFWSUB_WV)
  .value("VGHSH_VV", LIEF::assembly::riscv::OPCODE::VGHSH_VV)
  .value("VGMUL_VV", LIEF::assembly::riscv::OPCODE::VGMUL_VV)
  .value("VID_V", LIEF::assembly::riscv::OPCODE::VID_V)
  .value("VIOTA_M", LIEF::assembly::riscv::OPCODE::VIOTA_M)
  .value("VL1RE16_V", LIEF::assembly::riscv::OPCODE::VL1RE16_V)
  .value("VL1RE32_V", LIEF::assembly::riscv::OPCODE::VL1RE32_V)
  .value("VL1RE64_V", LIEF::assembly::riscv::OPCODE::VL1RE64_V)
  .value("VL1RE8_V", LIEF::assembly::riscv::OPCODE::VL1RE8_V)
  .value("VL2RE16_V", LIEF::assembly::riscv::OPCODE::VL2RE16_V)
  .value("VL2RE32_V", LIEF::assembly::riscv::OPCODE::VL2RE32_V)
  .value("VL2RE64_V", LIEF::assembly::riscv::OPCODE::VL2RE64_V)
  .value("VL2RE8_V", LIEF::assembly::riscv::OPCODE::VL2RE8_V)
  .value("VL4RE16_V", LIEF::assembly::riscv::OPCODE::VL4RE16_V)
  .value("VL4RE32_V", LIEF::assembly::riscv::OPCODE::VL4RE32_V)
  .value("VL4RE64_V", LIEF::assembly::riscv::OPCODE::VL4RE64_V)
  .value("VL4RE8_V", LIEF::assembly::riscv::OPCODE::VL4RE8_V)
  .value("VL8RE16_V", LIEF::assembly::riscv::OPCODE::VL8RE16_V)
  .value("VL8RE32_V", LIEF::assembly::riscv::OPCODE::VL8RE32_V)
  .value("VL8RE64_V", LIEF::assembly::riscv::OPCODE::VL8RE64_V)
  .value("VL8RE8_V", LIEF::assembly::riscv::OPCODE::VL8RE8_V)
  .value("VLE16FF_V", LIEF::assembly::riscv::OPCODE::VLE16FF_V)
  .value("VLE16_V", LIEF::assembly::riscv::OPCODE::VLE16_V)
  .value("VLE32FF_V", LIEF::assembly::riscv::OPCODE::VLE32FF_V)
  .value("VLE32_V", LIEF::assembly::riscv::OPCODE::VLE32_V)
  .value("VLE64FF_V", LIEF::assembly::riscv::OPCODE::VLE64FF_V)
  .value("VLE64_V", LIEF::assembly::riscv::OPCODE::VLE64_V)
  .value("VLE8FF_V", LIEF::assembly::riscv::OPCODE::VLE8FF_V)
  .value("VLE8_V", LIEF::assembly::riscv::OPCODE::VLE8_V)
  .value("VLM_V", LIEF::assembly::riscv::OPCODE::VLM_V)
  .value("VLOXEI16_V", LIEF::assembly::riscv::OPCODE::VLOXEI16_V)
  .value("VLOXEI32_V", LIEF::assembly::riscv::OPCODE::VLOXEI32_V)
  .value("VLOXEI64_V", LIEF::assembly::riscv::OPCODE::VLOXEI64_V)
  .value("VLOXEI8_V", LIEF::assembly::riscv::OPCODE::VLOXEI8_V)
  .value("VLOXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI16_V)
  .value("VLOXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI32_V)
  .value("VLOXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI64_V)
  .value("VLOXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI8_V)
  .value("VLOXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI16_V)
  .value("VLOXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI32_V)
  .value("VLOXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI64_V)
  .value("VLOXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI8_V)
  .value("VLOXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI16_V)
  .value("VLOXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI32_V)
  .value("VLOXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI64_V)
  .value("VLOXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI8_V)
  .value("VLOXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI16_V)
  .value("VLOXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI32_V)
  .value("VLOXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI64_V)
  .value("VLOXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI8_V)
  .value("VLOXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI16_V)
  .value("VLOXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI32_V)
  .value("VLOXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI64_V)
  .value("VLOXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI8_V)
  .value("VLOXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI16_V)
  .value("VLOXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI32_V)
  .value("VLOXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI64_V)
  .value("VLOXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI8_V)
  .value("VLOXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI16_V)
  .value("VLOXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI32_V)
  .value("VLOXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI64_V)
  .value("VLOXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI8_V)
  .value("VLSE16_V", LIEF::assembly::riscv::OPCODE::VLSE16_V)
  .value("VLSE32_V", LIEF::assembly::riscv::OPCODE::VLSE32_V)
  .value("VLSE64_V", LIEF::assembly::riscv::OPCODE::VLSE64_V)
  .value("VLSE8_V", LIEF::assembly::riscv::OPCODE::VLSE8_V)
  .value("VLSEG2E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E16FF_V)
  .value("VLSEG2E16_V", LIEF::assembly::riscv::OPCODE::VLSEG2E16_V)
  .value("VLSEG2E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E32FF_V)
  .value("VLSEG2E32_V", LIEF::assembly::riscv::OPCODE::VLSEG2E32_V)
  .value("VLSEG2E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E64FF_V)
  .value("VLSEG2E64_V", LIEF::assembly::riscv::OPCODE::VLSEG2E64_V)
  .value("VLSEG2E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E8FF_V)
  .value("VLSEG2E8_V", LIEF::assembly::riscv::OPCODE::VLSEG2E8_V)
  .value("VLSEG3E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E16FF_V)
  .value("VLSEG3E16_V", LIEF::assembly::riscv::OPCODE::VLSEG3E16_V)
  .value("VLSEG3E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E32FF_V)
  .value("VLSEG3E32_V", LIEF::assembly::riscv::OPCODE::VLSEG3E32_V)
  .value("VLSEG3E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E64FF_V)
  .value("VLSEG3E64_V", LIEF::assembly::riscv::OPCODE::VLSEG3E64_V)
  .value("VLSEG3E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E8FF_V)
  .value("VLSEG3E8_V", LIEF::assembly::riscv::OPCODE::VLSEG3E8_V)
  .value("VLSEG4E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E16FF_V)
  .value("VLSEG4E16_V", LIEF::assembly::riscv::OPCODE::VLSEG4E16_V)
  .value("VLSEG4E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E32FF_V)
  .value("VLSEG4E32_V", LIEF::assembly::riscv::OPCODE::VLSEG4E32_V)
  .value("VLSEG4E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E64FF_V)
  .value("VLSEG4E64_V", LIEF::assembly::riscv::OPCODE::VLSEG4E64_V)
  .value("VLSEG4E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E8FF_V)
  .value("VLSEG4E8_V", LIEF::assembly::riscv::OPCODE::VLSEG4E8_V)
  .value("VLSEG5E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E16FF_V)
  .value("VLSEG5E16_V", LIEF::assembly::riscv::OPCODE::VLSEG5E16_V)
  .value("VLSEG5E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E32FF_V)
  .value("VLSEG5E32_V", LIEF::assembly::riscv::OPCODE::VLSEG5E32_V)
  .value("VLSEG5E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E64FF_V)
  .value("VLSEG5E64_V", LIEF::assembly::riscv::OPCODE::VLSEG5E64_V)
  .value("VLSEG5E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E8FF_V)
  .value("VLSEG5E8_V", LIEF::assembly::riscv::OPCODE::VLSEG5E8_V)
  .value("VLSEG6E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E16FF_V)
  .value("VLSEG6E16_V", LIEF::assembly::riscv::OPCODE::VLSEG6E16_V)
  .value("VLSEG6E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E32FF_V)
  .value("VLSEG6E32_V", LIEF::assembly::riscv::OPCODE::VLSEG6E32_V)
  .value("VLSEG6E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E64FF_V)
  .value("VLSEG6E64_V", LIEF::assembly::riscv::OPCODE::VLSEG6E64_V)
  .value("VLSEG6E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E8FF_V)
  .value("VLSEG6E8_V", LIEF::assembly::riscv::OPCODE::VLSEG6E8_V)
  .value("VLSEG7E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E16FF_V)
  .value("VLSEG7E16_V", LIEF::assembly::riscv::OPCODE::VLSEG7E16_V)
  .value("VLSEG7E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E32FF_V)
  .value("VLSEG7E32_V", LIEF::assembly::riscv::OPCODE::VLSEG7E32_V)
  .value("VLSEG7E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E64FF_V)
  .value("VLSEG7E64_V", LIEF::assembly::riscv::OPCODE::VLSEG7E64_V)
  .value("VLSEG7E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E8FF_V)
  .value("VLSEG7E8_V", LIEF::assembly::riscv::OPCODE::VLSEG7E8_V)
  .value("VLSEG8E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E16FF_V)
  .value("VLSEG8E16_V", LIEF::assembly::riscv::OPCODE::VLSEG8E16_V)
  .value("VLSEG8E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E32FF_V)
  .value("VLSEG8E32_V", LIEF::assembly::riscv::OPCODE::VLSEG8E32_V)
  .value("VLSEG8E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E64FF_V)
  .value("VLSEG8E64_V", LIEF::assembly::riscv::OPCODE::VLSEG8E64_V)
  .value("VLSEG8E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E8FF_V)
  .value("VLSEG8E8_V", LIEF::assembly::riscv::OPCODE::VLSEG8E8_V)
  .value("VLSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E16_V)
  .value("VLSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E32_V)
  .value("VLSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E64_V)
  .value("VLSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E8_V)
  .value("VLSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E16_V)
  .value("VLSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E32_V)
  .value("VLSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E64_V)
  .value("VLSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E8_V)
  .value("VLSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E16_V)
  .value("VLSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E32_V)
  .value("VLSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E64_V)
  .value("VLSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E8_V)
  .value("VLSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E16_V)
  .value("VLSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E32_V)
  .value("VLSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E64_V)
  .value("VLSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E8_V)
  .value("VLSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E16_V)
  .value("VLSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E32_V)
  .value("VLSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E64_V)
  .value("VLSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E8_V)
  .value("VLSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E16_V)
  .value("VLSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E32_V)
  .value("VLSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E64_V)
  .value("VLSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E8_V)
  .value("VLSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E16_V)
  .value("VLSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E32_V)
  .value("VLSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E64_V)
  .value("VLSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E8_V)
  .value("VLUXEI16_V", LIEF::assembly::riscv::OPCODE::VLUXEI16_V)
  .value("VLUXEI32_V", LIEF::assembly::riscv::OPCODE::VLUXEI32_V)
  .value("VLUXEI64_V", LIEF::assembly::riscv::OPCODE::VLUXEI64_V)
  .value("VLUXEI8_V", LIEF::assembly::riscv::OPCODE::VLUXEI8_V)
  .value("VLUXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI16_V)
  .value("VLUXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI32_V)
  .value("VLUXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI64_V)
  .value("VLUXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI8_V)
  .value("VLUXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI16_V)
  .value("VLUXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI32_V)
  .value("VLUXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI64_V)
  .value("VLUXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI8_V)
  .value("VLUXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI16_V)
  .value("VLUXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI32_V)
  .value("VLUXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI64_V)
  .value("VLUXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI8_V)
  .value("VLUXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI16_V)
  .value("VLUXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI32_V)
  .value("VLUXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI64_V)
  .value("VLUXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI8_V)
  .value("VLUXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI16_V)
  .value("VLUXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI32_V)
  .value("VLUXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI64_V)
  .value("VLUXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI8_V)
  .value("VLUXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI16_V)
  .value("VLUXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI32_V)
  .value("VLUXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI64_V)
  .value("VLUXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI8_V)
  .value("VLUXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI16_V)
  .value("VLUXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI32_V)
  .value("VLUXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI64_V)
  .value("VLUXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI8_V)
  .value("VMACC_VV", LIEF::assembly::riscv::OPCODE::VMACC_VV)
  .value("VMACC_VX", LIEF::assembly::riscv::OPCODE::VMACC_VX)
  .value("VMADC_VI", LIEF::assembly::riscv::OPCODE::VMADC_VI)
  .value("VMADC_VIM", LIEF::assembly::riscv::OPCODE::VMADC_VIM)
  .value("VMADC_VV", LIEF::assembly::riscv::OPCODE::VMADC_VV)
  .value("VMADC_VVM", LIEF::assembly::riscv::OPCODE::VMADC_VVM)
  .value("VMADC_VX", LIEF::assembly::riscv::OPCODE::VMADC_VX)
  .value("VMADC_VXM", LIEF::assembly::riscv::OPCODE::VMADC_VXM)
  .value("VMADD_VV", LIEF::assembly::riscv::OPCODE::VMADD_VV)
  .value("VMADD_VX", LIEF::assembly::riscv::OPCODE::VMADD_VX)
  .value("VMANDN_MM", LIEF::assembly::riscv::OPCODE::VMANDN_MM)
  .value("VMAND_MM", LIEF::assembly::riscv::OPCODE::VMAND_MM)
  .value("VMAXU_VV", LIEF::assembly::riscv::OPCODE::VMAXU_VV)
  .value("VMAXU_VX", LIEF::assembly::riscv::OPCODE::VMAXU_VX)
  .value("VMAX_VV", LIEF::assembly::riscv::OPCODE::VMAX_VV)
  .value("VMAX_VX", LIEF::assembly::riscv::OPCODE::VMAX_VX)
  .value("VMERGE_VIM", LIEF::assembly::riscv::OPCODE::VMERGE_VIM)
  .value("VMERGE_VVM", LIEF::assembly::riscv::OPCODE::VMERGE_VVM)
  .value("VMERGE_VXM", LIEF::assembly::riscv::OPCODE::VMERGE_VXM)
  .value("VMFEQ_VF", LIEF::assembly::riscv::OPCODE::VMFEQ_VF)
  .value("VMFEQ_VV", LIEF::assembly::riscv::OPCODE::VMFEQ_VV)
  .value("VMFGE_VF", LIEF::assembly::riscv::OPCODE::VMFGE_VF)
  .value("VMFGT_VF", LIEF::assembly::riscv::OPCODE::VMFGT_VF)
  .value("VMFLE_VF", LIEF::assembly::riscv::OPCODE::VMFLE_VF)
  .value("VMFLE_VV", LIEF::assembly::riscv::OPCODE::VMFLE_VV)
  .value("VMFLT_VF", LIEF::assembly::riscv::OPCODE::VMFLT_VF)
  .value("VMFLT_VV", LIEF::assembly::riscv::OPCODE::VMFLT_VV)
  .value("VMFNE_VF", LIEF::assembly::riscv::OPCODE::VMFNE_VF)
  .value("VMFNE_VV", LIEF::assembly::riscv::OPCODE::VMFNE_VV)
  .value("VMINU_VV", LIEF::assembly::riscv::OPCODE::VMINU_VV)
  .value("VMINU_VX", LIEF::assembly::riscv::OPCODE::VMINU_VX)
  .value("VMIN_VV", LIEF::assembly::riscv::OPCODE::VMIN_VV)
  .value("VMIN_VX", LIEF::assembly::riscv::OPCODE::VMIN_VX)
  .value("VMNAND_MM", LIEF::assembly::riscv::OPCODE::VMNAND_MM)
  .value("VMNOR_MM", LIEF::assembly::riscv::OPCODE::VMNOR_MM)
  .value("VMORN_MM", LIEF::assembly::riscv::OPCODE::VMORN_MM)
  .value("VMOR_MM", LIEF::assembly::riscv::OPCODE::VMOR_MM)
  .value("VMSBC_VV", LIEF::assembly::riscv::OPCODE::VMSBC_VV)
  .value("VMSBC_VVM", LIEF::assembly::riscv::OPCODE::VMSBC_VVM)
  .value("VMSBC_VX", LIEF::assembly::riscv::OPCODE::VMSBC_VX);
  opcodes.value("VMSBC_VXM", LIEF::assembly::riscv::OPCODE::VMSBC_VXM)
  .value("VMSBF_M", LIEF::assembly::riscv::OPCODE::VMSBF_M)
  .value("VMSEQ_VI", LIEF::assembly::riscv::OPCODE::VMSEQ_VI)
  .value("VMSEQ_VV", LIEF::assembly::riscv::OPCODE::VMSEQ_VV)
  .value("VMSEQ_VX", LIEF::assembly::riscv::OPCODE::VMSEQ_VX)
  .value("VMSGTU_VI", LIEF::assembly::riscv::OPCODE::VMSGTU_VI)
  .value("VMSGTU_VX", LIEF::assembly::riscv::OPCODE::VMSGTU_VX)
  .value("VMSGT_VI", LIEF::assembly::riscv::OPCODE::VMSGT_VI)
  .value("VMSGT_VX", LIEF::assembly::riscv::OPCODE::VMSGT_VX)
  .value("VMSIF_M", LIEF::assembly::riscv::OPCODE::VMSIF_M)
  .value("VMSLEU_VI", LIEF::assembly::riscv::OPCODE::VMSLEU_VI)
  .value("VMSLEU_VV", LIEF::assembly::riscv::OPCODE::VMSLEU_VV)
  .value("VMSLEU_VX", LIEF::assembly::riscv::OPCODE::VMSLEU_VX)
  .value("VMSLE_VI", LIEF::assembly::riscv::OPCODE::VMSLE_VI)
  .value("VMSLE_VV", LIEF::assembly::riscv::OPCODE::VMSLE_VV)
  .value("VMSLE_VX", LIEF::assembly::riscv::OPCODE::VMSLE_VX)
  .value("VMSLTU_VV", LIEF::assembly::riscv::OPCODE::VMSLTU_VV)
  .value("VMSLTU_VX", LIEF::assembly::riscv::OPCODE::VMSLTU_VX)
  .value("VMSLT_VV", LIEF::assembly::riscv::OPCODE::VMSLT_VV)
  .value("VMSLT_VX", LIEF::assembly::riscv::OPCODE::VMSLT_VX)
  .value("VMSNE_VI", LIEF::assembly::riscv::OPCODE::VMSNE_VI)
  .value("VMSNE_VV", LIEF::assembly::riscv::OPCODE::VMSNE_VV)
  .value("VMSNE_VX", LIEF::assembly::riscv::OPCODE::VMSNE_VX)
  .value("VMSOF_M", LIEF::assembly::riscv::OPCODE::VMSOF_M)
  .value("VMULHSU_VV", LIEF::assembly::riscv::OPCODE::VMULHSU_VV)
  .value("VMULHSU_VX", LIEF::assembly::riscv::OPCODE::VMULHSU_VX)
  .value("VMULHU_VV", LIEF::assembly::riscv::OPCODE::VMULHU_VV)
  .value("VMULHU_VX", LIEF::assembly::riscv::OPCODE::VMULHU_VX)
  .value("VMULH_VV", LIEF::assembly::riscv::OPCODE::VMULH_VV)
  .value("VMULH_VX", LIEF::assembly::riscv::OPCODE::VMULH_VX)
  .value("VMUL_VV", LIEF::assembly::riscv::OPCODE::VMUL_VV)
  .value("VMUL_VX", LIEF::assembly::riscv::OPCODE::VMUL_VX)
  .value("VMV1R_V", LIEF::assembly::riscv::OPCODE::VMV1R_V)
  .value("VMV2R_V", LIEF::assembly::riscv::OPCODE::VMV2R_V)
  .value("VMV4R_V", LIEF::assembly::riscv::OPCODE::VMV4R_V)
  .value("VMV8R_V", LIEF::assembly::riscv::OPCODE::VMV8R_V)
  .value("VMV_S_X", LIEF::assembly::riscv::OPCODE::VMV_S_X)
  .value("VMV_V_I", LIEF::assembly::riscv::OPCODE::VMV_V_I)
  .value("VMV_V_V", LIEF::assembly::riscv::OPCODE::VMV_V_V)
  .value("VMV_V_X", LIEF::assembly::riscv::OPCODE::VMV_V_X)
  .value("VMV_X_S", LIEF::assembly::riscv::OPCODE::VMV_X_S)
  .value("VMXNOR_MM", LIEF::assembly::riscv::OPCODE::VMXNOR_MM)
  .value("VMXOR_MM", LIEF::assembly::riscv::OPCODE::VMXOR_MM)
  .value("VNCLIPU_WI", LIEF::assembly::riscv::OPCODE::VNCLIPU_WI)
  .value("VNCLIPU_WV", LIEF::assembly::riscv::OPCODE::VNCLIPU_WV)
  .value("VNCLIPU_WX", LIEF::assembly::riscv::OPCODE::VNCLIPU_WX)
  .value("VNCLIP_WI", LIEF::assembly::riscv::OPCODE::VNCLIP_WI)
  .value("VNCLIP_WV", LIEF::assembly::riscv::OPCODE::VNCLIP_WV)
  .value("VNCLIP_WX", LIEF::assembly::riscv::OPCODE::VNCLIP_WX)
  .value("VNMSAC_VV", LIEF::assembly::riscv::OPCODE::VNMSAC_VV)
  .value("VNMSAC_VX", LIEF::assembly::riscv::OPCODE::VNMSAC_VX)
  .value("VNMSUB_VV", LIEF::assembly::riscv::OPCODE::VNMSUB_VV)
  .value("VNMSUB_VX", LIEF::assembly::riscv::OPCODE::VNMSUB_VX)
  .value("VNSRA_WI", LIEF::assembly::riscv::OPCODE::VNSRA_WI)
  .value("VNSRA_WV", LIEF::assembly::riscv::OPCODE::VNSRA_WV)
  .value("VNSRA_WX", LIEF::assembly::riscv::OPCODE::VNSRA_WX)
  .value("VNSRL_WI", LIEF::assembly::riscv::OPCODE::VNSRL_WI)
  .value("VNSRL_WV", LIEF::assembly::riscv::OPCODE::VNSRL_WV)
  .value("VNSRL_WX", LIEF::assembly::riscv::OPCODE::VNSRL_WX)
  .value("VOR_VI", LIEF::assembly::riscv::OPCODE::VOR_VI)
  .value("VOR_VV", LIEF::assembly::riscv::OPCODE::VOR_VV)
  .value("VOR_VX", LIEF::assembly::riscv::OPCODE::VOR_VX)
  .value("VQMACCSU_2x8x2", LIEF::assembly::riscv::OPCODE::VQMACCSU_2x8x2)
  .value("VQMACCSU_4x8x4", LIEF::assembly::riscv::OPCODE::VQMACCSU_4x8x4)
  .value("VQMACCUS_2x8x2", LIEF::assembly::riscv::OPCODE::VQMACCUS_2x8x2)
  .value("VQMACCUS_4x8x4", LIEF::assembly::riscv::OPCODE::VQMACCUS_4x8x4)
  .value("VQMACCU_2x8x2", LIEF::assembly::riscv::OPCODE::VQMACCU_2x8x2)
  .value("VQMACCU_4x8x4", LIEF::assembly::riscv::OPCODE::VQMACCU_4x8x4)
  .value("VQMACC_2x8x2", LIEF::assembly::riscv::OPCODE::VQMACC_2x8x2)
  .value("VQMACC_4x8x4", LIEF::assembly::riscv::OPCODE::VQMACC_4x8x4)
  .value("VREDAND_VS", LIEF::assembly::riscv::OPCODE::VREDAND_VS)
  .value("VREDMAXU_VS", LIEF::assembly::riscv::OPCODE::VREDMAXU_VS)
  .value("VREDMAX_VS", LIEF::assembly::riscv::OPCODE::VREDMAX_VS)
  .value("VREDMINU_VS", LIEF::assembly::riscv::OPCODE::VREDMINU_VS)
  .value("VREDMIN_VS", LIEF::assembly::riscv::OPCODE::VREDMIN_VS)
  .value("VREDOR_VS", LIEF::assembly::riscv::OPCODE::VREDOR_VS)
  .value("VREDSUM_VS", LIEF::assembly::riscv::OPCODE::VREDSUM_VS)
  .value("VREDXOR_VS", LIEF::assembly::riscv::OPCODE::VREDXOR_VS)
  .value("VREMU_VV", LIEF::assembly::riscv::OPCODE::VREMU_VV)
  .value("VREMU_VX", LIEF::assembly::riscv::OPCODE::VREMU_VX)
  .value("VREM_VV", LIEF::assembly::riscv::OPCODE::VREM_VV)
  .value("VREM_VX", LIEF::assembly::riscv::OPCODE::VREM_VX)
  .value("VREV8_V", LIEF::assembly::riscv::OPCODE::VREV8_V)
  .value("VRGATHEREI16_VV", LIEF::assembly::riscv::OPCODE::VRGATHEREI16_VV)
  .value("VRGATHER_VI", LIEF::assembly::riscv::OPCODE::VRGATHER_VI)
  .value("VRGATHER_VV", LIEF::assembly::riscv::OPCODE::VRGATHER_VV)
  .value("VRGATHER_VX", LIEF::assembly::riscv::OPCODE::VRGATHER_VX)
  .value("VROL_VV", LIEF::assembly::riscv::OPCODE::VROL_VV)
  .value("VROL_VX", LIEF::assembly::riscv::OPCODE::VROL_VX)
  .value("VROR_VI", LIEF::assembly::riscv::OPCODE::VROR_VI)
  .value("VROR_VV", LIEF::assembly::riscv::OPCODE::VROR_VV)
  .value("VROR_VX", LIEF::assembly::riscv::OPCODE::VROR_VX)
  .value("VRSUB_VI", LIEF::assembly::riscv::OPCODE::VRSUB_VI)
  .value("VRSUB_VX", LIEF::assembly::riscv::OPCODE::VRSUB_VX)
  .value("VS1R_V", LIEF::assembly::riscv::OPCODE::VS1R_V)
  .value("VS2R_V", LIEF::assembly::riscv::OPCODE::VS2R_V)
  .value("VS4R_V", LIEF::assembly::riscv::OPCODE::VS4R_V)
  .value("VS8R_V", LIEF::assembly::riscv::OPCODE::VS8R_V)
  .value("VSADDU_VI", LIEF::assembly::riscv::OPCODE::VSADDU_VI)
  .value("VSADDU_VV", LIEF::assembly::riscv::OPCODE::VSADDU_VV)
  .value("VSADDU_VX", LIEF::assembly::riscv::OPCODE::VSADDU_VX)
  .value("VSADD_VI", LIEF::assembly::riscv::OPCODE::VSADD_VI)
  .value("VSADD_VV", LIEF::assembly::riscv::OPCODE::VSADD_VV)
  .value("VSADD_VX", LIEF::assembly::riscv::OPCODE::VSADD_VX)
  .value("VSBC_VVM", LIEF::assembly::riscv::OPCODE::VSBC_VVM)
  .value("VSBC_VXM", LIEF::assembly::riscv::OPCODE::VSBC_VXM)
  .value("VSE16_V", LIEF::assembly::riscv::OPCODE::VSE16_V)
  .value("VSE32_V", LIEF::assembly::riscv::OPCODE::VSE32_V)
  .value("VSE64_V", LIEF::assembly::riscv::OPCODE::VSE64_V)
  .value("VSE8_V", LIEF::assembly::riscv::OPCODE::VSE8_V)
  .value("VSETIVLI", LIEF::assembly::riscv::OPCODE::VSETIVLI)
  .value("VSETVL", LIEF::assembly::riscv::OPCODE::VSETVL)
  .value("VSETVLI", LIEF::assembly::riscv::OPCODE::VSETVLI)
  .value("VSEXT_VF2", LIEF::assembly::riscv::OPCODE::VSEXT_VF2)
  .value("VSEXT_VF4", LIEF::assembly::riscv::OPCODE::VSEXT_VF4)
  .value("VSEXT_VF8", LIEF::assembly::riscv::OPCODE::VSEXT_VF8)
  .value("VSHA2CH_VV", LIEF::assembly::riscv::OPCODE::VSHA2CH_VV)
  .value("VSHA2CL_VV", LIEF::assembly::riscv::OPCODE::VSHA2CL_VV)
  .value("VSHA2MS_VV", LIEF::assembly::riscv::OPCODE::VSHA2MS_VV)
  .value("VSLIDE1DOWN_VX", LIEF::assembly::riscv::OPCODE::VSLIDE1DOWN_VX)
  .value("VSLIDE1UP_VX", LIEF::assembly::riscv::OPCODE::VSLIDE1UP_VX)
  .value("VSLIDEDOWN_VI", LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VI)
  .value("VSLIDEDOWN_VX", LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VX)
  .value("VSLIDEUP_VI", LIEF::assembly::riscv::OPCODE::VSLIDEUP_VI)
  .value("VSLIDEUP_VX", LIEF::assembly::riscv::OPCODE::VSLIDEUP_VX)
  .value("VSLL_VI", LIEF::assembly::riscv::OPCODE::VSLL_VI)
  .value("VSLL_VV", LIEF::assembly::riscv::OPCODE::VSLL_VV)
  .value("VSLL_VX", LIEF::assembly::riscv::OPCODE::VSLL_VX)
  .value("VSM3C_VI", LIEF::assembly::riscv::OPCODE::VSM3C_VI)
  .value("VSM3ME_VV", LIEF::assembly::riscv::OPCODE::VSM3ME_VV)
  .value("VSM4K_VI", LIEF::assembly::riscv::OPCODE::VSM4K_VI)
  .value("VSM4R_VS", LIEF::assembly::riscv::OPCODE::VSM4R_VS)
  .value("VSM4R_VV", LIEF::assembly::riscv::OPCODE::VSM4R_VV)
  .value("VSMUL_VV", LIEF::assembly::riscv::OPCODE::VSMUL_VV)
  .value("VSMUL_VX", LIEF::assembly::riscv::OPCODE::VSMUL_VX)
  .value("VSM_V", LIEF::assembly::riscv::OPCODE::VSM_V)
  .value("VSOXEI16_V", LIEF::assembly::riscv::OPCODE::VSOXEI16_V)
  .value("VSOXEI32_V", LIEF::assembly::riscv::OPCODE::VSOXEI32_V)
  .value("VSOXEI64_V", LIEF::assembly::riscv::OPCODE::VSOXEI64_V)
  .value("VSOXEI8_V", LIEF::assembly::riscv::OPCODE::VSOXEI8_V)
  .value("VSOXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI16_V)
  .value("VSOXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI32_V)
  .value("VSOXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI64_V)
  .value("VSOXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI8_V)
  .value("VSOXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI16_V)
  .value("VSOXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI32_V)
  .value("VSOXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI64_V)
  .value("VSOXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI8_V)
  .value("VSOXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI16_V)
  .value("VSOXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI32_V)
  .value("VSOXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI64_V)
  .value("VSOXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI8_V)
  .value("VSOXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI16_V)
  .value("VSOXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI32_V)
  .value("VSOXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI64_V)
  .value("VSOXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI8_V)
  .value("VSOXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI16_V)
  .value("VSOXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI32_V)
  .value("VSOXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI64_V)
  .value("VSOXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI8_V)
  .value("VSOXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI16_V)
  .value("VSOXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI32_V)
  .value("VSOXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI64_V)
  .value("VSOXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI8_V)
  .value("VSOXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI16_V)
  .value("VSOXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI32_V)
  .value("VSOXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI64_V)
  .value("VSOXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI8_V)
  .value("VSRA_VI", LIEF::assembly::riscv::OPCODE::VSRA_VI)
  .value("VSRA_VV", LIEF::assembly::riscv::OPCODE::VSRA_VV)
  .value("VSRA_VX", LIEF::assembly::riscv::OPCODE::VSRA_VX)
  .value("VSRL_VI", LIEF::assembly::riscv::OPCODE::VSRL_VI)
  .value("VSRL_VV", LIEF::assembly::riscv::OPCODE::VSRL_VV)
  .value("VSRL_VX", LIEF::assembly::riscv::OPCODE::VSRL_VX)
  .value("VSSE16_V", LIEF::assembly::riscv::OPCODE::VSSE16_V)
  .value("VSSE32_V", LIEF::assembly::riscv::OPCODE::VSSE32_V)
  .value("VSSE64_V", LIEF::assembly::riscv::OPCODE::VSSE64_V)
  .value("VSSE8_V", LIEF::assembly::riscv::OPCODE::VSSE8_V)
  .value("VSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VSSEG2E16_V)
  .value("VSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VSSEG2E32_V)
  .value("VSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VSSEG2E64_V)
  .value("VSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VSSEG2E8_V)
  .value("VSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VSSEG3E16_V)
  .value("VSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VSSEG3E32_V)
  .value("VSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VSSEG3E64_V)
  .value("VSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VSSEG3E8_V)
  .value("VSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VSSEG4E16_V)
  .value("VSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VSSEG4E32_V)
  .value("VSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VSSEG4E64_V)
  .value("VSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VSSEG4E8_V)
  .value("VSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VSSEG5E16_V)
  .value("VSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VSSEG5E32_V)
  .value("VSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VSSEG5E64_V)
  .value("VSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VSSEG5E8_V)
  .value("VSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VSSEG6E16_V)
  .value("VSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VSSEG6E32_V)
  .value("VSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VSSEG6E64_V)
  .value("VSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VSSEG6E8_V)
  .value("VSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VSSEG7E16_V)
  .value("VSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VSSEG7E32_V)
  .value("VSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VSSEG7E64_V)
  .value("VSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VSSEG7E8_V)
  .value("VSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VSSEG8E16_V)
  .value("VSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VSSEG8E32_V)
  .value("VSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VSSEG8E64_V)
  .value("VSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VSSEG8E8_V)
  .value("VSSRA_VI", LIEF::assembly::riscv::OPCODE::VSSRA_VI)
  .value("VSSRA_VV", LIEF::assembly::riscv::OPCODE::VSSRA_VV)
  .value("VSSRA_VX", LIEF::assembly::riscv::OPCODE::VSSRA_VX)
  .value("VSSRL_VI", LIEF::assembly::riscv::OPCODE::VSSRL_VI)
  .value("VSSRL_VV", LIEF::assembly::riscv::OPCODE::VSSRL_VV)
  .value("VSSRL_VX", LIEF::assembly::riscv::OPCODE::VSSRL_VX)
  .value("VSSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E16_V)
  .value("VSSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E32_V)
  .value("VSSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E64_V)
  .value("VSSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E8_V)
  .value("VSSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E16_V)
  .value("VSSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E32_V)
  .value("VSSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E64_V)
  .value("VSSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E8_V)
  .value("VSSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E16_V)
  .value("VSSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E32_V)
  .value("VSSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E64_V)
  .value("VSSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E8_V)
  .value("VSSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E16_V)
  .value("VSSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E32_V)
  .value("VSSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E64_V)
  .value("VSSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E8_V)
  .value("VSSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E16_V)
  .value("VSSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E32_V)
  .value("VSSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E64_V)
  .value("VSSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E8_V)
  .value("VSSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E16_V)
  .value("VSSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E32_V)
  .value("VSSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E64_V)
  .value("VSSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E8_V)
  .value("VSSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E16_V)
  .value("VSSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E32_V)
  .value("VSSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E64_V)
  .value("VSSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E8_V)
  .value("VSSUBU_VV", LIEF::assembly::riscv::OPCODE::VSSUBU_VV)
  .value("VSSUBU_VX", LIEF::assembly::riscv::OPCODE::VSSUBU_VX)
  .value("VSSUB_VV", LIEF::assembly::riscv::OPCODE::VSSUB_VV)
  .value("VSSUB_VX", LIEF::assembly::riscv::OPCODE::VSSUB_VX)
  .value("VSUB_VV", LIEF::assembly::riscv::OPCODE::VSUB_VV)
  .value("VSUB_VX", LIEF::assembly::riscv::OPCODE::VSUB_VX)
  .value("VSUXEI16_V", LIEF::assembly::riscv::OPCODE::VSUXEI16_V)
  .value("VSUXEI32_V", LIEF::assembly::riscv::OPCODE::VSUXEI32_V)
  .value("VSUXEI64_V", LIEF::assembly::riscv::OPCODE::VSUXEI64_V)
  .value("VSUXEI8_V", LIEF::assembly::riscv::OPCODE::VSUXEI8_V)
  .value("VSUXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI16_V)
  .value("VSUXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI32_V)
  .value("VSUXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI64_V)
  .value("VSUXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI8_V)
  .value("VSUXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI16_V)
  .value("VSUXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI32_V)
  .value("VSUXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI64_V)
  .value("VSUXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI8_V)
  .value("VSUXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI16_V)
  .value("VSUXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI32_V)
  .value("VSUXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI64_V)
  .value("VSUXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI8_V)
  .value("VSUXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI16_V)
  .value("VSUXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI32_V)
  .value("VSUXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI64_V)
  .value("VSUXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI8_V)
  .value("VSUXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI16_V)
  .value("VSUXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI32_V)
  .value("VSUXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI64_V)
  .value("VSUXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI8_V)
  .value("VSUXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI16_V)
  .value("VSUXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI32_V)
  .value("VSUXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI64_V)
  .value("VSUXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI8_V)
  .value("VSUXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI16_V)
  .value("VSUXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI32_V)
  .value("VSUXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI64_V)
  .value("VSUXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI8_V)
  .value("VT_MASKC", LIEF::assembly::riscv::OPCODE::VT_MASKC)
  .value("VT_MASKCN", LIEF::assembly::riscv::OPCODE::VT_MASKCN)
  .value("VWADDU_VV", LIEF::assembly::riscv::OPCODE::VWADDU_VV)
  .value("VWADDU_VX", LIEF::assembly::riscv::OPCODE::VWADDU_VX)
  .value("VWADDU_WV", LIEF::assembly::riscv::OPCODE::VWADDU_WV)
  .value("VWADDU_WX", LIEF::assembly::riscv::OPCODE::VWADDU_WX)
  .value("VWADD_VV", LIEF::assembly::riscv::OPCODE::VWADD_VV)
  .value("VWADD_VX", LIEF::assembly::riscv::OPCODE::VWADD_VX)
  .value("VWADD_WV", LIEF::assembly::riscv::OPCODE::VWADD_WV)
  .value("VWADD_WX", LIEF::assembly::riscv::OPCODE::VWADD_WX)
  .value("VWMACCSU_VV", LIEF::assembly::riscv::OPCODE::VWMACCSU_VV)
  .value("VWMACCSU_VX", LIEF::assembly::riscv::OPCODE::VWMACCSU_VX)
  .value("VWMACCUS_VX", LIEF::assembly::riscv::OPCODE::VWMACCUS_VX)
  .value("VWMACCU_VV", LIEF::assembly::riscv::OPCODE::VWMACCU_VV)
  .value("VWMACCU_VX", LIEF::assembly::riscv::OPCODE::VWMACCU_VX)
  .value("VWMACC_VV", LIEF::assembly::riscv::OPCODE::VWMACC_VV)
  .value("VWMACC_VX", LIEF::assembly::riscv::OPCODE::VWMACC_VX)
  .value("VWMULSU_VV", LIEF::assembly::riscv::OPCODE::VWMULSU_VV)
  .value("VWMULSU_VX", LIEF::assembly::riscv::OPCODE::VWMULSU_VX)
  .value("VWMULU_VV", LIEF::assembly::riscv::OPCODE::VWMULU_VV)
  .value("VWMULU_VX", LIEF::assembly::riscv::OPCODE::VWMULU_VX)
  .value("VWMUL_VV", LIEF::assembly::riscv::OPCODE::VWMUL_VV);
  opcodes.value("VWMUL_VX", LIEF::assembly::riscv::OPCODE::VWMUL_VX)
  .value("VWREDSUMU_VS", LIEF::assembly::riscv::OPCODE::VWREDSUMU_VS)
  .value("VWREDSUM_VS", LIEF::assembly::riscv::OPCODE::VWREDSUM_VS)
  .value("VWSLL_VI", LIEF::assembly::riscv::OPCODE::VWSLL_VI)
  .value("VWSLL_VV", LIEF::assembly::riscv::OPCODE::VWSLL_VV)
  .value("VWSLL_VX", LIEF::assembly::riscv::OPCODE::VWSLL_VX)
  .value("VWSUBU_VV", LIEF::assembly::riscv::OPCODE::VWSUBU_VV)
  .value("VWSUBU_VX", LIEF::assembly::riscv::OPCODE::VWSUBU_VX)
  .value("VWSUBU_WV", LIEF::assembly::riscv::OPCODE::VWSUBU_WV)
  .value("VWSUBU_WX", LIEF::assembly::riscv::OPCODE::VWSUBU_WX)
  .value("VWSUB_VV", LIEF::assembly::riscv::OPCODE::VWSUB_VV)
  .value("VWSUB_VX", LIEF::assembly::riscv::OPCODE::VWSUB_VX)
  .value("VWSUB_WV", LIEF::assembly::riscv::OPCODE::VWSUB_WV)
  .value("VWSUB_WX", LIEF::assembly::riscv::OPCODE::VWSUB_WX)
  .value("VXOR_VI", LIEF::assembly::riscv::OPCODE::VXOR_VI)
  .value("VXOR_VV", LIEF::assembly::riscv::OPCODE::VXOR_VV)
  .value("VXOR_VX", LIEF::assembly::riscv::OPCODE::VXOR_VX)
  .value("VZEXT_VF2", LIEF::assembly::riscv::OPCODE::VZEXT_VF2)
  .value("VZEXT_VF4", LIEF::assembly::riscv::OPCODE::VZEXT_VF4)
  .value("VZEXT_VF8", LIEF::assembly::riscv::OPCODE::VZEXT_VF8)
  .value("WFI", LIEF::assembly::riscv::OPCODE::WFI)
  .value("WRS_NTO", LIEF::assembly::riscv::OPCODE::WRS_NTO)
  .value("WRS_STO", LIEF::assembly::riscv::OPCODE::WRS_STO)
  .value("XNOR", LIEF::assembly::riscv::OPCODE::XNOR)
  .value("XOR", LIEF::assembly::riscv::OPCODE::XOR)
  .value("XORI", LIEF::assembly::riscv::OPCODE::XORI)
  .value("XPERM4", LIEF::assembly::riscv::OPCODE::XPERM4)
  .value("XPERM8", LIEF::assembly::riscv::OPCODE::XPERM8)
  .value("ZEXT_H_RV32", LIEF::assembly::riscv::OPCODE::ZEXT_H_RV32)
  .value("ZEXT_H_RV64", LIEF::assembly::riscv::OPCODE::ZEXT_H_RV64)
  .value("ZIP_RV32", LIEF::assembly::riscv::OPCODE::ZIP_RV32)
  .value("INSTRUCTION_LIST_END", LIEF::assembly::riscv::OPCODE::INSTRUCTION_LIST_END)
  ;
}
}
