/*
    Stack, TIA and RAM share the same place on ZP

    Standardised start-up code, clears stack, all TIA registers and RAM to 0
    Sets stack pointer to $FF, and all registers to 0
    Sets decimal mode off, sets interrupt flag (kind of un-necessary)
    Use as very first section of code on boot (ie: at reset)
*/
.macro INIT_SYSTEM
    sei         ; for some unknown reason, 6509 does't have interrupt pin exposed
    cld
    ldx #$ff
    txs
    inx
    txa
    sta:rne 0,x+
.endm

/*
    Inserts the code required for a proper 3 scanline vertical sync sequence
    Note: Alters the accumulator
*/
.macro VERTICAL_SYNC
    lda #%1110  ; each '1' bits generate a VSYNC ON line (bits 1..3)
@   sta WSYNC   ; 1st '0' bit resets Vsync, 2nd '0' bit exit loop
    sta VSYNC
    lsr
    bne @-      ; branch until VYSNC has been reset
.endm

/*
    Wait specific number of scanelines
    Note: Alters x register
*/
.macro WAIT_X_SCANLINES v
    ldx #:v         
@   sta WSYNC   ; accessing WSYNC stops the CPU until next scanline
    dex
    bne @-
.endm

/*
    Wait for Horizontal Blank
*/
.macro W_SYNC
    sta WSYNC
.endm

/*
    Reset Horizontal Sync Counter
*/
.macro R_SYNC
    sta RSYNC
.endm

/*
    Reset Player 0
*/
.macro RES_P0
    sta RESP0
.endm

/*
    Reset Player 1
*/
.macro RES_P1
    sta RESP1
.endm

/*
    Reset Missle 0
*/
.macro RES_M0
    sta RESM0
.endm

/*
    Reset Missle 1
*/
.macro RES_M1
    sta RESM1
.endm

/*
    Reset Ball
*/
.macro RES_BL
    sta RESBL
.endm

/*
    Apply Horizontal Motion
*/
.macro H_MOVE
    sta HMOVE
.endm

/*
    Clear Horizontal Move Registers
*/
.macro HM_CLR
    sta HMCLR
.endm

/*
    Clear Collision Latche
*/
.macro CX_CLR
    sta CXCLR
.endm

;-------------------------------------------------------------------------------

/*
inline init     { i+ d-     s=x=0xFF    a=0 { zeropage,x=a x-- }!=  }
inline timwait  { { a=INTIM }!= }
inline wsync    { WSYNC=a }

// PAL:     0   45  275     312
// NTSC:    0   37  231     262

// PAL
inline sync1    { timwait wsync VBLANK=a=2 TIM64T=a=40 }
inline sync2    { timwait wsync VSYNC=a=2 wsync wsync a=0 wsync VSYNC=a TIM64T=a=54 }
inline sync3    { timwait wsync VBLANK=a=0 T1024T=a=18 }

// NTSC
inline sync1  { timwait wsync VBLANK=a=2 TIM64T=a=33 }
inline sync2  { timwait wsync VSYNC=a=2 wsync wsync a=0 wsync VSYNC=a TIM64T=a=44 }
inline sync3  { timwait wsync VBLANK=a=0 TIM64T=a=231 }
*/