# 7450 Events
#
event:0x1 counters:0,1,2,3,4,5 um:zero minimum:100 name:CYCLES : Cycles
event:0x2 counters:0,1,2,3   um:zero minimum:100 name:COMPLETED_INS : Completed Instructions
event:0x3 counters:0,1,2,3 um:zero minimum:500 name:TLB_TRANS : TBL bit transitions
event:0x4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_INS : Number of instructions dispatched: 0, 1, 2, or 3 per cycle
event:0x5 counters:0,1,2,3 um:zero minimum:0 name:PMC_EXCEPTION : Processor performance monitor exception
event:0x7 counters:0,1,2 um:zero minimum:0 name:EXTERNAL_PMC_SIGN : External performance monitor signal
event:0x8 counters:0,1,2 um:zero minimum:0 name:COMPLETED_VPU_INS : VPU instructions completed
event:0x9 counters:0,1,2 um:zero minimum:0 name:COMPLETED_VFPU_INS : VFPU instructions completed
event:0xa counters:0,1,2 um:zero minimum:0 name:COMPLETED_VIU1_INS : VIU1 instructions completed
event:0xb counters:0,1,2 um:zero minimum:0 name:COMPLETED_VIU2_INS : VIU2 instructions completed



