#
# MIPS 24K
#
# As standard the CPU supports 2 performance counters.  Event 0, 1, 11, 22,
# are available on both counters; events 12, 13, 24 - 63 are reserved;
# the remaining are counter-specific.
#
event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : Instructions completed
event:11 counters:0,1 um:zero minimum:500 name:DCACHE_MISS : Data cache misses
event:22 counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 cache misses

#
# Events specific to counter 0
#
event:2 counters:0 um:zero minimum:500 name:BRANCHES_LAUNCHED : Branch instructions launched (whether completed or mispredicted)
event:3 counters:0 um:zero minimum:500 name:JR_31_LAUNCHED : jr r31 (return) instructions launched (whether completed or mispredicted)
event:4 counters:0 um:zero minimum:500 name:JR_NON_31_LAUNCHED : jr (not r31) issues, which cost the same as a mispredict.
event:5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : Instruction micro-TLB accesses
event:6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : Data micro-TLB accesses
event:7 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : Joint TLB instruction accesses
event:8 counters:0 um:zero minimum:500 name:JTLB_INSTRUCTION_ACCESSES : Joint TLB data (non-instruction) accesses
event:9 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_ACCESSES : Instruction cache accesses
event:10 counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : Data cache accesses
event:14 counters:0 um:zero minimum:500 name:INTEGER_INSNS_COMPLETED : Integer instructions completed
event:15 counters:0 um:zero minimum:500 name:LOADS_COMPLETED : Loads completed (including FP)
event:16 counters:0 um:zero minimum:500 name:J_JAL_INSNS_COMPLETED : j/jal instructions completed
event:17 counters:0 um:zero minimum:500 name:NOPS_COMPLETED : no-ops completed, ie instructions writing $0
event:18 counters:0 um:zero minimum:500 name:STALLS : Stalls
event:19 counters:0 um:zero minimum:500 name:SC_COMPLETED : sc instructions completed
event:20 counters:0 um:zero minimum:500 name:PREFETCH_COMPLETED : Prefetch instructions completed
event:21 counters:0 um:zero minimum:500 name:SCACHE_WRITEBACKS : L2 cache writebacks
event:23 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : Exceptions taken
event:24 counters:0 um:zero minimum:500 name:CACHE_FIXUPS : ``cache fixup'' events (specific to the 24K family microarchitecture).

#
# Events specific to counter 1
#
event:2 counters:1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
event:3 counters:1 um:zero minimum:500 name:JR_31_MISSPREDICTS : jr r31 (return) mispredictions
event:5 counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction micro-TLB misses
event:6 counters:1 um:zero minimum:500 name:DTLB_MISSES : Data micro-TLB misses
event:7 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : Joint TLB instruction misses
event:8 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data (non-instruction) misses
event:9 counters:1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
event:10 counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Data cache writebacks
event:14 counters:1 um:zero minimum:500 name:FPU_INSNS_NON_LOAD_STORE_COMPLETED : FPU instructions completed (not including loads/stores)
event:15 counters:1 um:zero minimum:500 name:STORES_COMPLETED : Stores completed (including FP)
event:16 counters:1 um:zero minimum:500 name:MIPS16_INSTRUCTIONS_COMPLETED : MIPS16 instructions completed
event:17 counters:1 um:zero minimum:500 name:INTEGER_MUL_DIV_COMPLETED : integer multiply/divide unit instructions completed
event:18 counters:1 um:zero minimum:500 name:REPLAY_TRAPS_NOT_UTLB : ``replay traps'' (other than micro-TLB related)
event:19 counters:1 um:zero minimum:500 name:SC_COMPLETE_BUT_FAILED : sc instructions completed, but store failed (because the link bit had been cleared).
event:20 counters:1 um:zero minimum:500 name:SUPERFLUOUS_INSTRUCTIONS : ``superfluous'' prefetch instructions (data was already in cache).
event:21 counters:1 um:zero minimum:500 name:SCACHE_ACCESSES : L2 cache accesses
