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ROM
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EEPROM
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Common
SFRs
Features Configuration Bits RAM map SFR map
PIC12F520
CONFIG (address:0x0FFF, mask:0x007F, default:0x007F)
OSC -- Oscillator (bitmask:0x0003)
OSC = LP 0x0FFC LP Osc With 18 ms DRT.
OSC = XT 0x0FFD XT Osc With 18 ms DRT.
OSC = INTRC 0x0FFE INTRC With 1 ms DRT.
OSC = EXTRC 0x0FFF EXTRC With 1 ms DRT.
WDT -- Watchdog Timer Enable (bitmask:0x0004)
WDT = OFF 0x0FFB WDT disabled.
WDT = ON 0x0FFF WDT enabled.
CP -- Code Protect (bitmask:0x0008)
CP = ON 0x0FF7 Code protection on.
CP = OFF 0x0FFF Code protection off.
MCLR -- Master Clear Enable (bitmask:0x0010)
MCLR = OFF 0x0FEF RB3/MCLR Functions as RB3.
MCLR = ON 0x0FFF RB3/MCLR Functions as MCLR.
IOSCFS -- Internal Oscillator Frequency Select (bitmask:0x0020)
IOSCFS = 4MHZ 0x0FDF 4 MHz INTOSC Speed.
IOSCFS = 8MHZ 0x0FFF 8 MHz INTOSC Speed.
CPDF -- Code Protect bit - Self Writable Memory (bitmask:0x0040)
CPDF = ON 0x0FBF Code protection on.
CPDF = OFF 0x0FFF Code protection off.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:45 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.