


XSLS(1ICD)		     1/3/87		       XSLS(1ICD)



NNNNAAAAMMMMEEEE
     xsls, xspice, xedifnet - extract an SLS, SPICE or EDIF net-
     work description out of the database

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     xxxxssssllllssss [-fhirv] cell
     xxxxssssppppiiiicccceeee [-afhivElmnpuxy -z name] cell
     xxxxeeeeddddiiiiffffnnnneeeetttt [-efhiv] cell

OOOOPPPPTTTTIIIIOOOONNNNSSSS
     ----ffff   send output to a file _c_e_l_l.sls (for SLS output) a file
	  _c_e_l_l.spc (for SPICE output), a file _c_e_l_l.esp (for
	  ESPICE output), or a file _c_e_l_l.edif (for EDIF output),
	  instead of to _s_t_d_o_u_t.

     ----hhhh   also extract all local sub-cells.

     ----iiii   when option ----hhhh is used, also extract all imported sub-
	  cells.

     ----vvvv   enable verbose mode.

     The following option is used for SLS circuit descriptions
     only.

     ----rrrr   do not generate extern network definitions for sub-
	  cells that are not retrieved.

     The following options are used for SPICE circuit descrip-
     tions only.

     ----EEEE   extract an ESPICE circuit description.

     ----aaaa   use names for node and terminal references instead of
	  only numbers.

     ----llll   generate a name list that translates database names of
	  nodes into corresponding numbers of nodes as used in
	  the circuit description.

     ----mmmm   include model definitions for devices in the output
	  file.

     ----nnnn   always add terminals for n-bulk connections.

     ----pppp   always add terminals for p-bulk connections.

     ----uuuu   do not automatically add terminals for bulk connec-
	  tions.

     ----xxxx   use node number = 0 for nodes whose name start with
	  "gnd" or "GND".



		   The Nelsis IC Design System			1






XSLS(1ICD)		     1/3/87		       XSLS(1ICD)



     ----yyyy   the same for node whose names start with "vss" or
	  "VSS".

     ----zzzz _p_r_e_f_i_x
	  the same for nodes whose name start with _p_r_e_f_i_x.

     The following option is used for EDIF circuit descriptions
     only.

     ----eeee   expand name arrays into single names.

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _X_s_l_s, _x_s_p_i_c_e and _x_e_d_i_f_n_e_t are programs to respectively
     extract an SLS circuit description, a SPICE circuit descrip-
     tion or an EDIF netlist description out of the database.
     Default, only a circuit description of the cell itself is
     extracted and no sub-cells are extracted.	When using the
     option ----hhhh the program will also extract all (local) sub-
     cells that are not a function (see "SLS: Switch-Level Simu-
     lator User's Manual") or a device.

     Whether or not a cell is a device is determined by (1) a set
     of built-in device names: "res" for resistor, "cap" for
     capacitor, "nenh" for an n-enhancement transistor, "penh"
     for an p-enhancement transistor and "ndep" for a n-depletion
     transistor, (2) the use of the program _p_u_t_d_e_v_m_o_d(_1_I_C_D) (see
     the manual page of this program), or (3) - optionally and
     for SPICE circuit descriptions only - by the contents of a
     file "spice_prim".  The syntax of the file "spice_prim" is
     defined as follows: Each line contains (1) the name of the
     cell, and (2) a letter that specifies the first letter for
     instance names for that cell.  E.g: "pnp q" specifies that
     cell pnp is a primitive cell for SPICE, and that each
     instance name that is generated for that cell should start
     with the letter 'q'.  It is however recommanded to use to
     program _p_u_t_d_e_v_m_o_d instead of the file "spice_prim" to
     specify whether or not a cell is a device.

     When extracting SPICE circuit descriptions, the program
     _x_s_p_i_c_e will automatically determine if n-bulk and/or p-bulk
     terminals should be added.  This is determined from the bulk
     voltages that are required for the different devices that
     are part of the circuit and, under normal circumstances,
     comes down to the fact that for circuits containing n-
     enhancement and depletion transistors n-bulk connections are
     added, and that for circuits containing p-enhancement
     transistors (also) p-bulk connections are added.

     When using the option ----mmmm _x_s_p_i_c_e will automatically add model
     descriptions to the network for the devices that are part
     the network.  These model descriptions are searched at the
     following places.	First the process library directory is



2		   The Nelsis IC Design System






XSLS(1ICD)		     1/3/87		       XSLS(1ICD)



     searched for a file _s_p_i_c_e_m_o_d(_3_I_C_D). If this file is present
     it will added at the end of the network description.
     Second, the program will search for model descriptions that
     have been added to the database with the use of the program
     _p_u_t_d_e_v_m_o_d. For all devices that occur in the network and
     that have a model description stored in the database, this
     model description will added to the end of the network.
     Further, when using the ----mmmm option, the program will automat-
     ically generate an n-bulk and/or p-bulk voltage source if
     required (this is determined from the bulk terminals that
     are added).

EEEEXXXXAAAAMMMMPPPPLLLLEEEESSSS
     $ xsls -h latch

     $ xspice -fhmx invert

AAAAUUUUTTTTHHHHOOOORRRR
     A.J. van Genderen

FFFFIIIILLLLEEEESSSS
     _c_e_l_l.sls	       (opt.) output file
     _c_e_l_l.spc	       (opt.) output file
     _c_e_l_l.esp	       (opt.) output file
     _c_e_l_l.edif	       (opt.) output file
     spice_prim        (opt.) input file

SSSSEEEEEEEE AAAALLLLSSSSOOOO
     sls_mkdb(1ICD),
     putdevmod(1ICD).

























		   The Nelsis IC Design System			3



