


SPACE(1ICD)                  25/1/88                  SPACE(1ICD)



NNNNAAAAMMMMEEEE
     space - hierarchical layout to circuit extractor.

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     ssssppppaaaacccceeee [-cCl3rzFIuntdvi] [-D_d_e_p_t_h] [-a_s_e_c] [-e_x_x_x | -E_f_i_l_e]
     [-p_x_x_x | -P_f_i_l_e] cell ...

OOOOPPPPTTTTIIIIOOOONNNNSSSS
     The following options can be specified:

     ----cccc      Extract capacitances to substrate.

     ----CCCC      Also extract coupling capacitances, implies ----cccc.

     ----llll      Also extract lateral coupling capacitances, implies
             ----CCCC.

     ----3333      Use a 3-dimensional finite-element technique for
             accurate capacitance extraction.  Use with ----cccc or ----CCCC.

     ----rrrr      Extract resistances for high-resistivity (non-metal)
             interconnect.

     ----zzzz      Use a fine mesh for resistance extraction, implies
             ----rrrr.

     ----FFFF      Do flat extraction, instead of hierarchical.

     ----IIII      Unset incremental mode: do not skip sub-cells for
             which the circuit is up-to-date.  Cannot be used
             with the ----FFFF option.

     ----DDDD_d_e_p_t_h Selectively unset incremental mode for all cells at
             level <= _d_e_p_t_h.  Cannot be used with the ----FFFF option.

     ----uuuu      Do not automatically run the preprocessors
             _m_a_k_e_b_o_x_l(_1_I_C_D) and _m_a_k_e_g_l_n(_1_I_C_D).

     ----nnnn      Do not apply the circuit reduction heuristics.

     ----tttt      Add transistor positions to the extracted circuit.

     ----dddd      Omit the transistor dimensions from the circuit.

     ----vvvv      Verbose mode.

     ----iiii      Print statistics, implies verbose mode.

     ----aaaa_s_e_c   Make Space report its progression every _s_e_c seconds.

     ----eeee_x_x_x   Use the file space._x_x_x.t in the ICD process library
             as the element definition file.



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     ----EEEE_f_i_l_e  Use _f_i_l_e as the element definition file.

     ----pppp_x_x_x   Use the file space._x_x_x.p in the ICD process library
             as the parameter file.

     ----PPPP_f_i_l_e  Use _f_i_l_e as the parameter file.

NNNNOOOOTTTTIIIICCCCEEEE
     This manual page only gives a brief introduction to Space.
     It should in most cases be sufficient, however, for perform-
     ing straight-forward extraction tasks.  Other documentation
     is available, see below.

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _S_p_a_c_e is a hierarchical layout to circuit extractor for 45
     degree polygonal geometries.  The program is capable of
     accurately extracting MOS integrated circuits, including
     parasitic resistances, substrate and coupling capacitances.
     Generally spoken, Space extracts the circuits for all layout
     cells that are specified in the cell argument list.  These
     circuits can then be directly simulated, for example, with
     _s_l_s(_1_I_C_D) or _s_p_i_c_e.

     HHHHiiiieeeerrrraaaarrrrcccchhhhiiiiccccaaaallll,,,, FFFFllllaaaatttt oooorrrr MMMMiiiixxxxeeeedddd EEEExxxxttttrrrraaaaccccttttiiiioooonnnn
     The basic extraction mode of Space is hierarchical.  In this
     mode, the hierarchical structure of the circuit produced is
     identical to that of the layout.  In hierarchical mode,
     Space traverses the hierarchy itself.  It is thus only
     necessary to specify the root(s) of the tree(s) to be
     extracted on the command line.  When the ----FFFF option is used,
     the layout is flattened before extraction.  Mixed
     hierarchical/fat extraction can be accomplished by assigning
     some cells the _m_a_c_r_o status, see macro (1ICD).  Cells with
     the _m_a_c_r_o status are always completely expanded in their
     parent cells.  When all cells would have the macro status,
     the circuit produced would be the same as when the ----FFFF option
     was used.

     IIIInnnnccccrrrreeeemmmmeeeennnnttttaaaallll EEEExxxxttttrrrraaaaccccttttiiiioooonnnn
     In hierarchical mode, Space works incrementally.  That is,
     it only extracts those cells which have not yet been
     extracted or are out of date with respect to the layout.
     Incremental mode can be disabled with the ----IIII option, in
     which case Space extracts all cells in the tree.  It can be
     selectively disabled for all cells at level <= _d_e_p_t_h with
     the ----DDDD_d_e_p_t_h option.  The cells named on the command line are
     at level 1, their children at level 2, etc.  The default
     _d_e_p_t_h is 1.  Thus, the cells named on the command line are
     extracted even if the circuit exists and is up-to-date with
     respect to the layout.  Use ----DDDD_0 if this is not desirable.
     The option ----DDDD_i_n_f_i_n_i_t_y is equivalent to ----IIII.  The ----IIII and
     ----DDDD_d_e_p_t_h options have no effect in flat extraction mode.



2                  The Nelsis IC Design System






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     AAAArrrreeeeaaaa////PPPPeeeerrrriiiimmmmeeeetttteeeerrrr bbbbaaaasssseeeedddd CCCCaaaappppaaaacccciiiittttaaaannnncccceeee EEEExxxxttttrrrraaaaccccttttiiiioooonnnn
     By default, Space uses an area area/perimeter method for
     capacitance extraction.  The capacitance is assumed to be
     proportional to c1 * A + c2 * P, where c1 and c2 are con-
     stants depending on which masks are present at a certain
     spot, and A and P are the relevant interconnect areas and
     perimeters, respectively.  When the ----cccc option is used, all
     capacitances so found, including the inter-wire coupling
     capacitances, are connected to ground (the substrate).  When
     the ----CCCC option is used, however, the coupling capacitances
     are put in the extracted circuit.

     The formula above only accounts for the coupling capaci-
     tances caused by overlapping wires.  To also extract the
     capacitive coupling between neigboring wires, the ----llll option
     can be used.  See the user's manual for details.

     TTTThhhhrrrreeeeeeee----DDDDiiiimmmmeeeennnnssssiiiioooonnnnaaaallll CCCCaaaappppaaaacccciiiittttaaaannnncccceeee EEEExxxxttttrrrraaaaccccttttiiiioooonnnn
     Space can also use a finite-element method for capacitance
     extraction.  Currently, however, the version of Space that
     supports this option is only limitedly distributed, and is
     not discussed here any further.

     RRRReeeessssiiiissssttttaaaannnncccceeee EEEExxxxttttrrrraaaaccccttttiiiioooonnnn
     When extracting resistances, Space applies finite element
     techniques to construct a fine resistance mesh that models
     resistive effects in detail, and then applies a Gaussian
     elimination (or, equivalently, a star-triangle transforma-
     tion) node reduction technique to find the final network.
     In general, this network contains the nodes that are gate,
     source or drain connections, and nodes that are connections
     to instances or terminals of the cell.  However, the topol-
     ogy of the network is influenced by the network reduction
     heuristics that are applied, see below.

     When also extracting capacitances, the mesh will be an RC
     mesh.  In this case, the node reduction will proceed such
     that the Elmore time constants between the nodes in the
     final network are unchanged with respect to their value in
     the fine RC mesh.  This will guarantee that the electrical
     transfer function of the final network closely matches that
     of the fine RC mesh and, consequently, that of the actual
     circuit.

     NNNNeeeettttwwwwoooorrrrkkkk RRRReeeedddduuuuccccttttiiiioooonnnn HHHHeeeeuuuurrrriiiissssttttiiiiccccssss
     When extracting resistances and capacitances, Space can
     apply some heuristics to further reduce the number of ele-
     ments (resistors, capacitors and nodes) in the final network
     by neglecting irrelevant detail.  These heuristics include

     1       Merging of nodes that are connected by a small
             resistance.



                   The Nelsis IC Design System                  3






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     2       Deletion of large shunt resistances.

     3       Reconnecting small coupling capacitances to ground.

     All heuristics are controlled by parameters from the parame-
     ter file (see below).

     SSSSiiiimmmmuuuullllaaaattttiiiioooonnnn MMMMooooddddeeeellll SSSSuuuuppppppppoooorrrrtttt
     Space can treat selected cells as network primitives.
     Rather than extracting them, it will plug a pre-defined
     simulation model (see _p_u_t_d_e_v_m_o_d(_1_I_C_D))) in the extracted
     circuit.  This feature is especially useful for the extrac-
     tion of non-MOS (e.g. bipolar or BICMOS) technologies.  Each
     active device can then be assigned a simulation model, of
     course dependent on the simulator(s) that will be used.
     This simulation model status of a device can be combined
     with the macro status (see above), for accurate extraction
     of the interconnect parasitics associated with the device.

     EEEElllleeeemmmmeeeennnntttt DDDDeeeeffffiiiinnnniiiittttiiiioooonnnn FFFFiiiilllleeee
     _S_p_a_c_e is technology independent.  At start up, it reads a
     tabular element definition file specifying how the different
     elements like conductors and transistors can be recognized
     from the different mask combinations, and which values
     should be used for for example conductor capacitivity and
     conductor resistivity.  This tabular element file is con-
     structed from a user-defined element definition file by the
     Space technology compiler _t_e_c_c(1ICD).

     The default element definition file is _s_p_a_c_e._d_e_f._t in the
     appropriate directory of the ICD process library.  However,
     there can be several other element definition files for a
     particular process.  For example, the file _s_p_a_c_e._m_a_x._t may
     contain an element description with worst-case capacitance
     and resistance values.  This file can be read rather than
     the standard file by specifying ----eeee_m_a_x at the command line.

     You can also prepare your own element definition file and
     specify the name of that file with the ----EEEE_f_i_l_e option.  For a
     description of the format of such a file, see the Space user
     manual.

     PPPPaaaarrrraaaammmmeeeetttteeeerrrr FFFFiiiilllleeee
     Much of the operation of Space is also under control of
     parameters that are specified in a parameter file.  The
     default parameter file is _s_p_a_c_e._d_e_f._p in the appropriate
     directory of the ICD process library.  You can select
     another parameter file with the ----pppp_x_x_x or the ----PPPP_f_i_l_e options,
     analogous to selecting another element definition file.

     IIIInnnnffffoooorrrrmmmmaaaattttiiiioooonnnn FFFFeeeeeeeeddddbbbbaaaacccckkkk
     The ----vvvv option produces information on what files space is



4                  The Nelsis IC Design System






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     reading and what extraction steps are being taken.  The ----iiii
     option produces quantitative information, such as the number
     of nets and transistors.  With the ----aaaa_s_e_c option, Space
     reports its progression, in percentage of the layout
     scanned, every _s_e_c seconds.  Space also reports its progres-
     sion when it receives an ALARM signal, such a signal can be
     send by the command ``kill -ALRM _p_i_d'', where _p_i_d is the
     process id.

     IIIImmmmpppplllleeeemmmmeeeennnnttttaaaattttiiiioooonnnn
     _S_p_a_c_e is a scanline based extractor.  As a scanline is swept
     over the layout plane, the different steps of the method are
     executed in one pass.  While the RC mesh is being con-
     structed from the layout, nodes are eliminated as soon as
     all resistances and capacitances for that node are known.
     Also, all network elements are written to the database as
     soon as possible.  This results in low time and space com-
     plexities of O(N) and O(sqrt(N)) respectively, where N is
     the number of contour edges of the interconnection polygons.

EEEEXXXXAAAAMMMMPPPPLLLLEEEESSSS
     Produce a transistor network for the cell _l_a_t_c_h:

          space latch

     Include substrate capacitances:

          space -c latch

     Also include coupling capacitances and non-metal resis-
     tances:

          space -Cr latch

SSSSPPPPEEEECCCCIIIIAAAALLLL CCCCOOOONNNNSSSSIIIIDDDDEEEERRRRAAAATTTTIIIIOOOONNNNSSSS
     Before performing the actual extraction, _S_p_a_c_e first runs
     the preprocessors _m_a_k_e_b_o_x_l(_1_I_C_D) and _m_a_k_e_g_l_n(_1_I_C_D) to con-
     vert the original layout information into a set of non-
     vertical line segment files (gln files).  In contrast to a
     previous situation, this is currently automatically done by
     _S_p_a_c_e.

AAAAUUUUTTTTHHHHOOOORRRRSSSS
     A.J. van Genderen, N.P. van der Meijs

FFFFIIIILLLLEEEESSSS
     ICDPATH/lib/process/_p_r_o_c_e_s_s/space.def.t
                         default element definition file
     ICDPATH/lib/process/_p_r_o_c_e_s_s/space.def.p
                         default parameter file
     _p_r_o_j__d_i_r/exp_dat    list of cells to be extracted




                   The Nelsis IC Design System                  5






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SSSSEEEEEEEE AAAALLLLSSSSOOOO
     N.P. van der Meijs and A.J. van Genderen, ``Space User's
     Manual,'' Delft University of Technology, Delft, The Nether-
     lands.

     N.P. van der Meijs and A.J. van Genderen, ``Space
     Tutorial,'' Delft University of Technology, Delft, The Neth-
     erlands.

     A.J. van Genderen and N.P. van der Meijs, ``Extracting Sim-
     ple but Accurate RC Models for VLSI Interconnect,'' _P_r_o_c.
     _I_E_E_E _I_S_C_A_S-_8_8, (June 7-9, 1988).

     N.P. van der Meijs and J.T. Fokkema, ``VLSI circuit recon-
     struction from mask topology,'' _I_N_T_E_G_R_A_T_I_O_N, _t_h_e _V_L_S_I _J_o_u_r_-
     _n_a_l 2222(2) pp. 85-119 (1984).

     exp(1ICD), makeboxl(1ICD), makegln(1ICD), macro(1ICD),
     tecc(1ICD).




































6                  The Nelsis IC Design System



