SEQU(1ICD)

NAME
sequ - perform the detailed routing of a cell from a sequence of channels

SYNOPSIS
sequ [-cdfhlLmOPqrRsSxy4] [-C cir_core_name] [-X width] [-Y height] [-p opt] [-o c_name] [-G t_name] [-V t_name] [-g t_name] [-v t_name] flp_core_name [cir_chip_name]

OPTIONS
Sequ has an impressive list of options/arguments:

<flp_core_name>
    Specifies the name floorplan cell to be routed (obligatory). <cir_chip_name> Specifies the circuit cell containing the connectivity of the bonding-pads (optionally).

-c  No cleanup of the temporary files and cells in the database.

-d  Global one-Direction routing: Metal1 will be used in the horizontal direction, and the vertical layer in the vertical direction (see remarks).

-f  Fixed terminal positions on the chip boundary. If this option is supplied, the i/o terminal positions entered in ipp(1ICD) will be used.

-h  Help: print the list of options.

-l  Use poly terminals on left or right side of each channel. By default these (new) terminals are in the metal1 layer.

-L  Disable vertical terminals at the end of the channel.

-m  Shift of block (in x-direction) using mer (1ICD). This option should improve the abutment of adjacent terminals. Not implemented on each platform.

-O  Do not perform simple wire ordering at ends of the channel.

-P  Make spacer cells between the pad blocks. This option implies the specification of a 'cir_chip_cell'.

-q  Quiet mode: nothing is printed (except errors).

-r  Place the i/o terminals regularly on the chip boundary. This option causes sequ to divide these terminals evenly on each side. The spacing between the terminals will be approximately the same.

-R  Risky spacing rules. Using this option the length of the channel will be as short as possible. This may cause some problems for the channel router some problems.

-s  Print detailed routing statistics.

-S  Print detailed routing statistics and accurate wire length data to a file called "<cell_name>.stat".

-x  Fixed x-coordinate: Disables shift of blocks by composer.

-y  Fixed y-coordinate: No shift of blocks by channel router.

-4  No routing of last 4 (outer-) channels.

-C <cir_core_name>
    This option specifies the name of the core cell in the circuit view. By default sequ sets this name to <flp_core_cel>'. This option implies the specification of a <cir_chip_cell>.

-X <width>
    Set the minimum width of the core_cell to <width>.

-Y <height>
    Set the minimum height of the core_cell to <height>.

-o <flp_name>
    This option forces sequ to generate a placement called "flp_name" in the floorplan view of the database. It can be useful for accurate placement feedback to ipp(1ICD) or glroute(1ICD).

-p <opt>
    Send options to gcr(1ICD). The string <opt> will be send to the channel router as option(s).

-G <terminal_name>
    Set the name of the first GND-power terminal. This terminal (which has to be either on the left or bottom side of the father model) will be connected without using poly-wires.

-V <terminal_name>
    Set the name of first VDD-power terminal. This terminal has to be either on the right or on the top side.

-g <terminal_name>
    Set the name of second GND-power terminal. This terminal will be placed on the opposite side of the first gnd terminal.

-v <terminal_name>
    Set the name of second VDD-power terminal.

DESCRIPTION
Sequ is the control program for detailed routing. It is the interface between the global router and the gridless channel router. Starting from the output of the global router (glroute 1ICD) it will construct the channels in the correct order and call the channel router to generate the wires in each of them. The channel router gcr (1ICD) will return the width of the channel and write a layout cell into the database. Sequ keeps track of the translations and rotations involved. Finally it will merge the layout cells of each channel into the layout view under the name flp_core_name . If a <cir_chip_name> is specified, sequ will generate a pad ring. The design rule file "Route_rules" is read from the project directory. If, however, no such file is present, the default design rules file from the database will be read.

EXAMPLE
Let's assume you want to route a cell called 'processor'. In the layout and the circuit view the components (son cells) of 'processor' exist. In the circuit view the nets (connections) between the components of 'processor' are defined. Using the interactive placement program ipp a placement (floorplan) called 'chip' was created. This placement was stored in the floorplan view. The processor has power nets called 'Gnd' and 'Vdd'. The terminals of these nets are also called 'Gnd' and 'Vdd'. The global routing and detailed routing can be performed by entering the following commands:
% glroute -G Gnd -V Vdd chip processor
% sequ -G Gnd -V Vdd chip
------ (sequ) reading core cell 'processor' from floorplan view ------
------ (sequ) routing channels ------
****** gcr H6
****** gcr V5
****** gcr H4
****** gcr V3
****** gcr H2
****** gcr V1
------ (sequ) channel routing complete ------
------ (sequ) writing core cell 'processor' into layout view ------
------ (sequ) semoving temporary cells and files ------
......
------ (sequ) Program finished ------
%

REMARKS
Power nets
If no gnd or vdd terminals are specified, the power nets will contain polysilicon wires. Notice that - in contrast to glroute - the names of the vdd and gnd terminals will have to be specified, not the name of their net. Sequ places the power terminals on the same side of the chip as they were placed in ipp (but never on the same position). The gnd-terminals must be either on the left or on the bottom side and the vdd-terminals on the right of top side. For each power net, two terminals can be specified which will be connected without using poly wires. The second power terminal will be placed automatically on the opposite side of the chip as the first power terminal. The width of the power terminals will be adjusted according to width of the power wires. 4 outer channels If the '-4' option is supplied, the last 4 channels will not be routed. The terminals which are at that time on the edges of the father model will be 'lifted up'. Terminals which belong to cells keep their original name. Terminals which are at the end of a channel (generated internally) will obtain the name of the net they belong to. Notice that the father cell could contain a number of terminals which share the same name. detailed placement
The '-x' option disables the horizontal shift of blocks by the composer, while the '-y' fixes the width of all channels (if possible). If both options are supplied, sequ will attempt to make the final chip layout resemble the initial placement. This will only work properly if the spacing between the blocks is about the same as the spacing required by the wires. Another way to perform detailed placement is by using the '-m' option. In that case, a channel width estimator (mer(1ICD)) will attempt to find the best horizontal offset of the blocks. Placement output
To feedback the final placement to ipp, the '-o' option can be used. A floorplan cell will be created in which the son-cells are placed on exactly the same place as in the layout cell. If a floorplan cell with that name already exists, it will be overwritten. This cell does not contain channels, so it will have to be re-routed globally. The '-x' and '-y' options can be used successfully for this cell because the spacing between the blocks is likely to be correct. Terminal placement
Sequ will adjust the positions of the external terminals, in order to minimize the wiring in the 4 outer channels. This is very useful for the generation of hierarchical building blocks. By supplying the '-f' option this mechanism is disabled: In that case the spacing between the terminals on the chip boundaries will be the same as was entered in ipp. The '-r' option causes sequ to spread the terminals evenly over the chip boundaries.

Temporary files
If, for some reasons, sequ is aborted before the program was finished, the layout view of the database will contain a number of cells called H* and V*. These cells contain the interconnect layout of the wires in a single channel. The cells can be removed, as well as the channel router input- and output files in the project directory (called H*, V*, H*.out, V*.out and optionally H*.stat and V*.stat). If these cells still exist the next time sequ is called, the channel router will print a warning message indicating a cell called H* or V* already exists. This will not cause any troubles because sequ keeps track of the actual cell name. By the way: by supplying the '-c' option all temporary cells will not be removed. -l option br The '-l' option will also introduce poly wires in power nets. No concurrency
Never execute more than one sequ at the time in the same project directory.

Statistics
The '-S' option causes sequ to generate a file called "<cell_name>.stat" which contains the wire length of each net. This file is constructed from the statistics files of each channel (which were generated by gcr(1ICD)). Layer direction
The '-d' option enables 'global one directional routing'. If this option is supplied, the horizontal wires in the horizontal channels of the chip will be in METAL1. The wires in the main direction of the vertical channels will be in the vertical layer specified in the design rule file "Route_rules" (3ICD). The default vertical layer is POLY. In this way, many vias at the edges of the channels can be prevented. A special design rule file is required for this option: 'Route_rev'. Sequ will complain and abort the the '-d' option if this file could not be found. The rules in 'Route_rev' will be used by gcr for the VERTICAL channels. You must 'fake' the channel router by specifying reversed layers in this file: interchange the rules of poly and metal. The '-d' option will only work correctly for 2-layer routing. Tests on the MCNC benchmark chips showed no great improvement with '-d'. However, for some double metal processes some gain could be expected. This feature has not been tested extensively. Cell size
Using the '-X <width>' and '-Y <height>' options the final size of the cell can be specified. Sequ will print a warning message if the cell does not fit within the specified area. Bonding pads (final chip assembly)
The bonding pad ring can also be assembled by sequ. To achieve pad ring assembly a number of preparations must be performed. A 'chip' cell must be created in the circuit view. This cell is the 'root' of the entire chip. It contains a single model call to the 'core' cell and model calls to the bonding pads. The chip cell is used to assign bonding pads to specify the which terminal of the core cell is specified to which terminal of a bonding pad.

               CIRCUIT
                chip
               / \
              / \
           core bonding_pads
          / / blocks All bonding pad cells should be present in the layout and circuit view (import them from a library if necessary). In order to achieve succesful assembly of the pad ring the bonding pad cells must fulfil a number of criteria. First of all the following restrictions apply to the terminals which connect them to the 'core' (signal terminals): They must touch the bonding-box. They must be on the same side. Sequ will rotate the bonding pad such that the terminal(s) are 'facing' the core terminals. Do not place them exactly in a corner of the bonding pad. The terminals should also be present in the circuit view. An arbitrary number of terminals is allowed on each bonding pad cell. It is therefore allowed to merge a number of bonding pads into a larger block. In this way 'fixed' bonding pad positions can be achieved. All terminals connecting to a single bonding pad cell must be connected to terminals placed on the same side of the core cell. For example, if a bonding pad contains the terminals for net 'a', 'b', and 'c' the terminals of those nets on the core cell must be placed on the same side. These restrictions do not apply to terminals which are not connected to the core. Sequ will place bonding pads at zero spacing. Therefore the bonding pads should be designed such that no design rule violations occur in that case. This can usually be achieved by simply adapting the size of the bounding box. The following restrictions apply to the 'chip' cell in the circuit view: The model call must contain exactly one instantiation of the core cell. Different types of bonding pads are allowed. All nets must contain exactly two terminals. Of each net, one terminal must belong to the core and the other to a bonding pad. In other words: a net between two pads is not allowed, as is a net between two terminals of the core cell. Notice that the chip cell is not present in the floorplan view. If this data is available pad ring assembly can be performed by sequ simply by specifying the name of the 'chip'-cell as second argument. It is even possible to make sequ fill the remaining space in the pad ring. In this way a 'power ring' can be assembled automatically. See the user's manual for more details.

AUTHORS
P. Groeneveld,
H. Cai

FILES
Technology file:
proj_dir/Route_rules      or
ICDPATH/lib/process/process_name/Route_rules
Input files:
proj_dir/floorplan/cell/info
proj_dir/floorplan/cell/mc
proj_dir/floorplan/cell/term
proj_dir/floorplan/cell/chan
proj_dir/layout/cell/info
proj_dir/layout/cell/term
Scratch files:
H* and V* files (gcr input/output channel files, see gcr(1ICD))
H* and V* cells (Temporary cells in the database generated by the channel router).
Output files:
proj_dir/layout/cell/box
proj_dir/layout/cell/mc
proj_dir/layout/cell/term
proj_dir/layout/cell/info

BUGS
In some cases, warnings for single terminal power nets will be printed. They can be ignored.

SEE ALSO
H. Cai and P. Groeneveld, "Delft Placement and Routing System User's Manual", The Nelsis IC Design System Documentation, Delft, March 1988.
gcr(1ICD),
glroute(1ICD),
ipp(1ICD),
mer(1ICD),
route_rules(3ICD).