


DIMCHECK(1ICD)		     6/15/82		   DIMCHECK(1ICD)



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     dimcheck - do a complete design_rule check

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     ddddiiiimmmmcccchhhheeeecccckkkk [-v] [----cccc||||----nnnn] [----ffff] [----tttt] [----gggg] [cell_name]

OOOOPPPPTTTTIIIIOOOONNNNSSSS
     ----vvvv      verbose mode

     ----cccc      Perform hierarchy_checks on the cell: i.e.  check if
	     connections between sub_cells are made via terminals
	     and check if no elements are formed from primitives
	     from different sub_cells. (default).

     ----nnnn      Do not perform hierarchy_checks.

     ----tttt      Debugging option, do not filter or merge error mes-
	     sages for a non orthogonal layout.

     ----gggg      Report gap errors between elements of the same
	     group.

     ----ffff      Use files 'booldata', 'dimcheckdata1', 'dimcheck-
	     data2' and 'dubcheckdata' if present in the current
	     working directory instead of the standard ones from
	     the library.

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _D_i_m_c_h_e_c_k checks the layers of a cell definition for all
     design rule errors.  Width, gap and overlap checks are per-
     formed and eventually an hierarchy_check.	Gap errors
     between edges of the same group are usually suppressed; use
     the -g option if this is not desired.

     The program _d_i_m_c_h_e_c_k can be used after _e_x_p.

     Checking is carried out in three steps performed by three
     subprograms, which are called automatically.  First the sub-
     program _n_b_o_o_l is called to produce the "bool_BN" files and
     to perform an hierarchy_check.  The latter is only signifi-
     cant if the cell to check has been expanded hierarchically.
     After that the subprograms _d_i_m_c_h_e_c_k and _d_u_b_c_h_e_c_k are called
     which use these files, together with the "LC_vln" files to
     do the actual checking for width, gap and overlap errors.
     The errors are reported on standard output.

     If no cell_name is specified the names of the cells to be
     checked will be read from the file "exp_dat".

     The current working directory must be the project directory.





		   The Nelsis IC Design System			1






DIMCHECK(1ICD)		     6/15/82		   DIMCHECK(1ICD)



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     T.G.R. van Leuken, J. Fokkema, J. Liedorp

FFFFIIIILLLLEEEESSSS
     ICDPATH/lib/nbool			     executable
     ICDPATH/lib/dimcheck		     executable
     ICDPATH/lib/dubcheck		     executable
     ICDPATH/lib/process/TECHN/booldata      (TECHN=technology directory)
     ICDPATH/lib/process/TECHN/dimcheckdata2
     ICDPATH/lib/process/TECHN/dubcheckdata
     proj_dir/exp_dat			     names of cells to be checked
     proj_dir/layout/cell/LC_vln	     input files, LC=LayerCode
     proj_dir/layout/cell/bool_BN	     input files, BN=BooleanNr

SSSSEEEEEEEE AAAALLLLSSSSOOOO
     T.G.R. van Leuken, J. Liedorp "An Hierarchical and Technol-
     ogy Independent Design Rule Checker", Delft University of
     Technology,
     autocheck(1ICD), booldata(3ICD), dimdata(3ICD),
     dubdata(3ICD), exp(1ICD), nbool(1ICD)

BBBBUUUUGGGGSSSS
     It is understood that the design rules are consistent.
     Error reporting is rather poor; the kind of error (width,
     gap or overlap) is reported together with the coordinates of
     the two points between which the error occurred.  In case of
     non orthogonal layouts the errors reported may be shifted a
     little from the place where they occurred due to rounding
     errors.


























2		   The Nelsis IC Design System



