


DMINST(1ICD)		    10/10/88		     DMINST(1ICD)



NNNNAAAAMMMMEEEE
     dminst - install cell in hierarchy after being updated

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     ddddmmmmiiiinnnnsssstttt [-lcf] [-drCv] cell_name

OOOOPPPPTTTTIIIIOOOONNNNSSSS
     ----llll      Install layout view of cell.

     ----cccc      Install circuit view of cell.

     ----ffff      Install floorplan view of cell.

     ----dddd      Delete hierarchical references ("mc" records) from
	     father cell(s).

     ----rrrr      Propagate always up to the root cell(s).

     ----CCCC      Perform hierarchical consistency Check only, do not
	     update.

     ----vvvv      Verbose mode.

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _D_m_i_n_s_t is a program that installs the specified cell in the
     design hierarchy.	It should be invoked by designers when
     updates have been made to a cell and this updated cell is
     still to be used as a component in its father cells.

     When a cell is being referenced hierarchically, i.e. a
     composite- or father cell uses this son cell as a component,
     certain parts of the description of the father cell relate
     to the description of the son cell.  For instance, in the
     layout view the bounding box of a cell depends on the bound-
     ing boxes of its instances.  In the circuit view the
     description of the connectivity of a father cell refers to
     terminals of its instances.  _H_i_e_r_a_r_c_h_i_c_a_l _c_o_n_s_i_s_t_e_n_c_y
     implies that these parts of the description of the father
     cell _c_o_r_r_e_c_t_l_y refer to the description of the son cell.

     The hierarchical consistency may be offended by updates to a
     cell that is being used as a component in higher level
     cells.  For instance, when a layout has been edited with
     _d_a_l_i (1ICD) or a circuit has been overwritten by _s_l_s__m_k_d_b
     (1ICD).  _D_m_i_n_s_t is a program that _i_n_s_t_a_l_l_s the specified
     cell in the design hierarchy: it checks / enforces hierarch-
     ical consistency.	In order to do so it recursively
     traverses the hierarchy in the upward direction as far as
     necessary, starting from the specified cell.  For all father
     cells it checks / enforces hierarchical consistency with
     respect to the specified son cell, and propagates changes if
     necessary.



		   The Nelsis IC Design System			1






DMINST(1ICD)		    10/10/88		     DMINST(1ICD)



     The operations performed by _d_m_i_n_s_t are to a large extent
     specific for the particular view-type of the specified cell.
     In the _l_a_y_o_u_t view information concerning bounding boxes is
     checked and, if necessary, updated.  Changes are propagated
     upward in the hierarchy until no changes occur.  Using the
     -r option all bounding boxes up to the root cells of the
     design hierarchy can be checked and updated, even if no
     changes occur on the way.	This is a useful feature for
     repairing corrupted databases.

     In the _c_i_r_c_u_i_t view _d_m_i_n_s_t only performs a number of checks
     on the connectivity of cells that instantiate the specified
     cell.  It checks whether these father cells correctly refer
     to terminals of the specified cell.  References to non-
     existing terminals are reported.  Currently no updates are
     performed.

     In the _f_l_o_o_r_p_l_a_n view currently no checks / updates are per-
     formed.

     By default _d_m_i_n_s_t installs "cell-name" for all view-types.
     Using the appropriate options the operation can be limited
     to a particular view-type(s).

     If a cell is not to be used any more as a component,
     hierarchical references to this cell can be _d_e_l_e_t_e_d with the
     -d option.  Limitation: the -d option currently only works
     for the layout view.

     Using the -C option only checks are performed, without
     information being updated.  _D_m_i_n_s_t reports what should be
     updated.

AAAAUUUUTTTTHHHHOOOORRRRSSSS
     G.W. Sloof, S. de Graaf, P. van der Wolf

FFFFIIIILLLLEEEESSSS
     proj_dir/layout/_c_e_l_l/mc		(in/out file)
     proj_dir/layout/_c_e_l_l/info		(in/out file)
     proj_dir/circuit/_c_e_l_l/mc		(input file)
     proj_dir/circuit/_c_e_l_l/net		(input file)
     proj_dir/circuit/_c_e_l_l/term 	(input file)













2		   The Nelsis IC Design System



