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     slsmod - process file for sls

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     The file _s_l_s_m_o_d contains the process information for the _s_l_s
     simulator.  This file is used by _s_l_s when a simulation is
     done at level 2 or level 3.

     The following variables are used in an _s_l_s_m_o_d process file:

     _v_h 	 The positive supply voltage in the circuit (vl =
		 0 is assumed).

     _v_m_i_n_h	 Minimum stable voltage for a logic I state.

     _v_m_a_x_l	 Maximum stable voltage for a logic O state.

     _k_r_i_s_e	 Factor with which RC time constants for rising
		 voltages are multiplied during timing simula-
		 tion.

     _k_f_a_l_l	 Factor with which RC time constants for falling
		 voltages are multiplied during timing simula-
		 tion.

     _l_o_f_f_s_e_t	 Value which has to be subtracted from the
		 layout-specified length of a transistor to gain
		 the effective length of the transistor.

     _w_o_f_f_s_e_t	 Value which has to be subtracted from the
		 layout-specified width of a transistor to gain
		 the effective width of the transistor.

     _r_s_t_a_t	 The resistance between drain and source used for
		 stable voltage determination.

     _r_s_a_t_u	 The same resistance but now for the saturated
		 case.	A transistor is said to be saturated when
		 - after an initial calculation with rstat resis-
		 tances - it appears that Vdrain or Vsource >
		 vh/2 (for nenh transistors) or Vdrain or Vsource
		 < vh/2 (for penh transistors).

     _c_g_s_t_a_t	 The gate capacitance of the transistor used for
		 stable voltage determination.

     _c_g_r_i_s_e	 The gate capacitance of the transistor used for
		 rise time calculations.

     _c_g_f_a_l_l	 The gate capacitance of the transistor used for
		 fall time calculations.




		   The Nelsis IC Design System			1






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     _c_e_s_t_a_t	 The drain or source capacitance of the transis-
		 tor used for stable voltage determination.

     _c_e_r_i_s_e	 The drain or source capacitance of the transis-
		 tor used for rise time calculations.

     _c_e_f_a_l_l	 The drain or source capacitance of the transis-
		 tor used for fall time calculations.

     _r_d_y_n	 The resistance between source and drain used for
		 rise and fall time calculations.

     _c_c_h	 The drain or source capacitance of the transis-
		 tor which is used in addition to _c_e_r_i_s_e or
		 _c_e_f_a_l_l during rise and fall time calculations.
		 However, this capacitance is only used if the
		 transistor is conducting.

     First the general simulation parameters _v_h, _v_m_i_n_h, _v_m_a_x_l,
     _k_r_i_s_e and _k_k_f_a_l_l are specified in the _s_l_s_m_o_d file.  Next,
     the other parameters - which are the transistor model param-
     eters - are specified.

     Transistor model parameters can be specified for a nenh, a
     penh and a ndep transistor.  Each of these parameter specif-
     ications might be omitted but their order is fixed.

     For each transistor first a specification of _l_o_f_f_s_e_t and
     _w_o_f_f_s_e_t is done.  Then the other variables are specified by
     giving their value for some typical transistor dimensions.
     This is done by first specifying the values for a minimum
     width and length and then specifying the values for a width
     and length that only differ from the first width and length
     by that the width is larger or that the length is larger.

     In order to obtain the parameters for transistors that have
     dimensions that are not enumerated, _s_l_s will perform an
     interpolation.

     For each transistor there is one general parameter specifi-
     cation list and several mode parameter specification lists.
     The general specification list contains the values for
     _r_s_t_a_t, _c_g_s_t_a_t, _c_g_r_i_s_e, _c_g_f_a_l_l, _c_e_s_t_a_t, _c_e_r_i_s_e and _c_e_f_a_l_l,
     and the mode specification lists contain the values for _r_d_y_n
     and _c_c_h.

     For the nenh transistor and the penh transistor _r_d_y_n and _c_c_h
     have to be specified for the following modes:

     _p_u_l_l_u_p	   A transistor is in the pullup mode when there
		   is static current flow through it and when a
		   time constant for a falling voltage is



2		   The Nelsis IC Design System






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		   determined.

     _p_u_l_l_d_o_w_n	   A transistor is in the pulldown mode when
		   there is static current flow through it and
		   when a time constant for a falling voltage is
		   determined.

     _p_a_s_s_u_p	   A transistor is in the passup mode when there
		   is no static current flow through it and when
		   a time constant for a rising voltage is deter-
		   mined.

     _p_a_s_s_d_o_w_n	   A transistor is in the passdown mode when
		   there is no static current flow through it and
		   when a time constant for a falling voltage is
		   determined.

     Whether or not there is a static current flow through a
     transistor is determined by considering all transistors to
     be "on".

     For an ndep transistor _r_d_y_n and _c_c_h have to be specified for
     the modes:

     _l_o_a_d	   A transistor is in the load mode when its gate
		   is connected to its drain or source (via a
		   resistor).

     _s_u_p_e_r_l_o_a_d	   A transistor is in the superload mode when its
		   gate is not connected to its drain or source
		   (via a resistor).

EEEEXXXXAAAAMMMMPPPPLLLLEEEE
     Below an example of a slsmod file for a NMOS process is
     given.

     /* process : nmos4u700A  TU-Delft
     /* author	: A.J. Schooneveld, TU-Delft
     /* date	: 6 May 1987
     */

     vh=5
     vminh=4
     vmaxl=1
     krise=0.90
     kfall=0.66

     nenh
	loffset=0.625u
	woffset=0.88u
	w=6u l=4u : rstat=4.97k rsatu=25.4k cgstat=13.0f cgrise=9.2f
		 cgfall=12.0f cestat=2.2f cerise=2.4f cefall=2.9f



		   The Nelsis IC Design System			3






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	w=15u l=4u : rstat=1.69k rsatu=6.95k cgstat=48.8f cgrise=24.2f
		  cgfall=38.0f cestat=6.3f cerise=5.6f cefall=8.9f
	w=30u l=4u : rstat=0.832k rsatu=3.19k cgstat=92.1f cgrise=54.1f
		  cgfall=82.2f cestat=12.8f cerise=11.8f cefall=15.0f
	pullup
	   /* not determined */
	   w=6u l=4u : rdyn=22.3k cch=8.7f
	   w=15u l=4u : rdyn=5.3k cch=31.8f
	   w=30u l=4u : rdyn=2.2k cch=53.3f
	end
	pulldown
	   w=6u l=4u : rdyn=22.3k cch=8.7f
	   w=15u l=4u : rdyn=5.3k cch=31.8f
	   w=30u l=4u : rdyn=2.2k cch=53.3f
	end
	passup
	   w=8u l=4u : rdyn=7.94k cch=4.62f
	end
	passdown
	   w=8u l=4u : rdyn=5.24k cch=5.29f
	end
     end

     ndep
	loffset=0.605u
	woffset=1.2u
	w=6u l=4u : rstat=29.2k rsatu=29.2k cgstat=7.8f cgrise=10.7f
		 cgfall=23.4f cestat=0f cerise=0f cefall=0f
	w=6u l=10u : rstat=76.5k rsatu=76.5k cgstat=11.7f cgrise=19.8f
		  cgfall=28.2f cestat=0f cerise=0f cefall=0f
	w=12u l=4u : rstat=10.2k rsatu=10.2k cgstat=16.4f cgrise=31.7f
		  cgfall=46.0f cestat=0f cerise=0f cefall=0f
	load
	   w=6u l=4u : rdyn=25.5k cch=-3.6f
	   w=6u l=10u : rdyn=66.3k cch=-14.9f
	   w=12u l=4u : rdyn=8.7k cch=-15.9f
	end
	superload
	   w=12u l=4u : rdyn=3.63k cch=-15.6f
	end
     end


AAAAUUUUTTTTHHHHOOOORRRR
     A.J. van Genderen

SSSSEEEEEEEE AAAALLLLSSSSOOOO
     A.J. Schooneveld, "Determination of SLS transistor model
     parameters", Delft University of Technology,
     sls(1ICD).





4		   The Nelsis IC Design System



