


SEQU(1ICD)		     29/7/87		       SEQU(1ICD)



NNNNAAAAMMMMEEEE
     sequ - perform the detailed routing of a cell from a
     sequence of channels

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     sssseeeeqqqquuuu [----ccccddddffffhhhhllllLLLLmmmmOOOOPPPPqqqqrrrrRRRRssssSSSSxxxxyyyy4444] [----CCCC cir_core_name] [----XXXX width] [----YYYY
     height] [----pppp opt] [----oooo c_name] [----GGGG t_name] [----VVVV t_name] [----gggg
     t_name] [----vvvv t_name] flp_core_name [cir_chip_name]

OOOOPPPPTTTTIIIIOOOONNNNSSSS
     _S_e_q_u has an impressive list of options/arguments:

     <<<<ffffllllpppp____ccccoooorrrreeee____nnnnaaaammmmeeee>>>>
	  Specifies the name floorplan cell to be routed (obliga-
	  tory).  <<<<cccciiiirrrr____cccchhhhiiiipppp____nnnnaaaammmmeeee>>>> Specifies the circuit cell con-
	  taining the connectivity of the bonding-pads (option-
	  ally).

     ----cccc   No cleanup of the temporary files and cells in the
	  database.

     ----dddd   Global one-Direction routing: Metal1 will be used in
	  the horizontal direction, and the vertical layer in the
	  vertical direction (see remarks).

     ----ffff   Fixed terminal positions on the chip boundary.  If this
	  option is supplied, the i/o terminal positions entered
	  in _i_p_p(1ICD) will be used.

     ----hhhh   Help: print the list of options.

     ----llll   Use poly terminals on left or right side of each chan-
	  nel.	By default these (new) terminals are in the
	  metal1 layer.

     ----LLLL   Disable vertical terminals at the end of the channel.

     ----mmmm   Shift of block (in x-direction) using mer (1ICD). This
	  option should improve the abutment of adjacent termi-
	  nals.  Not implemented on each platform.

     ----OOOO   Do not perform simple wire ordering at ends of the
	  channel.

     ----PPPP   Make spacer cells between the pad blocks. This option
	  implies the specification of a 'cir_chip_cell'.

     ----qqqq   Quiet mode: nothing is printed (except errors).

     ----rrrr   Place the i/o terminals rrrregularly on the chip boundary.
	  This option causes _s_e_q_u to divide these terminals
	  evenly on each side.	The spacing between the terminals



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	  will be approximately the same.

     ----RRRR   Risky spacing rules. Using this option the length of
	  the channel will be as short as possible. This may
	  cause some problems for the channel router some prob-
	  lems.

     ----ssss   Print detailed routing statistics.

     ----SSSS   Print detailed routing statistics and accurate wire
	  length data to a file called "<cell_name>.stat".

     ----xxxx   Fixed x-coordinate: Disables shift of blocks by com-
	  poser.

     ----yyyy   Fixed y-coordinate: No shift of blocks by channel
	  router.

     ----4444   No routing of last 4 (outer-) channels.

     ----CCCC <<<<cccciiiirrrr____ccccoooorrrreeee____nnnnaaaammmmeeee>>>>
	  This option specifies the name of the core cell in the
	  circuit view. By default sequ sets this name to
	  <flp_core_cel>'. This option implies the specification
	  of a <cir_chip_cell>.

     ----XXXX <<<<wwwwiiiiddddtttthhhh>>>>
	  Set the minimum width of the core_cell to <width>.

     ----YYYY <<<<hhhheeeeiiiigggghhhhtttt>>>>
	  Set the minimum height of the core_cell to <height>.

     ----oooo <<<<ffffllllpppp____nnnnaaaammmmeeee>>>>
	  This option forces _s_e_q_u to generate a placement called
	  "flp_name" in the floorplan view of the database.  It
	  can be useful for accurate placement feedback to
	  _i_p_p(1ICD) or _g_l_r_o_u_t_e(1ICD).

     ----pppp <<<<oooopppptttt>>>>
	  Send options to _g_c_r(1ICD).  The string <opt> will be
	  send to the channel router as option(s).

     ----GGGG <<<<tttteeeerrrrmmmmiiiinnnnaaaallll____nnnnaaaammmmeeee>>>>
	  Set the name of the first GND-power terminal.  This
	  terminal (which has to be either on the left or bottom
	  side of the father model) will be connected without
	  using poly-wires.

     ----VVVV <<<<tttteeeerrrrmmmmiiiinnnnaaaallll____nnnnaaaammmmeeee>>>>
	  Set the name of first VDD-power terminal.  This termi-
	  nal has to be either on the right or on the top side.




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     ----gggg <<<<tttteeeerrrrmmmmiiiinnnnaaaallll____nnnnaaaammmmeeee>>>>
	  Set the name of second GND-power terminal.  This termi-
	  nal will be placed on the opposite side of the first
	  gnd terminal.

     ----vvvv <<<<tttteeeerrrrmmmmiiiinnnnaaaallll____nnnnaaaammmmeeee>>>>
	  Set the name of second VDD-power terminal.

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _S_e_q_u is the control program for detailed routing.	It is the
     interface between the global router and the gridless channel
     router.  Starting from the output of the global router
     (_g_l_r_o_u_t_e 1ICD) it will construct the channels in the correct
     order and call the channel router to generate the wires in
     each of them.  The channel router _g_c_r (1ICD) will return the
     width of the channel and write a layout cell into the data-
     base.  _S_e_q_u keeps track of the translations and rotations
     involved.	Finally it will merge the layout cells of each
     channel into the layout view under the name ffffllllpppp____ccccoooorrrreeee____nnnnaaaammmmeeee ....
     If a <cir_chip_name> is specified, sequ will generate a pad
     ring.  The design rule file "Route_rules" is read from the
     project directory.  If, however, no such file is present,
     the default design rules file from the database will be
     read.

EEEEXXXXAAAAMMMMPPPPLLLLEEEE
     Let's assume you want to route a cell called 'processor'.
     In the layout and the circuit view the components (son
     cells) of 'processor' exist.  In the circuit view the nets
     (connections) between the components of 'processor' are
     defined.  Using the interactive placement program _i_p_p a
     placement (floorplan) called 'chip' was created.  This
     placement was stored in the floorplan view.  The processor
     has power nets called 'Gnd' and 'Vdd'.  The terminals of
     these nets are also called 'Gnd' and 'Vdd'.  The global
     routing and detailed routing can be performed by entering
     the following commands:

     % glroute -G Gnd -V Vdd chip processor
     % sequ -G Gnd -V Vdd chip

     ------ (sequ) reading core cell 'processor' from floorplan view ------

     ------ (sequ) routing channels ------
     ****** gcr H6
     ****** gcr V5
     ****** gcr H4
     ****** gcr V3
     ****** gcr H2
     ****** gcr V1

     ------ (sequ) channel routing complete ------



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     ------ (sequ) writing core cell 'processor' into layout view ------

     ------ (sequ) semoving temporary cells and files ------
     ------ (sequ) Program finished ------
     %

RRRREEEEMMMMAAAARRRRKKKKSSSS
     PPPPoooowwwweeeerrrr nnnneeeettttssss
     If no gnd or vdd terminals are specified, the power nets
     will contain polysilicon wires.  Notice that - in contrast
     to _g_l_r_o_u_t_e - the _n_a_m_e_s of the vdd and gnd terminals will
     have to be specified, nnnnooootttt the name of their net.  _S_e_q_u
     places the power terminals on the same side of the chip as
     they were placed in _i_p_p (but never on the same position).
     The gnd-terminals must be either on the left or on the bot-
     tom side and the vdd-terminals on the right of top side.
     For each power net, two terminals can be specified which
     will be connected without using poly wires.  The second
     power terminal will be placed automatically on the opposite
     side of the chip as the first power terminal.  The width of
     the power terminals will be adjusted according to width of
     the power wires.

     4444 oooouuuutttteeeerrrr cccchhhhaaaannnnnnnneeeellllssss If the '-4' option is supplied, the last 4
     channels will not be routed.  The terminals which are at
     that time on the edges of the father model will be 'lifted
     up'.  Terminals which belong to cells keep their original
     name.  Terminals which are at the end of a channel (gen-
     erated internally) will obtain the name of the net they
     belong to.  Notice that the father cell could contain a
     number of terminals which share the same name.

     ddddeeeettttaaaaiiiilllleeeedddd ppppllllaaaacccceeeemmmmeeeennnntttt
     The '-x' option disables the horizontal shift of blocks by
     the composer, while the '-y' fixes the width of all channels
     (if possible).  If both options are supplied, _s_e_q_u will
     attempt to make the final chip layout resemble the initial
     placement.  This will only work properly if the spacing
     between the blocks is about the same as the spacing required
     by the wires. Another way to perform detailed placement is
     by using the '-m' option.	In that case, a channel width
     estimator (_m_e_r(1ICD)) will attempt to find the best horizon-
     tal offset of the blocks.

     PPPPllllaaaacccceeeemmmmeeeennnntttt oooouuuuttttppppuuuutttt
     To feedback the final placement to _i_p_p, the '-o' option can
     be used.  A floorplan cell will be created in which the
     son-cells are placed on exactly the same place as in the
     layout cell.  If a floorplan cell with that name already
     exists, it will be overwritten.  This cell does not contain
     channels, so it will have to be re-routed globally.  The '-
     x' and '-y' options can be used successfully for this cell



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     because the spacing between the blocks is likely to be
     correct.

     TTTTeeeerrrrmmmmiiiinnnnaaaallll ppppllllaaaacccceeeemmmmeeeennnntttt
     _S_e_q_u will adjust the positions of the external terminals, in
     order to minimize the wiring in the 4 outer channels.  This
     is very useful for the generation of hierarchical building
     blocks.  By supplying the '-f' option this mechanism is dis-
     abled: In that case the spacing between the terminals on the
     chip boundaries will be the same as was entered in _i_p_p.  The
     '-r' option causes _s_e_q_u to spread the terminals evenly over
     the chip boundaries.

     TTTTeeeemmmmppppoooorrrraaaarrrryyyy ffffiiiilllleeeessss
     If, for some reasons, _s_e_q_u is aborted before the program was
     finished, the layout view of the database will contain a
     number of cells called H* and V*.	These cells contain the
     interconnect layout of the wires in a single channel.  The
     cells can be removed, as well as the channel router input-
     and output files in the project directory (called H*, V*,
     H*.out, V*.out and optionally H*.stat and V*.stat).  If
     these cells still exist the next time _s_e_q_u is called, the
     channel router will print a warning message indicating a
     cell called H* or V* already exists.  This will not cause
     any troubles because _s_e_q_u keeps track of the actual cell
     name.  By the way: by supplying the '-c' option all tem-
     porary cells will not be removed.

     ----llll ooooppppttttiiiioooonnnn br The '-l' option will also introduce poly wires
     in power nets.

     NNNNoooo ccccoooonnnnccccuuuurrrrrrrreeeennnnccccyyyy
     Never execute more than one _s_e_q_u at the time in the same
     project directory.

     SSSSttttaaaattttiiiissssttttiiiiccccssss
     The '-S' option causes _s_e_q_u to generate a file called
     "<cell_name>.stat" which contains the wire length of each
     net.  This file is constructed from the statistics files of
     each channel (which were generated by _g_c_r(1ICD)).

     LLLLaaaayyyyeeeerrrr ddddiiiirrrreeeeccccttttiiiioooonnnn
     The '-d' option enables 'global one directional routing'. If
     this option is supplied, the horizontal wires in the hor-
     izontal channels of the chip will be in METAL1.  The wires
     in the main direction of the vertical channels will be in
     the vertical layer specified in the design rule file
     "Route_rules" (3ICD).  The default vertical layer is POLY.
     In this way, many vias at the edges of the channels can be
     prevented. A special design rule file is required for this
     option: 'Route_rev'.  Sequ will complain and abort the the
     '-d' option if this file could not be found.  The rules in



		   The Nelsis IC Design System			5






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     'Route_rev' will be used by gcr for the VERTICAL channels.
     You must 'fake' the channel router by specifying reversed
     layers in this file: interchange the rules of poly and
     metal. The '-d' option will only work correctly for 2-layer
     routing.  Tests on the MCNC benchmark chips showed no great
     improvement with '-d'. However, for some double metal
     processes some gain could be expected.  This feature has not
     been tested extensively.

     CCCCeeeellllllll ssssiiiizzzzeeee
     Using the '-X <width>' and '-Y <height>' options the final
     size of the cell can be specified. Sequ will print a warning
     message if the cell does not fit within the specified area.

     BBBBoooonnnnddddiiiinnnngggg ppppaaaaddddssss ((((ffffiiiinnnnaaaallll cccchhhhiiiipppp aaaasssssssseeeemmmmbbbbllllyyyy))))
     The bonding pad ring can also be assembled by sequ. To
     achieve pad ring assembly a number of preparations must be
     performed.  A ''''cccchhhhiiiipppp'''' cccceeeellllllll must be created in the circuit
     view. This cell is the 'root' of the entire chip. It con-
     tains a single model call to the 'core' cell and model calls
     to the bonding pads.  The chip cell is used to assign bond-
     ing pads to specify the which terminal of the core cell is
     specified to which terminal of a bonding pad.

		    CIRCUIT

		     chip
		    /	 \
		   /	  \
		core	bonding_pads
	       / /	      blocks

     All bbbboooonnnnddddiiiinnnngggg ppppaaaadddd cccceeeellllllllssss should be present in the layout and
     circuit view (import them from a library if necessary). In
     order to achieve succesful assembly of the pad ring the
     bonding pad cells must fulfil a number of criteria.  First
     of all the following restrictions apply to the terminals
     which connect them to the 'core' (signal terminals): They
     must touch the bonding-box.  They must be on the same side.
     Sequ will rotate the bonding pad such that the terminal(s)
     are 'facing' the core terminals.  Do not place them exactly
     in a corner of the bonding pad. The terminals should also be
     present in the circuit view.  An arbitrary number of termi-
     nals is allowed on each bonding pad cell.	It is therefore
     allowed to merge a number of bonding pads into a larger
     block. In this way 'fixed' bonding pad positions can be
     achieved.	All terminals connecting to a single bonding pad
     cell must be connected to terminals placed on the same side
     of the core cell. For example, if a bonding pad contains the
     terminals for net 'a', 'b', and 'c' the terminals of those
     nets on the core cell must be placed on the same side.
     These restrictions do not apply to terminals which are not



6		   The Nelsis IC Design System






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     connected to the core.

     Sequ will place bonding pads at zero spacing. Therefore the
     bonding pads should be designed such that no design rule
     violations occur in that case. This can usually be achieved
     by simply adapting the size of the bounding box.

     The following restrictions apply to the 'chip' cell in the
     circuit view: The model call must contain exactly one
     instantiation of the core cell.  Different types of bonding
     pads are allowed.	All nets must contain exactly two termi-
     nals.  Of each net, one terminal must belong to the core and
     the other to a bonding pad.  In other words: a net between
     two pads is not allowed, as is a net between two terminals
     of the core cell.

     Notice that the chip cell is not present in the floorplan
     view.

     If this data is available pad ring assembly can be performed
     by sequ simply by specifying the name of the 'chip'-cell as
     second argument.

     It is even possible to make sequ fill the remaining space in
     the pad ring. In this way a 'power ring' can be assembled
     automatically. See the user's manual for more details.

AAAAUUUUTTTTHHHHOOOORRRRSSSS
     P. Groeneveld,
     H. Cai

FFFFIIIILLLLEEEESSSS
     Technology file:
     proj_dir/Route_rules      or
     IIIICCCCDDDDPPPPAAAATTTTHHHH/lib/process/_p_r_o_c_e_s_s__n_a_m_e/Route_rules

     Input files:
     proj_dir/floorplan/_c_e_l_l/info
     proj_dir/floorplan/_c_e_l_l/mc
     proj_dir/floorplan/_c_e_l_l/term
     proj_dir/floorplan/_c_e_l_l/chan
     proj_dir/layout/_c_e_l_l/info
     proj_dir/layout/_c_e_l_l/term

     Scratch files:
     H* and V* files (_g_c_r input/output channel files, see _g_c_r(1ICD))
     H* and V* cells (Temporary cells in the database generated by the channel router).

     Output files:
     proj_dir/layout/_c_e_l_l/box
     proj_dir/layout/_c_e_l_l/mc
     proj_dir/layout/_c_e_l_l/term



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     proj_dir/layout/_c_e_l_l/info

BBBBUUUUGGGGSSSS
     In some cases, warnings for single terminal power nets will
     be printed.  They can be ignored.

SSSSEEEEEEEE AAAALLLLSSSSOOOO
     H. Cai and P. Groeneveld, "Delft Placement and Routing Sys-
     tem User's Manual", The Nelsis IC Design System Documenta-
     tion, Delft, March 1988.
     gcr(1ICD),
     glroute(1ICD),
     ipp(1ICD),
     mer(1ICD),
     route_rules(3ICD).








































8		   The Nelsis IC Design System



