# Define SciTE settings for Verilog files.

# Verilog files
file.patterns.verilog=*.v;*.vh
filter.verilog=Verilog (verilog)|$(file.patterns.verilog)|

lexer.$(file.patterns.verilog)=verilog

word.chars.verilog=$(chars.alpha)$(chars.numeric)_`$#
word.characters.$(file.patterns.verilog)=$(word.chars.verilog)

calltip.verilog.word.characters=$(chars.alpha)$(chars.numeric)_$

comment.block.verilog=//~
#comment.block.at.line.start.verilog=1
comment.stream.start.verilog=/*
comment.stream.end.verilog=*/
comment.box.start.verilog=/*
comment.box.middle.verilog= *
comment.box.end.verilog= */

fold.verilog.flags=0

#statement.lookback.$(file.patterns.verilog)=20
#block.start.$(file.patterns.verilog)=5 begin
#block.end.$(file.patterns.verilog)=5 end
#statement.indent.$(file.patterns.verilog)=5 always case casex casez else for if while \
#module function task

indent.maintain.$(file.patterns.verilog)=1;

preprocessor.symbol.$(file.patterns.verilog)=`
preprocessor.start.$(file.patterns.verilog)=ifdef ifndef
preprocessor.middle.$(file.patterns.verilog)=else
preprocessor.end.$(file.patterns.verilog)=endif

keywordclass.verilog= \
always and assign automatic \
begin buf bufif0 bufif1 \
case casex casez cell cmos config \
deassign default defparam design disable \
edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
for force forever fork function \
generate genvar \
highz0 highz1 \
if ifnone incdir include initial inout input instance integer \
join \
large liblist library localparam \
macromodule medium module \
nand negedge nmos nor noshowcancelled not notif0 notif1 \
or output \
parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
unsigned use \
vectored \
wait wand weak0 weak1 while wire wor \
xnor xor

keywords.$(file.patterns.verilog)=$(keywordclass.verilog)

keywords3.$(file.patterns.verilog)= \
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
$bitstoreal \
$countdrivers \
$display $displayb $displayh $displayo \
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
$getpattern \
$history $hold \
$incsave $input $itor \
$key \
$list $log \
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
$nochange $nokey $nolog \
$period $printtimescale \
$q_add $q_exam $q_full $q_initialize $q_remove \
$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
$test$plusargs $time $timeformat $timeskew \
$ungetc $unsigned \
$value$plusargs \
$width $writeb $writeh $write $writeo

# Verilog styles

# Default
style.verilog.32=$(font.base)
# White space
style.verilog.0=fore:#808080
# Comment
style.verilog.1=$(colour.code.comment.box),$(font.code.comment.box)
# Line Comment
style.verilog.2=$(colour.code.comment.line),$(font.code.comment.line)
# Bang comment
style.verilog.3=fore:#3F7F3F,$(font.code.comment.line),back:#E0F0FF,eolfilled
# Number
style.verilog.4=$(colour.number)
# Keyword
style.verilog.5=$(colour.keyword),bold
# Double quoted string
style.verilog.6=$(colour.string),$(font.string.literal)
# Keyword2
style.verilog.7=fore:#007F7F
# System tasks
style.verilog.8=fore:#804020
# Preprocessor
style.verilog.9=$(colour.preproc)
# Operators
#style.verilog.10=$(colour.operator),bold
style.verilog.10=fore:#007070,bold
# Identifiers
style.verilog.11=
# End of line where string is not closed
style.verilog.12=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
# User defined identifiers and tasks
style.verilog.19=fore:#804020,$(font.code.comment.doc)
# Braces are only matched in operator style
braces.verilog.style=10

