//
// This file is automatically generated by the 'pikdb' utility
// from Microchip .dev files. Do not edit.
// in case of errors, please contact the author : 
//             alain.gibaud@free.fr
//

deviceRecord devDB[] = { 
{
"p10f200"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"1(1-0)"
"{Unused\n}"

, 0x00, 0xFF // program memory 
, 0x100, 0x103 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0xFF, 0xFF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p10f202"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"1(1-0)"
"{Unused\n}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p10f204"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"1(1-0)"
"{Unused\n}"

, 0x00, 0xFF // program memory 
, 0x100, 0x103 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0xFF, 0xFF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p10f206"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"1(1-0)"
"{Unused\n}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p10f220"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"MCPU[1]"
"{Master Clear Pull-up Resistor Enable\n"
"1=Disabled\n0=Enabled\n""}"
"IOFSCS[0]"
"{Internal Oscillator Speed Select\n"
"1=8 MHz\n0=4 MHz\n""}"

, 0x00, 0xFF // program memory 
, 0x100, 0x103 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0xFF, 0xFF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p10f222"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=Functions as Master Clear\n0=Functions as GP3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"MCPU[1]"
"{Master Clear Pull-up Resistor Enable\n"
"1=Disabled\n0=Enabled\n""}"
"IOFSCS[0]"
"{Internal Oscillator Speed Select\n"
"1=8 MHz\n0=4 MHz\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12c508a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12c508"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12c509a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12c509"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12c671"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"MCLRE[7]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[6-5]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12c672"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"MCLRE[7]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[6-5]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x7FF, 0x7FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12ce518"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12ce519"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12ce673"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"MCLRE[7]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[6-5]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12ce674"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"MCLRE[7]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[6-5]"
"{Code Protect\n"
"11=Off\n01=200:3FE\n00=All\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x7FF, 0x7FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12cr509a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"1(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=External RC\n00=LP\n01=XT\n10=Internal RC\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12f508"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC\n10=INTOSC\n01=XT\n00=LP\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x1FF, 0x1FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12f509"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(11-5)"
"{Unused\n}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC\n10=INTOSC\n01=XT\n00=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12f510"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xfff)
"0(11-6)"
"{Unused\n}"
"IOSCFS[5]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz INTOSC Speed\n0=4 MHz INTOSC Speed\n""}"
"MCLRE[4]"
"{Master Clear Enable\n"
"1=RB3/MCLR Functions as MCLR\n0=RB3/MCLR Functions as RB3\n""}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC[1-0]"
"{Oscillator Select\n"
"11=EXTRC With 1 ms DRT\n10=INTRC With 1 ms DRT\n01=XT Osc With 18 ms DRT\n00=LP Osc With 18 ms DRT\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 12 // bits per word 
}
,
{
"p12f609"
, 0x2240  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12f615"
, 0x2180  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12f629"
, 0xf80  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BG[13-12]"
"{Bandgap Calibration Bits\n"
"11=Highest Bandgap Voltage\n00=Lowest Bandgap Voltage\n""}"
"0(11-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[7]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12f635"
, 0xfa0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13)"
"{Unused\n}"
"WUR[12]"
"{Wake-Up Reset\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2009 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p12f675"
, 0xfc0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BG[13-12]"
"{Bandgap Calibration Bits\n"
"11=Highest Bandgap Voltage\n00=Lowest Bandgap Voltage\n""}"
"0(11-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[7]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12f683"
, 0x460  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p12hv609"
, 0x2280  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p12hv615"
, 0x21a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c432"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c433"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FE\n010101=200:7FE\n000000=All\n""}"
"MCLRE[7]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[6-5]"
"{Code Protect\n"
"11=Off\n10=400:7FE\n01=200:7FE\n00=All\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x7FF, 0x7FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c505"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-6]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c54c"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c54"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c554"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"X(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c557"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=0400h-07FFh Code Protected\n010101=0200h-07FFh Code Protected\n000000=0000h-07FFh Code Protected\n""}"
"X(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0400h-07FFh Code Protected\n01=0200h-07FFh Code Protected\n00=0000h-07FFh Code Protected\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c558"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"X(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c55a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c55"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c56a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c56"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c57c"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c57"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c58a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c58b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c620a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c620"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c621a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n010101=200:3FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c621"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n010101=200:3FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c622a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c622"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c62a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c62b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c63a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c63"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c642"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"PARITY[7]"
"{Parity\n"
"1=On\n0=Off\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c64a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=0400:07FF\n010101=0200:07FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0400:07FF\n01=0200:07FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c65a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c65b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c662"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"PARITY[7]"
"{Parity\n"
"1=On\n0=Off\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c66"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c67"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c710"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-7]"
"{Code Protect\n"
"1111111=Off\n0000000=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c711"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-7]"
"{Code Protect\n"
"1111111=Off\n0000000=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c712"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n010101=200:3FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c715"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"PARITY[7]"
"{Parity\n"
"1=On\n0=Off\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c716"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c717"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=ER CLKOUT\n110=ER I/O\n101=INTRC CLKOUT\n100=INTRC I/O\n011=EC I/O\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c71"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"1(13-5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=On\n0=Off\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c72a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c72"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c73a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c73b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c745"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"X(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=E4\n00=HS\n01=EC\n10=H4\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c74a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c74b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c765"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"X(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=E4\n00=HS\n01=EC\n10=H4\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c76"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c770"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=ER CLKOUT\n110=ER I/O\n101=INTRC CLKOUT\n100=INTRC I/O\n011=EC I/O\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c771"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=ER CLKOUT\n110=ER I/O\n101=INTRC CLKOUT\n100=INTRC I/O\n011=EC I/O\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c773"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c774"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c77"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=1000:1FFF\n010101=800:1FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1000:1FFF\n01=800:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c781"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=RC CLKOUT\n110=RC I/O\n101=INTRC CLKOUT\n100=INTRC I/O\n011=EC I/O\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c782"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"BODENV[11-10]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"CP[9-8]"
"{Code Protect\n"
"11=Off\n00=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=RC CLKOUT\n110=RC I/O\n101=INTRC CLKOUT\n100=INTRC I/O\n011=EC I/O\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c923"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c924"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7-6)"
"{Unused\n}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c925"
, 0x140  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0000:07FF\n01=0000:0EFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16c926"
, 0x100  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0000:0FFF\n01=0000:1EFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16ce623"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16ce624"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n010101=200:3FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16ce625"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr54a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr54c"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr54"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr56a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr57c"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr58b"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-12)"
"{Unused\n}"
"CP[11-3]"
"{Code Protect\n"
"111111111=Off\n000000000=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr620a"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n000000=On\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr62"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr63"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr64"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr65"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=800:FFF\n010101=400:FFF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=800:FFF\n01=400:FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr72"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-8]"
"{Code Protect\n"
"111111=Off\n101010=400:7FF\n010101=200:7FF\n000000=All\n""}"
"1(7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr73"
, 0xc80  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr74"
, 0xcc0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr76"
, 0xc00  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr77"
, 0xc40  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr83"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-4]"
"{Code Protect\n"
"1111111111=Program/Data Off\n1111110111=Program Off/Data On\n0000001000=Program On/Data Off\n0000000000=Program/Data On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16cr84"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-4]"
"{Code Protect\n"
"1111111111=Program/Data Off\n1111110111=Program Off/Data On\n0000001000=Program On/Data Off\n0000000000=Program/Data On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f1937"
, 0x1380  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x0, 0x5fff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f505"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-6)"
"{Unused\n}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC w/ RB4 on OSC2\n101=INTOSC RC Clockout\n100=INTOSC w/ RB4 on OSC2\n011=EC w/ RB4 on OSC2\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f506"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-7)"
"{Unused\n}"
"IOSCFS[6]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz INTOSC Speed\n0=4 MHz INTOSC Speed\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=RB3/MCLR Functions as MCLR\n0=RB3/MCLR Functions as RB3\n""}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC[2-0]"
"{Oscillator Select\n"
"000=LP Osc With 18 ms DRT\n001=XT Osc With 18 ms DRT\n010=HS Osc With 18 ms DRT\n011=EC Osc With RB4 and 18 ms DRT\n100=INTRC With RB4 and 1 ms DRT\n101=INTRC With CLKOUT and 1 ms DRT\n110=EXTRC With RB4 1 ms DRT\n111=EXTRC With CLKOUT 1 ms DRT\n""}"

, 0x00, 0x3FF // program memory 
, 0x400, 0x403 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f526"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-8)"
"{Unused\n}"
"CPDF[7]"
"{Code Protect bit - Flash Data Memory\n"
"1=Off\n0=On\n""}"
"IOSCFS[6]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz INTOSC Speed\n0=4 MHz INTOSC Speed\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=RB3/MCLR functions as MCLR\n0=RB3/MCLR functions as RB3, MCLR internally tied to Vdd\n""}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"000=LP oscillator and 18 ms DRT\n001=XT oscillator and 18 ms DRT\n010=HS oscillator and 18 ms DRT\n011=EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT\n100=INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT\n101=INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT\n110=EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT\n111=EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT\n""}"

, 0x00, 0x3FF // program memory 
, 0x440, 0x443 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, 0x3ff, 0x3ff // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f54"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f57"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f59"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"0(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x000, 0x7FF // program memory 
, 0x800, 0x803 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f610"
, 0x2260  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f616"
, 0x1240  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f627a"
, 0x1040  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n1=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n0=EC\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n10=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n01=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n00=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n11=EC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f627"
, 0x7a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n01=200:3FF\n00=All\n""}"
"1(9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=ER CLKOUT\n1=ER I/O\n1=INTRC CLKOUT\n1=INTRC I/O\n0=EC I/O\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=ER CLKOUT\n10=ER I/O\n01=INTRC CLKOUT\n00=INTRC I/O\n11=EC I/O\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f628a"
, 0x1060  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n1=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n0=EC\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n10=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n01=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n00=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n11=EC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f628"
, 0x7c0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"CP[11-10]"
"{Code Protect\n"
"11=Off\n10=400:7FF\n01=200:7FF\n00=All\n""}"
"1(9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=ER CLKOUT\n1=ER I/O\n1=INTRC CLKOUT\n1=INTRC I/O\n0=EC I/O\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=ER CLKOUT\n10=ER I/O\n01=INTRC CLKOUT\n00=INTRC I/O\n11=EC I/O\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f630"
, 0x10c0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BG[13-12]"
"{Bandgap Calibration Bits\n"
"11=Highest Bandgap Voltage\n00=Lowest Bandgap Voltage\n""}"
"0(11-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[7]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f631"
, 0x1420  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f636"
, 0x10a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13)"
"{Unused\n}"
"WUR[12]"
"{Wake-Up Reset\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBOREN Disabled\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n01=SBOREN controls BOR function\n00=BOD and SBOREN disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2009 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f639"
, 0x10a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13)"
"{Unused\n}"
"WUR[12]"
"{Wake-Up Reset\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2009 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f648a"
, 0x1100  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"X(12-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=Enabled\n0=Disabled\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n1=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n1=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n0=EC\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC: CLKOUT on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n10=RC: I/O on RA6/OSC2/CLKOUT, RC on RA7/OSC1/CLKIN\n01=INTOSC: CLKOUT on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n00=INTOSC: I/O on RA6/OSC2/CLKOUT, I/O on RA7/OSC1/CLKIN\n11=EC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f676"
, 0x10e0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BG[13-12]"
"{Bandgap Calibration Bits\n"
"11=Highest Bandgap Voltage\n00=Lowest Bandgap Voltage\n""}"
"0(11-9)"
"{Unused\n}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[7]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x3FF, 0x3FF // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f677"
, 0x1440  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x7ff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f684"
, 0x1080  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f685"
, 0x4a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0000, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f687"
, 0x1320  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0000, 0x07FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f688"
, 0x1180  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f689"
, 0x1340  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0000, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f690"
, 0x1400  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0000, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, 0x2008, 0x2008 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f716"
, 0x1140  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=All\n""}"
"1(12-8)"
"{Unused\n}"
"BODENV[7]"
"{Brown Out Voltage\n"
"1=VBOR set to 4.0V\n0=VBOR set to 2.5V\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5-4)"
"{Unused\n}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f722"
, 0x1880  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"DEBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"PLLEN[12]"
"{INTOSC PLLEN Enable Bit\n"
"1=16MHz\n0=500KHz\n""}"
"WDTCS[11]"
"{Watchdog Timer Clock Select\n"
"1=Standard Watchdog Timer is selected\n0=Low Power Watchdog Timer is selected\n""}"
"BORV[10]"
"{Brown-out Reset Voltage Selection\n"
"1=1.9V\n0=2.5V\n""}"
"BOREN[9-8]"
"{Brown Out Reset Enable\n"
"00=BOR disabled\n01=BOR disabled\n10=BOR enabled in run, disabled in sleep\n11=BOR Enabled\n""}"
"RES[7]"
"{Reserved\n"
"1=Reserved\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"nPWRTE[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"0(13-6)"
"{Unused\n}"
"VCAPEN[5-4]"
"{Voltage Regulator Capacitor Enable bits\n"
"11=All VCAP pin functions are disabled\n10=VCAP functionality is enabled on RA6\n01=VCAP functionality is enabled on RA5\n00=VCAP functionality is enabled on RA0\n""}"
"0(3-0)"
"{Unused\n}"

, 0x0, 0x7ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f723"
, 0x1860  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"DEBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"PLLEN[12]"
"{INTOSC PLLEN Enable Bit\n"
"1=16MHz\n0=500KHz\n""}"
"WDTCS[11]"
"{Watchdog Timer Clock Select\n"
"1=Standard Watchdog Timer is selected\n0=Low Power Watchdog Timer is selected\n""}"
"BORV[10]"
"{Brown-out Reset Voltage Selection\n"
"1=1.9V\n0=2.5V\n""}"
"BOREN[9-8]"
"{Brown Out Reset Enable\n"
"00=BOR disabled\n01=BOR disabled\n10=BOR enabled in run, disabled in sleep\n11=BOR Enabled\n""}"
"RES[7]"
"{Reserved\n"
"1=Reserved\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"nPWRTE[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"0(13-6)"
"{Unused\n}"
"VCAPEN[5-4]"
"{Voltage Regulator Capacitor Enable bits\n"
"11=All VCAP pin functions are disabled\n10=VCAP functionality is enabled on RA6\n01=VCAP functionality is enabled on RA5\n00=VCAP functionality is enabled on RA0\n""}"
"0(3-0)"
"{Unused\n}"

, 0x0, 0xfff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f724"
, 0x1840  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"DEBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"PLLEN[12]"
"{INTOSC PLLEN Enable Bit\n"
"1=16MHz\n0=500KHz\n""}"
"WDTCS[11]"
"{Watchdog Timer Clock Select\n"
"1=Standard Watchdog Timer is selected\n0=Low Power Watchdog Timer is selected\n""}"
"BORV[10]"
"{Brown-out Reset Voltage Selection\n"
"1=1.9V\n0=2.5V\n""}"
"BOREN[9-8]"
"{Brown Out Reset Enable\n"
"00=BOR disabled\n01=BOR disabled\n10=BOR enabled in run, disabled in sleep\n11=BOR Enabled\n""}"
"RES[7]"
"{Reserved\n"
"1=Reserved\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"nPWRTE[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"0(13-6)"
"{Unused\n}"
"VCAPEN[5-4]"
"{Voltage Regulator Capacitor Enable bits\n"
"11=All VCAP pin functions are disabled\n10=VCAP functionality is enabled on RA6\n01=VCAP functionality is enabled on RA5\n00=VCAP functionality is enabled on RA0\n""}"
"0(3-0)"
"{Unused\n}"

, 0x0, 0xfff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f726"
, 0x1820  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"DEBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"PLLEN[12]"
"{INTOSC PLLEN Enable Bit\n"
"1=16MHz\n0=500KHz\n""}"
"WDTCS[11]"
"{Watchdog Timer Clock Select\n"
"1=Standard Watchdog Timer is selected\n0=Low Power Watchdog Timer is selected\n""}"
"BORV[10]"
"{Brown-out Reset Voltage Selection\n"
"1=1.9V\n0=2.5V\n""}"
"BOREN[9-8]"
"{Brown Out Reset Enable\n"
"00=BOR disabled\n01=BOR disabled\n10=BOR enabled in run, disabled in sleep\n11=BOR Enabled\n""}"
"RES[7]"
"{Reserved\n"
"1=Reserved\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"nPWRTE[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"0(13-6)"
"{Unused\n}"
"VCAPEN[5-4]"
"{Voltage Regulator Capacitor Enable bits\n"
"11=All VCAP pin functions are disabled\n10=VCAP functionality is enabled on RA6\n01=VCAP functionality is enabled on RA5\n00=VCAP functionality is enabled on RA0\n""}"
"0(3-0)"
"{Unused\n}"

, 0x0, 0x1fff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f727"
, 0x1800  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"DEBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"PLLEN[12]"
"{INTOSC PLLEN Enable Bit\n"
"1=16MHz\n0=500KHz\n""}"
"WDTCS[11]"
"{Watchdog Timer Clock Select\n"
"1=Standard Watchdog Timer is selected\n0=Low Power Watchdog Timer is selected\n""}"
"BORV[10]"
"{Brown-out Reset Voltage Selection\n"
"1=1.9V\n0=2.5V\n""}"
"BOREN[9-8]"
"{Brown Out Reset Enable\n"
"00=BOR disabled\n01=BOR disabled\n10=BOR enabled in run, disabled in sleep\n11=BOR Enabled\n""}"
"RES[7]"
"{Reserved\n"
"1=Reserved\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"nPWRTE[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"FOSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"0(13-6)"
"{Unused\n}"
"VCAPEN[5-4]"
"{Voltage Regulator Capacitor Enable bits\n"
"11=All VCAP pin functions are disabled\n10=VCAP functionality is enabled on RA6\n01=VCAP functionality is enabled on RA5\n00=VCAP functionality is enabled on RA0\n""}"
"0(3-0)"
"{Unused\n}"

, 0x0, 0x1fff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f72"
, 0xa0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f737"
, 0xba0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"CCP2MUX[12]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"X(10-9)"
"{Unused\n}"
"BODENV[8-7]"
"{Brown Out Voltage\n"
"11=Set to 2.0V\n10=Set to 2.7V\n01=Set to 4.2V\n00=Set to 4.5V\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enable\n0=Disable\n""}"
"MCLRE[5]"
"{RE3/MCLR Pin Function Select\n"
"1=MCLR\n0=RE3\n""}"
"OSC[4]"
"{Oscillator\n"
"1=EXTRC as Clock Out\n1=EXTRC as Port I/O\n1=INTRC as Clock Out\n1=INTRC as Port I/O\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC as Clock Out\n10=EXTRC as Port I/O\n01=INTRC as Clock Out\n00=INTRC as Port I/O\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-7)"
"{Unused\n}"
"BORSEN[6]"
"{BOR Software Enable\n"
"1=Enabled\n0=Disabled\n""}"
"1(5-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f73"
, 0x600  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f747"
, 0xbe0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"CCP2MUX[12]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"X(10-9)"
"{Unused\n}"
"BODENV[8-7]"
"{Brown Out Voltage\n"
"11=Set to 2.0V\n10=Set to 2.7V\n01=Set to 4.2V\n00=Set to 4.5V\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enable\n0=Disable\n""}"
"MCLRE[5]"
"{RE3/MCLR Pin Function Select\n"
"1=MCLR\n0=RE3\n""}"
"OSC[4]"
"{Oscillator\n"
"1=EXTRC as Clock Out\n1=EXTRC as Port I/O\n1=INTRC as Clock Out\n1=INTRC as Port I/O\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC as Clock Out\n10=EXTRC as Port I/O\n01=INTRC as Clock Out\n00=INTRC as Port I/O\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-7)"
"{Unused\n}"
"BORSEN[6]"
"{BOR Software Enable\n"
"1=Enabled\n0=Disabled\n""}"
"1(5-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f74"
, 0x620  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f767"
, 0xea0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"CCP2MUX[12]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"X(10-9)"
"{Unused\n}"
"BODENV[8-7]"
"{Brown Out Voltage\n"
"11=Set to 2.0V\n10=Set to 2.7V\n01=Set to 4.2V\n00=Set to 4.5V\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enable\n0=Disable\n""}"
"MCLRE[5]"
"{RE3/MCLR Pin Function Select\n"
"1=MCLR\n0=RE3\n""}"
"OSC[4]"
"{Oscillator\n"
"1=EXTRC as Clock Out\n1=EXTRC as Port I/O\n1=INTRC as Clock Out\n1=INTRC as Port I/O\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC as Clock Out\n10=EXTRC as Port I/O\n01=INTRC as Clock Out\n00=INTRC as Port I/O\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-7)"
"{Unused\n}"
"BORSEN[6]"
"{BOR Software Enable\n"
"1=Enabled\n0=Disabled\n""}"
"1(5-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f76"
, 0x640  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f777"
, 0xde0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"CCP2MUX[12]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"X(10-9)"
"{Unused\n}"
"BODENV[8-7]"
"{Brown Out Voltage\n"
"11=Set to 2.0V\n10=Set to 2.7V\n01=Set to 4.2V\n00=Set to 4.5V\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=Enable\n0=Disable\n""}"
"MCLRE[5]"
"{RE3/MCLR Pin Function Select\n"
"1=MCLR\n0=RE3\n""}"
"OSC[4]"
"{Oscillator\n"
"1=EXTRC as Clock Out\n1=EXTRC as Port I/O\n1=INTRC as Clock Out\n1=INTRC as Port I/O\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC as Clock Out\n10=EXTRC as Port I/O\n01=INTRC as Clock Out\n00=INTRC as Port I/O\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-7)"
"{Unused\n}"
"BORSEN[6]"
"{BOR Software Enable\n"
"1=Enabled\n0=Disabled\n""}"
"1(5-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f77"
, 0x660  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-7)"
"{Unused\n}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5)"
"{Unused\n}"
"CP[4]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 2 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f785"
, 0x1200  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=EXTRC: CLKOUT on RA4, RC on RA5\n110=EXTRCIO: I/O on RA4, RC on RA5\n101=INTOSC: CLKOUT on RA4, I/O on RA5\n100=INTOSCIO: I/O on RA4/RA5\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f818"
, 0x4c0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Disabled\n0=Enabled - All protected\n""}"
"CCP1MUX[12]"
"{CCP1 Mux\n"
"1=RB2\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Disabled\n10=0x0000-0x1FF Write Protected, 0x200-0x3FF may be modified by EECON\n01=0x0000-0x3FF Write Protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{MCLR Select Bit\n"
"1=RA5 is MCLR\n0=RA5 is digital I/O, MCLR tied to VDD\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=EXTRC-RA6 is CLKOUT\n1=EXTRC-RA6 is Port I/O\n1=INTRC-RA6 is CLKOUT\n1=INTRC-RA6 is Port I/O\n0=EXTCLK-RA6 is Port I/O\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC-RA6 is CLKOUT\n10=EXTRC-RA6 is Port I/O\n01=INTRC-RA6 is CLKOUT\n00=INTRC-RA6 is Port I/O\n11=EXTCLK-RA6 is Port I/O\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f819"
, 0x4e0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Disabled\n0=Enabled - All protected\n""}"
"CCP1MUX[12]"
"{CCP1 Mux\n"
"1=RB2\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Disabled\n10=0x0000-0x1FF Write Protected, 0x200-0x7FF may be modified by EECON\n01=0x0000-0x3FF Write Protected, 0x400-0x7FF may be modified by EECON\n00=0x0000-0x5FF Write Protected, 0x600-0x7FF may be modified by EECON\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{MCLR Select Bit\n"
"1=RA5 is MCLR\n0=RA5 is digital I/O, MCLR tied to VDD\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=EXTRC-RA6 is CLKOUT\n1=EXTRC-RA6 is Port I/O\n1=INTRC-RA6 is CLKOUT\n1=INTRC-RA6 is Port I/O\n0=EXTCLK-RA6 is Port I/O\n0=HS\n0=XT\n0=LP\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC-RA6 is CLKOUT\n10=EXTRC-RA6 is Port I/O\n01=INTRC-RA6 is CLKOUT\n00=INTRC-RA6 is Port I/O\n11=EXTCLK-RA6 is Port I/O\n10=HS\n01=XT\n00=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f83"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-4]"
"{Code Protect\n"
"1111111111=Off\n0000000000=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f84a"
, 0x560  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-4]"
"{Code Protect\n"
"1111111111=Off\n0000000000=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f84"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-4]"
"{Code Protect\n"
"1111111111=Off\n0000000000=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x3FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f870"
, 0xd00  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f871"
, 0xd20  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f872"
, 0x8e0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n00=On\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x3f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f873a"
, 0xe40  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12)"
"{Unused\n}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Off\n10=0h to FFh write Protected\n01=0h to 3FFh write Protected\n00=0h to 7FFh write Protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5-4)"
"{Unused\n}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f873"
, 0x960  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=0F00:0FFF\n01=0800:0FFF\n00=All\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0F00:0FFF\n01=0800:0FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f874a"
, 0xe60  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12)"
"{Unused\n}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Off\n10=0h to FFh write Protected\n01=0h to 3FFh write Protected\n00=0h to 7FFh write Protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5-4)"
"{Unused\n}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f874"
, 0x920  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=0F00:0FFF\n01=0800:0FFF\n00=All\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=0F00:0FFF\n01=0800:0FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f876a"
, 0xe00  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12)"
"{Unused\n}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Off\n10=0h to FFh write Protected\n01=0h to 7FFh write Protected\n00=0h to FFFh write Protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5-4)"
"{Unused\n}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f876"
, 0x9e0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=1F00:1FFF\n01=1000:1FFF\n00=All\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1F00:1FFF\n01=1000:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f877a"
, 0xe20  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"1(12)"
"{Unused\n}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protection Off\n10=0h to FFh write Protected\n01=0h to 7FFh write Protected\n00=0h to FFFh write Protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"1(5-4)"
"{Unused\n}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f877"
, 0x9a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13-12]"
"{Code Protect\n"
"11=Off\n10=1F00:1FFF\n01=1000:1FFF\n00=All\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"1(10)"
"{Unused\n}"
"WRT_ENABLE[9]"
"{Flash Program Write\n"
"1=Enabled\n0=Disabled\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"CP[5-4]"
"{Code Protect\n"
"11=Off\n10=1F00:1FFF\n01=1000:1FFF\n00=All\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f87"
, 0x720  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=All\n""}"
"CCP1MUX[12]"
"{CCP1 Mux\n"
"1=RB0\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protect Off\n10=0000 to 00FF write protected\n01=0000 to 07FF write protected\n00=0000 to 0FFF write protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{RA5/MCLR Pin Function Select\n"
"1=MCLR\n0=RA5\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=EXTRC-OSC2 as Clock Out\n1=EXTRC-OSC2 as RA6\n1=INTRC-OSC2 as Clock Out\n1=INTRC-OSC2 as RA6\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC-OSC2 as Clock Out\n10=EXTRC-OSC2 as RA6\n01=INTRC-OSC2 as Clock Out\n00=INTRC-OSC2 as RA6\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f882"
, 0x2000  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BACKBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[12]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"1(13-11)"
"{Unused\n}"
"WRT[10-9]"
"{Self Write Enable\n"
"00=0000-07ff prot\n01=0000-03ff prot\n10=0000-00ff prot\n11=No protection\n""}"
"BOR4V[8]"
"{Brown Out Reset Sel Bit\n"
"0=Brown out at 2.1V\n1=Brown out at 4.0V\n""}"
"1(7-0)"
"{Unused\n}"

, 0x0, 0x7ff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0x7f+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f883"
, 0x2020  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BACKBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[12]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"1(13-11)"
"{Unused\n}"
"WRT[10-9]"
"{Self Write Enable\n"
"00=0000-07ff prot\n01=0000-03ff prot\n10=0000-00ff prot\n11=No protection\n""}"
"BOR4V[8]"
"{Brown Out Reset Sel Bit\n"
"0=Brown out at 2.1V\n1=Brown out at 4.0V\n""}"
"1(7-0)"
"{Unused\n}"

, 0x0, 0xfff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f884"
, 0x2040  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BACKBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[12]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"1(13-11)"
"{Unused\n}"
"WRT[10-9]"
"{Self Write Enable\n"
"00=0000-07ff prot\n01=0000-03ff prot\n10=0000-00ff prot\n11=No protection\n""}"
"BOR4V[8]"
"{Brown Out Reset Sel Bit\n"
"0=Brown out at 2.1V\n1=Brown out at 4.0V\n""}"
"1(7-0)"
"{Unused\n}"

, 0x0, 0xfff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f886"
, 0x2060  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BACKBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[12]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"1(13-11)"
"{Unused\n}"
"WRT[10-9]"
"{Self Write Enable\n"
"00=0000-0fff prot\n01=0000-07ff prot\n10=0000-00ff prot\n11=No protection\n""}"
"BOR4V[8]"
"{Brown Out Reset Sel Bit\n"
"0=Brown out at 2.1V\n1=Brown out at 4.0V\n""}"
"1(7-0)"
"{Unused\n}"

, 0x0, 0x1fff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f887"
, 0x2080  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"BACKBUG[13]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"LVP[12]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"0=RE3 is digital input\n1=/MCLR is external\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

";"

// CONFIG2 (0x2008)
"1(13-11)"
"{Unused\n}"
"WRT[10-9]"
"{Self Write Enable\n"
"00=0000-0fff prot\n01=0000-07ff prot\n10=0000-00ff prot\n11=No protection\n""}"
"BOR4V[8]"
"{Brown Out Reset Sel Bit\n"
"0=Brown out at 2.1V\n1=Brown out at 4.0V\n""}"
"1(7-0)"
"{Unused\n}"

, 0x0, 0x1fff // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f88"
, 0x760  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"CP[13]"
"{Code Protect\n"
"1=Off\n0=All\n""}"
"CCP1MUX[12]"
"{CCP1 Mux\n"
"1=RB0\n0=RB3\n""}"
"BACKBUG[11]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_ENABLE[10-9]"
"{Flash Program Write\n"
"11=Write Protect Off\n10=0000 to 00FF write protected\n01=0000 to 07FF write protected\n00=0000 to 0FFF write protected\n""}"
"CPD[8]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"LVP[7]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[6]"
"{Brown Out Detect\n"
"1=On\n0=Off\n""}"
"MCLRE[5]"
"{RA5/MCLR Pin Function Select\n"
"1=MCLR\n0=RA5\n""}"
"OSC-2[4]"
"{Oscillator\n"
"1=EXTRC-OSC2 as Clock Out\n1=EXTRC-OSC2 as RA6\n1=INTRC-OSC2 as Clock Out\n1=INTRC-OSC2 as RA6\n0=EXTCLK as Port IO\n0=LP\n0=XT\n0=HS\n""}"
"PUT[3]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=EXTRC-OSC2 as Clock Out\n10=EXTRC-OSC2 as RA6\n01=INTRC-OSC2 as Clock Out\n00=INTRC-OSC2 as RA6\n11=EXTCLK as Port IO\n00=LP\n01=XT\n10=HS\n""}"

";"

// CONFIG2 (0x2008)
"1(13-2)"
"{Unused\n}"
"IESO[1]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[0]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"

, 0x00, 0xFFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2008 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f913"
, 0x13e0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xFF+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f914"
, 0x13c0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x00, 0x0FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xFF+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f916"
, 0x13a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xFF+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f917"
, 0x1380  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xFF+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16f946"
, 0x1460  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"0(13)"
"{Unused\n}"
"BACKBUG[12]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"FCMEN[11]"
"{Fail Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal-External Switch Over\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"11=BOD Enabled, SBODEN Disabled\n10=BOD Enabled While Running, Disabled In Sleep, SBODEN Disabled\n01=Controlled by SBODEN\n00=BOD And SBODEN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{MCLR Pin Function Select\n"
"1=Normal Function\n0=Alternate Function\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"000=LP\n001=XT\n010=HS\n011=EC\n100=INTOSCIO\n101=INTOSC\n110=EXTRCIO\n111=EXTRC\n""}"

, 0x00, 0x1FFF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xFF+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 8 // write buffer size 

, 14 // bits per word 
}
,
{
"p16hv540"
, -1U // non autodetectable 
// config bits descriptor
,
// CONFIG (0xFFF)
"X(13-4)"
"{Unused\n}"
"CP[3]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"WDT[2]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[1-0]"
"{Oscillator\n"
"11=RC\n00=LP\n01=XT\n10=HS\n""}"

, 0x00, 0x1FF // program memory 
, 0x200, 0x203 // user ID data
, -1, -1 // EEPROM data
, 0xFFF, 0xFFF // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16hv610"
, 0x22a0  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD disabled\n01=BOD disabled\n10=BOD enabled in run, disabled in sleep\n11=BOD Enabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x0, 0x3ff // program memory 
, 0x2000, 0x2003 // user ID data
, -1, -1 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 1 // write buffer size 

, 14 // bits per word 
}
,
{
"p16hv616"
, 0x1260  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"X(13-10)"
"{Unused\n}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"IOSCFS[7]"
"{Internal Oscillator Frequency Select\n"
"1=8 MHz\n0=4 MHz\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=External RC Clockout\n110=External RC No Clock\n101=Internal RC Clockout\n100=Internal RC No Clock\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p16hv785"
, 0x1220  // device ID 

// config bits descriptor
,
// CONFIG (0x2007)
"1(13-12)"
"{Unused\n}"
"FCMEN[11]"
"{Monitor Clock Fail-safe\n"
"1=Enabled\n0=Disabled\n""}"
"IESO[10]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"BODEN[9-8]"
"{Brown Out Detect\n"
"00=BOD and SBOREN disabled\n01=SBOREN controls BOR function\n10=BOD enabled in run, disabled in sleep, SBOREN disabled\n11=BOD Enabled, SBOREN Disabled\n""}"
"CPD[7]"
"{Data EE Read Protect\n"
"1=Off\n0=On\n""}"
"CP[6]"
"{Code Protect\n"
"1=Off\n0=On\n""}"
"MCLRE[5]"
"{Master Clear Enable\n"
"1=External\n0=Internal\n""}"
"PUT[4]"
"{Power Up Timer\n"
"1=Off\n0=On\n""}"
"WDT[3]"
"{Watchdog Timer\n"
"1=On\n0=Off\n""}"
"OSC[2-0]"
"{Oscillator\n"
"111=EXTRC: CLKOUT on RA4, RC on RA5\n110=EXTRCIO: I/O on RA4, RC on RA5\n101=INTOSC: CLKOUT on RA4, I/O on RA5\n100=INTOSCIO: I/O on RA4/RA5\n011=EC\n010=HS\n001=XT\n000=LP\n""}"

, 0x00, 0x7FF // program memory 
, 0x2000, 0x2003 // user ID data
, 0x0+0x2100, 0xff+0x2100 // EEPROM data
, 0x2007, 0x2007 // CONFIG data
, -1, -1 // calibration data words
, 4 // write buffer size 

, 14 // bits per word 
}
,
{
"p18c242"
, 0x8320  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"1(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"X(7-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c252"
, 0x8220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"1(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"X(7-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c442"
, 0x8300  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"1(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"X(7-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c452"
, 0x8200  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"1(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"X(7-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c601"
, 0x8120  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-10)"
"{Unused\n}"
"OSC[9-8]"
"{Oscillator\n"
"11=RC\n10=HS\n01=EC\n00=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7)"
"{Unused\n}"
"BUS[6]"
"{Bus Width\n"
"1=16 Bit\n0=8 Bit\n""}"
"0(5-1)"
"{Unused\n}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, -1, -1 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c658"
, 0x80a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"RES1[15]"
"{Reserved\n"
"1=Reserved\n""}"
"RES2[14]"
"{Reserved\n"
"1=Reserved\n""}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"0(7-2)"
"{Unused\n}"
"RES1[1]"
"{Reserved\n"
"1=Reserved\n""}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c801"
, 0x8100  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-10)"
"{Unused\n}"
"OSC[9-8]"
"{Oscillator\n"
"11=RC\n10=HS\n01=EC\n00=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7)"
"{Unused\n}"
"BUS[6]"
"{Bus Width\n"
"1=16 Bit\n0=8 Bit\n""}"
"0(5-1)"
"{Unused\n}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, -1, -1 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18c858"
, 0x80e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"RES1[15]"
"{Reserved\n"
"1=Reserved\n""}"
"RES2[14]"
"{Reserved\n"
"1=Reserved\n""}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L (0x300000)
"CP[7-0]"
"{Code Protect\n"
"11111111=Disabled\n00000000=Enabled\n""}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"0(7-2)"
"{Unused\n}"
"RES1[1]"
"{Reserved\n"
"1=Reserved\n""}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x300007/2 // CONFIG data
, -1, -1 // calibration data words
, -1 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1220"
, 0x87e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 000800-000FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-0007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x0FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1230"
, 0x9e00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1010=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-12)"
"{Unused\n}"
"T1OSCMX[11]"
"{T1OSC Mux bit\n"
"1=T1OSC reside on RA6 and RA7\n0=T1OSC reside on RB3 and RB3\n0=FLTA is muxed onto RA5\n0=FLTA is muxed onto RA7\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L (0x300004)
"0(7-5)"
"{Unused\n}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Select bits\n"
"11=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n10=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n01=Boot Block size is 512 W\n00=Boot Block size is 256 W\n""}"
"ENICPORT[3]"
"{ICD/ICSP Port Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 001000-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-000FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x0FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1231"
, 0x9e80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1010=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-12)"
"{Unused\n}"
"T1OSCMX[11]"
"{T1OSC Mux bit\n"
"1=T1OSC reside on RA6 and RA7\n0=T1OSC reside on RB3 and RB3\n0=FLTA is muxed onto RA5\n0=FLTA is muxed onto RA7\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L (0x300004)
"0(7-5)"
"{Unused\n}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Select bits\n"
"11=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n10=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n01=Boot Block size is 512 W\n00=Boot Block size is 256 W\n""}"
"ENICPORT[3]"
"{ICD/ICSP Port Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 001000-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-000FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x0FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1320"
, 0x87c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 001000-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-000FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1330"
, 0x9e20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1010=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-12)"
"{Unused\n}"
"T1OSCMX[11]"
"{T1OSC Mux bit\n"
"1=T1OSC reside on RA6 and RA7\n0=T1OSC reside on RB2 and RB3\n0=FLTA is muxed onto RA5\n0=FLTA is muxed onto RA7\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L (0x300004)
"0(7-5)"
"{Unused\n}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Select bits\n"
"11=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n10=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n01=Boot Block size is 512 W\n00=Boot Block size is 256 W\n""}"
"ENICPORT[3]"
"{ICD/ICSP Port Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 001000-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-000FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f1331"
, 0x9ea0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1010=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RA5 input disabled\n0=MCLR disabled, RA5 input enabled\n""}"
"0(14-12)"
"{Unused\n}"
"T1OSCMX[11]"
"{T1OSC Mux bit\n"
"1=T1OSC reside on RA6 and RA7\n0=T1OSC reside on RB2 and RB3\n0=FLTA is muxed onto RA5\n0=FLTA is muxed onto RA7\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L (0x300004)
"0(7-5)"
"{Unused\n}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Select bits\n"
"11=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n10=Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0\n01=Boot Block size is 512 W\n00=Boot Block size is 256 W\n""}"
"ENICPORT[3]"
"{ICD/ICSP Port Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 001000-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-000FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f13k20"
, 0xcf40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"PCLKEN[13]"
"{Primary Clock Enable bit\n"
"1=Primary Clock enabled\n0=Primary Clock disabled\n""}"
"PLLEN[12]"
"{4 X PLL Enable bit\n"
"1=Oscillator multiplied by 4\n0=Oscillator used directly\n""}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBDIV[5]"
"{USB Clock Selection bit\n"
"1=USB clock comes from the OSC1/OSC2 divided by 2\n0=USB clock comes directly from the OSC1/OSC2 Oscillator block, no divide\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Selection bits\n"
"11=CPU system clock divided by 4\n10=CPU system clock divided by 3\n01=CPU system clock divided by 2\n00=No CPU system clock divide\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDTEN[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{Voltage Regulator Enable bit\n"
"0=Voltage Regulator is disabled\n1=Voltage Regulator is enabled\n""}"
"BORV[4-3]"
"{Brown Out Voltage\n"
"11=1.9V\n10=2.2V\n01=2.7V\n00=3.0V\n""}"
"BOREN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"nPWRTEN[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start-up\n"
"1=HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize\n0=The system clock is held off until the HFINTOSC is stable\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-4)"
"{Unused\n}"
"BBSIZ[3]"
"{Boot BLock Size Select bit\n"
"1=1 kW boot block size\n0=512 W boot block size\n""}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xfff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f13k50"
, 0xc740  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"PCLKEN[13]"
"{Primary Clock Enable bit\n"
"1=Primary Clock enabled\n0=Primary Clock disabled\n""}"
"PLLEN[12]"
"{4 X PLL Enable bit\n"
"1=Oscillator multiplied by 4\n0=Oscillator used directly\n""}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBDIV[5]"
"{USB Clock Selection bit\n"
"1=USB clock comes from the OSC1/OSC2 divided by 2\n0=USB clock comes directly from the OSC1/OSC2 Oscillator block, no divide\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Selection bits\n"
"11=CPU system clock divided by 4\n10=CPU system clock divided by 3\n01=CPU system clock divided by 2\n00=No CPU system clock divide\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDTEN[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{Voltage Regulator Enable bit\n"
"0=Voltage Regulator is disabled\n1=Voltage Regulator is enabled\n""}"
"BORV[4-3]"
"{Brown Out Voltage\n"
"11=1.9V\n10=2.2V\n01=2.7V\n00=3.0V\n""}"
"BOREN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"nPWRTEN[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start-up\n"
"1=HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize\n0=The system clock is held off until the HFINTOSC is stable\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-4)"
"{Unused\n}"
"BBSIZ[3]"
"{Boot BLock Size Select bit\n"
"1=2 kW boot block size\n0=1 kW boot block size\n""}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x7f/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f14k20"
, 0xcf20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"PCLKEN[13]"
"{Primary Clock Enable bit\n"
"1=Primary Clock enabled\n0=Primary Clock disabled\n""}"
"PLLEN[12]"
"{4 X PLL Enable bit\n"
"1=Oscillator multiplied by 4\n0=Oscillator used directly\n""}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBDIV[5]"
"{USB Clock Selection bit\n"
"1=USB clock comes from the OSC1/OSC2 divided by 2\n0=USB clock comes directly from the OSC1/OSC2 Oscillator block, no divide\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Selection bits\n"
"11=CPU system clock divided by 4\n10=CPU system clock divided by 3\n01=CPU system clock divided by 2\n00=No CPU system clock divide\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDTEN[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{Voltage Regulator Enable bit\n"
"0=Voltage Regulator is disabled\n1=Voltage Regulator is enabled\n""}"
"BORV[4-3]"
"{Brown Out Voltage\n"
"11=1.9V\n10=2.2V\n01=2.7V\n00=3.0V\n""}"
"BOREN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"nPWRTEN[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start-up\n"
"1=HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize\n0=The system clock is held off until the HFINTOSC is stable\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-4)"
"{Unused\n}"
"BBSIZ[3]"
"{Boot BLock Size Select bit\n"
"1=1 kW boot block size\n0=512 W boot block size\n""}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f14k50"
, 0xc760  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"PCLKEN[13]"
"{Primary Clock Enable bit\n"
"1=Primary Clock enabled\n0=Primary Clock disabled\n""}"
"PLLEN[12]"
"{4 X PLL Enable bit\n"
"1=Oscillator multiplied by 4\n0=Oscillator used directly\n""}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBDIV[5]"
"{USB Clock Selection bit\n"
"1=USB clock comes from the OSC1/OSC2 divided by 2\n0=USB clock comes directly from the OSC1/OSC2 Oscillator block, no divide\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Selection bits\n"
"11=CPU system clock divided by 4\n10=CPU system clock divided by 3\n01=CPU system clock divided by 2\n00=No CPU system clock divide\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDTEN[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{Voltage Regulator Enable bit\n"
"0=Voltage Regulator is disabled\n1=Voltage Regulator is enabled\n""}"
"BORV[4-3]"
"{Brown Out Voltage\n"
"11=1.9V\n10=2.2V\n01=2.7V\n00=3.0V\n""}"
"BOREN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"nPWRTEN[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start-up\n"
"1=HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize\n0=The system clock is held off until the HFINTOSC is stable\n""}"
"0(10-8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-4)"
"{Unused\n}"
"BBSIZ[3]"
"{Boot BLock Size Select bit\n"
"1=2 kW boot block size\n0=1 kW boot block size\n""}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2220"
, 0x8580  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled\n0=MCLR Disabled\n""}"
"0(14-10)"
"{Unused\n}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_1[1]"
"{Code Protect 000800-000FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-0007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_1[1]"
"{Table Read Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x0FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2221"
, 0xa160  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"FOSC[11-8]"
"{Oscillator Select\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BORV[4-3]"
"{Brown-out Reset Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BOREN[2-1]"
"{Brown-out Reset Enable\n"
"11=Enabled In Hardware, SBOREN Ignored\n10=Enabled When Not In SLEEP, SBOREN Ignored\n01=Controlled By SBOREN\n00=Disabled, SBOREN Ignored\n""}"
"PWRTEN[0]"
"{Power-up Timer Enable\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR Pin Enable\n"
"1=MCLR Enabled, RG5 Input Pin Disabled\n0=MCLR Disabled, RG5 Input Pin Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc Enable\n"
"1=Low Power Consumption, Low Noise Immunity\n0=High Power Consumption, High Noise Immunity\n""}"
"PBADEN[9]"
"{Port B A/D Enable\n"
"1=Port B[4:0] Are Analog Inputs on Reset\n0=Port B[4:0] Are Digital I/O on Reset\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed With RC1\n0=CCP2 I/O Muxed With RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size Select\n"
"11=1 KW (512 W)\n10=1 KW (512 W)\n01=512 W (512 W)\n00=256 W (256 W)\n""}"
"ENICPORT[3]"
"{Dedicated In-Circuit PORT Enable\n"
"0=Disabled\n""}"
"LVP[2]"
"{Low Voltage Programming Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Code Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Write Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Write Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Write Protect Config Bits\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT1[1]"
"{Write Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"WRT0[0]"
"{Write Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR1[1]"
"{Table Read Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR0[0]"
"{Table Read Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2320"
, 0x8500  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled\n0=MCLR Disabled\n""}"
"0(14-10)"
"{Unused\n}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 001800-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 001000-0017FF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 000800-000FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-0007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2321"
, 0xa120  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"FOSC[11-8]"
"{Oscillator Select\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BORV[4-3]"
"{Brown-out Reset Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BOREN[2-1]"
"{Brown-out Reset Enable\n"
"11=Enabled In Hardware, SBOREN Ignored\n10=Enabled When Not In SLEEP, SBOREN Ignored\n01=Controlled By SBOREN\n00=Disabled, SBOREN Ignored\n""}"
"PWRTEN[0]"
"{Power-up Timer Enable\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR Pin Enable\n"
"1=MCLR Enabled, RG5 Input Pin Disabled\n0=MCLR Disabled, RG5 Input Pin Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc Enable\n"
"1=Low Power Consumption, Low Noise Immunity\n0=High Power Consumption, High Noise Immunity\n""}"
"PBADEN[9]"
"{Port B A/D Enable\n"
"1=Port B[4:0] Are Analog Inputs on Reset\n0=Port B[4:0] Are Digital I/O on Reset\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed With RC1\n0=CCP2 I/O Muxed With RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size Select\n"
"11=1 KW (512 W)\n10=1 KW (512 W)\n01=512 W (512 W)\n00=256 W (256 W)\n""}"
"ENICPORT[3]"
"{Dedicated In-Circuit PORT Enable\n"
"0=Disabled\n""}"
"LVP[2]"
"{Low Voltage Programming Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Code Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Write Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Write Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Write Protect Config Bits\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT1[1]"
"{Write Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"WRT0[0]"
"{Write Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR1[1]"
"{Table Read Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR0[0]"
"{Table Read Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2331"
, 0x88e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-14)"
"{Unused\n}"
"WINEN[13]"
"{Watchdog Timer Window\n"
"1=Disabled\n0=Enabled\n""}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=Undefined\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RE3 input disabled\n0=RE3 input enabled, MCLR disabled\n""}"
"0(14-13)"
"{Unused\n}"
"EXCLKMX[12]"
"{TMR0/T5CKI EXT CLK Mux\n"
"0=TMR0/T5CKI external clock input is multiplexed with RD0\n1=TMR0/T5CKI external clock input is multiplexed with RC3\n""}"
"PWM4MX[11]"
"{PWM4 Mux\n"
"1=PWM4 output muxed w/ RB5\n0=PWM4 output muxed w/ RD5\n""}"
"SSPMX[10]"
"{SSP I/O Mux\n"
"0=SPI not assigned\n1=SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively.\n""}"
"0(9)"
"{Unused\n}"
"FLTAMX[8]"
"{FLTA Mux\n"
"1=FLTA input muxed with RC1\n0=FLTA input muxed with RD4\n""}"


// CONFIG3L (0x300004)
"0(7-6)"
"{Unused\n}"
"T1OSCMX[5]"
"{Timer1 OSC\n"
"1=Low Power\n0=Legacy\n""}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2410"
, 0x9160  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"0(15)"
"{Unused\n}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n0=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2420"
, 0x9140  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2423"
, 0x9150  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f242"
, 0x8480  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2431"
, 0x88c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-14)"
"{Unused\n}"
"WINEN[13]"
"{Watchdog Timer Window\n"
"1=Disabled\n0=Enabled\n""}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=Undefined\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RE3 input disabled\n0=RE3 input enabled, MCLR disabled\n""}"
"0(14-13)"
"{Unused\n}"
"EXCLKMX[12]"
"{TMR0/T5CKI EXT CLK Mux\n"
"0=TMR0/T5CKI external clock input is multiplexed with RD0\n1=TMR0/T5CKI external clock input is multiplexed with RC3\n""}"
"PWM4MX[11]"
"{PWM4 Mux\n"
"1=PWM4 output muxed w/ RB5\n0=PWM4 output muxed w/ RD5\n""}"
"SSPMX[10]"
"{SSP I/O Mux\n"
"0=SPI not assigned\n1=SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively.\n""}"
"0(9)"
"{Unused\n}"
"FLTAMX[8]"
"{FLTA Mux\n"
"1=FLTA input muxed with RC1\n0=FLTA input muxed with RD4\n""}"


// CONFIG3L (0x300004)
"0(7-6)"
"{Unused\n}"
"T1OSCMX[5]"
"{Timer1 OSC\n"
"1=Low Power\n0=Legacy\n""}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2439"
, 0x8480  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"RES1[13]"
"{Reserved\n"
"1=Reserved\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n010=HS\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2450"
, 0xa420  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n0=2 KW\n0=1 KW\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"0(15)"
"{Unused\n}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"0(15)"
"{Unused\n}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2455"
, 0x9260  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x5FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2458"
, 0xaa60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x5fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2480"
, 0x9ae0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5)"
"{Unused\n}"
"BBSIZ[4]"
"{Boot Block Size Select\n"
"1=2 KW\n0=1 KW\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f248"
, 0x8800  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f24j10"
, 0x9d00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x3ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x3ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f24j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x3ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x3ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x3fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x3ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f24j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x3ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x3ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x3fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x3ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f24k20"
, 0xa0a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=1.8V\n10=2.3V\n01=2.8V\n00=3.1V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start\n"
"1=HFINTOSC is not delayed\n0=HFINTOSC is delayed until oscillator is stable(IOFS=1)\n""}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2510"
, 0x9120  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2515"
, 0x8ce0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2520"
, 0x9100  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2523"
, 0x9110  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2525"
, 0x8cc0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f252"
, 0x8400  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2539"
, 0x8400  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"RES1[13]"
"{Reserved\n"
"1=Reserved\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n010=HS\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2550"
, 0x9240  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2553"
, 0xaa40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2580"
, 0x9ac0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5)"
"{Unused\n}"
"BBSIZ[4]"
"{Boot Block Size Select\n"
"1=2 KW\n0=1 KW\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2585"
, 0x8ee0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2586"
, 0x8e60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f258"
, 0x8840  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f25j10"
, 0x9c00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f25j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x7ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x7fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x7ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f25j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x7ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x7fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x7ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f25k20"
, 0xa060  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=1.8V\n10=2.3V\n01=2.8V\n00=3.1V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start\n"
"1=HFINTOSC is not delayed\n0=HFINTOSC is delayed until oscillator is stable(IOFS=1)\n""}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2610"
, 0x8ca0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2620"
, 0x8c80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2680"
, 0x8ec0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2682"
, 0xa700  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x13fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f2685"
, 0xa720  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f26j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0xfffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0xffff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0xfffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f26j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0xfffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0xffff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0xfffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f26k20"
, 0xa020  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=1.8V\n10=2.3V\n01=2.8V\n00=3.1V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start\n"
"1=HFINTOSC is not delayed\n0=HFINTOSC is delayed until oscillator is stable(IOFS=1)\n""}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4220"
, 0x85a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_1[1]"
"{Code Protect 000800-000FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-0007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES2[3]"
"{Reserved\n"
"1=Reserved\n""}"
"RES1[2]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_1[1]"
"{Table Read Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x0FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4221"
, 0xa140  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"FOSC[11-8]"
"{Oscillator Select\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BORV[4-3]"
"{Brown-out Reset Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BOREN[2-1]"
"{Brown-out Reset Enable\n"
"11=Enabled In Hardware, SBOREN Ignored\n10=Enabled When Not In SLEEP, SBOREN Ignored\n01=Controlled By SBOREN\n00=Disabled, SBOREN Ignored\n""}"
"PWRTEN[0]"
"{Power-up Timer Enable\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR Pin Enable\n"
"1=MCLR Enabled, RG5 Input Pin Disabled\n0=MCLR Disabled, RG5 Input Pin Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc Enable\n"
"1=Low Power Consumption, Low Noise Immunity\n0=High Power Consumption, High Noise Immunity\n""}"
"PBADEN[9]"
"{Port B A/D Enable\n"
"1=Port B[4:0] Are Analog Inputs on Reset\n0=Port B[4:0] Are Digital I/O on Reset\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed With RC1\n0=CCP2 I/O Muxed With RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size Select\n"
"11=1 KW (512 W)\n10=1 KW (512 W)\n01=512 W (512 W)\n00=256 W (256 W)\n""}"
"ENICPORT[3]"
"{Dedicated In-Circuit PORT Enable\n"
"1=Enabled\n0=Disabled\n""}"
"LVP[2]"
"{Low Voltage Programming Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Code Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Write Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Write Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Write Protect Config Bits\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT1[1]"
"{Write Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"WRT0[0]"
"{Write Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR1[1]"
"{Table Read Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR0[0]"
"{Table Read Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4320"
, 0x8520  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 001800-001FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 001000-0017FF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 000800-000FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000200-0007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4321"
, 0xa100  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"FOSC[11-8]"
"{Oscillator Select\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BORV[4-3]"
"{Brown-out Reset Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BOREN[2-1]"
"{Brown-out Reset Enable\n"
"11=Enabled In Hardware, SBOREN Ignored\n10=Enabled When Not In SLEEP, SBOREN Ignored\n01=Controlled By SBOREN\n00=Disabled, SBOREN Ignored\n""}"
"PWRTEN[0]"
"{Power-up Timer Enable\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR Pin Enable\n"
"1=MCLR Enabled, RG5 Input Pin Disabled\n0=MCLR Disabled, RG5 Input Pin Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc Enable\n"
"1=Low Power Consumption, Low Noise Immunity\n0=High Power Consumption, High Noise Immunity\n""}"
"PBADEN[9]"
"{Port B A/D Enable\n"
"1=Port B[4:0] Are Analog Inputs on Reset\n0=Port B[4:0] Are Digital I/O on Reset\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed With RC1\n0=CCP2 I/O Muxed With RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size Select\n"
"11=1 KW (512 W)\n10=1 KW (512 W)\n01=512 W (512 W)\n00=256 W (256 W)\n""}"
"ENICPORT[3]"
"{Dedicated In-Circuit PORT Enable\n"
"1=Enabled\n0=Disabled\n""}"
"LVP[2]"
"{Low Voltage Programming Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Code Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Write Protect Data EEPROM\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Write Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Write Protect Config Bits\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT1[1]"
"{Write Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"WRT0[0]"
"{Write Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot Block\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR1[1]"
"{Table Read Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR0[0]"
"{Table Read Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4331"
, 0x88a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-14)"
"{Unused\n}"
"WINEN[13]"
"{Watchdog Timer Window\n"
"1=Disabled\n0=Enabled\n""}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=Undefined\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RE3 input disabled\n0=RE3 input enabled, MCLR disabled\n""}"
"0(14-13)"
"{Unused\n}"
"EXCLKMX[12]"
"{TMR0/T5CKI EXT CLK Mux\n"
"0=TMR0/T5CKI external clock input is multiplexed with RD0\n1=TMR0/T5CKI external clock input is multiplexed with RC3\n""}"
"PWM4MX[11]"
"{PWM4 Mux\n"
"1=PWM4 output muxed w/ RB5\n0=PWM4 output muxed w/ RD5\n""}"
"SSPMX[10]"
"{SSP I/O Mux\n"
"0=SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively.\n1=SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively.\n""}"
"0(9)"
"{Unused\n}"
"FLTAMX[8]"
"{FLTA Mux\n"
"1=FLTA input muxed with RC1\n0=FLTA input muxed with RD4\n""}"


// CONFIG3L (0x300004)
"0(7-6)"
"{Unused\n}"
"T1OSCMX[5]"
"{Timer1 OSC\n"
"1=Low Power\n0=Legacy\n""}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4410"
, 0x90e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4420"
, 0x90c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4423"
, 0x90d0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f442"
, 0x84a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4431"
, 0x8880  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-14)"
"{Unused\n}"
"WINEN[13]"
"{Watchdog Timer Window\n"
"1=Disabled\n0=Enabled\n""}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=Undefined\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR enabled, RE3 input disabled\n0=RE3 input enabled, MCLR disabled\n""}"
"0(14-13)"
"{Unused\n}"
"EXCLKMX[12]"
"{TMR0/T5CKI EXT CLK Mux\n"
"1=TMR0/T5CKI external clock input is multiplexed with RC3\n0=TMR0/T5CKI external clock input is multiplexed with RD0\n""}"
"PWM4MX[11]"
"{PWM4 Mux\n"
"1=PWM4 output muxed w/ RB5\n0=PWM4 output muxed w/ RD5\n""}"
"SSPMX[10]"
"{SSP I/O Mux\n"
"1=SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively.\n0=SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively.\n""}"
"0(9)"
"{Unused\n}"
"FLTAMX[8]"
"{FLTA Mux\n"
"1=FLTA input muxed with RC1\n0=FLTA input muxed with RD4\n""}"


// CONFIG3L (0x300004)
"0(7-6)"
"{Unused\n}"
"T1OSCMX[5]"
"{Timer1 OSC\n"
"1=Low Power\n0=Legacy\n""}"
"HPOL[4]"
"{High-Side Transistors Polarity\n"
"1=PWM 1, 3, 5, and 7 are active high\n0=PWM 1, 3, 5, and 7 are active low\n""}"
"LPOL[3]"
"{Low-Side Transistors Polarity\n"
"1=PWM 0, 2, 4 and 6 are active high\n0=PWM 0, 2, 4 and 6 are active low\n""}"
"PWMPIN[2]"
"{PWM Output Pin Reset\n"
"1=PWM outputs disabled upon RESET\n0=PWM outputs drive active states upon RESET\n""}"
"0(1-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 03000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 02000-02FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4439"
, 0x84a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"RES1[13]"
"{Reserved\n"
"1=Reserved\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n010=HS\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4450"
, 0xa400  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n0=2 KW\n0=1 KW\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"0(15)"
"{Unused\n}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"0(15)"
"{Unused\n}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4455"
, 0x9220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x5FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4458"
, 0xaa20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x5fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4480"
, 0x9aa0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5)"
"{Unused\n}"
"BBSIZ[4]"
"{Boot Block Size Select\n"
"1=2 KW\n0=1 KW\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f448"
, 0x8820  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f44j10"
, 0x9d20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x3ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x3ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f44j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x3ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x3ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x3fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x3ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f44j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x3ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x3ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x3fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x3ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f44k20"
, 0xa080  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=1.8V\n10=2.3V\n01=2.8V\n00=3.1V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start\n"
"1=HFINTOSC is not delayed\n0=HFINTOSC is delayed until oscillator is stable(IOFS=1)\n""}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect Block 1\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect Block 0\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 01000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-00FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4510"
, 0x90a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4515"
, 0x8c60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4520"
, 0x9080  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4523"
, 0x9090  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4525"
, 0x8c40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f452"
, 0x8420  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4539"
, 0x8420  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"RES1[13]"
"{Reserved\n"
"1=Reserved\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n010=HS\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"RES1[3]"
"{Reserved\n"
"1=Reserved\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4550"
, 0x9200  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4553"
, 0xaa00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1110=HS: HS+PLL, USB-HS\n1100=HS: USB-HS\n1011=INTOSC: USB-HS\n1010=INTOSC: USB-XT\n1001=INTOSC: INTOSC+CLK0(RA6), USB-EC\n1000=INTOSC: INTOSC+RA6, USB-EC\n0111=EC: EC+PLL, EC+PLL+CLKO(RA6), USB-EC\n0110=EC: EC+PLL, EC+PLL+RA6, USB-EC\n0101=EC: EC+CLKO(RA6), USB-EC\n0100=EC: EC+RA6, USB-EC\n0010=XT: XT+PLL, USB-XT\n0000=XT: USB-XT\n""}"


// CONFIG1L (0x300000)
"0(7-6)"
"{Unused\n}"
"USBPLL[5]"
"{Full-Speed USB Clock Source Selection\n"
"1=Clock src from 96MHz PLL/2\n0=Clock src from OSC1/OSC2\n""}"
"CPUDIV[4-3]"
"{CPU System Clock Postscaler\n"
"11=[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]\n10=[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]\n01=[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]\n00=[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]\n""}"
"PLLDIV[2-0]"
"{96MHz PLL Prescaler\n"
"111=Divide by 12 (48MHz input)\n110=Divide by 10 (40MHz input)\n101=Divide by 6 (24MHz input)\n100=Divide by 5 (20MHz input)\n011=Divide by 4 (16MHz input)\n010=Divide by 3 (12MHz input)\n001=Divide by 2 (8MHz input)\n000=No Divide (4MHz input)\n""}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-6)"
"{Unused\n}"
"VREGEN[5]"
"{USB Voltage Regulator\n"
"1=Enabled\n0=Disabled\n""}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"ENICPORT[5]"
"{Dedicated In-Circuit Port (ICD/ICSP)\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4580"
, 0x9a80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5)"
"{Unused\n}"
"BBSIZ[4]"
"{Boot Block Size Select\n"
"1=2 KW\n0=1 KW\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4585"
, 0x8ea0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4586"
, 0x8e20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f458"
, 0x8860  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f45j10"
, 0x9c20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f45j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x7ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x7fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x7ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f45j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0x7ffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0x7fff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0x7ffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f45k20"
, 0xa040  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=1.8V\n10=2.3V\n01=2.8V\n00=3.1V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-12)"
"{Unused\n}"
"HFOFST[11]"
"{HFINTOSC Fast Start\n"
"1=HFINTOSC is not delayed\n0=HFINTOSC is delayed until oscillator is stable(IOFS=1)\n""}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 01800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 01000-017FF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 00800-00FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-007FF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4610"
, 0x8c20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4620"
, 0x8c00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4680"
, 0x8e80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4682"
, 0xa740  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x13fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f4685"
, 0xa760  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4> and <1:0> configured as analog inputs on RESET\n0=PORTB<4> and <1:0> configured as digital I/O on RESET\n""}"
"0(8)"
"{Unused\n}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f46j11"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0xfffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0xffff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0xfffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f46j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protection bit\n"
"1=Program memory is not code-protected\n0=Program memory is code-protected\n""}"
"CPUDIV[9-8]"
"{CPU System Clock Postscaler\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"DEBUG[7]"
"{Background Debug\n"
"1=Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins\n0=Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Instruction set extension and Indexed Addressing mode enabled\n0=Instruction set extension and Indexed Addressing mode disabled (Legacy mode)\n""}"
"STVR[5]"
"{Stack Overflow/Underflow Reset Enable bit\n"
"1=Reset on stack overflow/underflow enabled\n0=Reset on stack overflow/underflow disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL Prescaler Selection bits\n"
"111=No prescale (4 MHz oscillator input drives PLL directly)\n110=Divide by 2 (8 MHz oscillator input)\n101=Divide by 3 (12 MHz oscillator input)\n100=Divide by 4 (16 MHz oscillator input)\n011=Divide by 5 (20 MHz oscillator input)\n010=Divide by 6 (24 MHz oscillator input)\n001=Divide by 10 (40 MHz oscillator input)\n000=Divide by 12 (48 MHz oscillator input)\n""}"
"WDTEN[0]"
"{Watchdog Timer Enable bit\n"
"1=WDT enabled\n0=WDT disabled (control is placed on SWDTEN bit)\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscaler Select bits\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit\n"
"0=Two-Speed Start-up disabled\n1=Two-Speed Start-up enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable bit\n"
"0=Fail-Safe Clock Monitor disabled\n1=Fail-Safe Clock Monitor enabled\n""}"
"0(5)"
"{Unused\n}"
"LPT1OSC[4]"
"{Low-Power Timer1 Oscillator Enable bit\n"
"1=Timer1 oscillator configured for low-power operation\n0=Timer1 oscillator configured for higher power operation\n""}"
"T1DIG[3]"
"{Secondary Clock Source T1OSCEN Enforcement\n"
"1=Secondary Oscillator clock source may be selected\n0=Secondary Oscillator clock source may not be selected\n""}"
"OSC[2-0]"
"{Oscillator Selection bits\n"
"111=EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB\n110=EC Oscillator with clock out on RA6, EC used by USB\n101=HS oscillator, PLL enabled, HSPLL used by USB\n100=HS oscillator, HS used by USB\n011=INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB\n010=INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB\n001=Internal oscillator, CLKOUT on RA6 and port function on RA7\n000=Internal oscillator, port function on RA6 and RA7 \n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address mask\n"
"1=7 Bit address masking\n0=5 Bit address masking\n""}"
"0(10-9)"
"{Unused\n}"
"IOL1WAY[8]"
"{IOLOCK One-Way Set Enable bit\n"
"1=The IOLOCK bit (PPSCON<0>) can be set once,\n0=The IOLOCK bit (PPSCON<0>) can be set and cleared as needed\n""}"


// CONFIG3L (0xfffc)
"DSWDTPS[7-4]"
"{Deep Sleep Watchdog Timer Postscale Select bits\n"
"1111=1:2,147,483,648 (25.7 days)\n1110=1:536,870,912 (6.4 days)\n1101=1:134,217,728 (38.5 hours)\n1100=1:33,554,432 (9.6 hours)\n1011=1:8,388,608 (2.4 hours)\n1010=1:2,097,152 (36 minutes)\n1001=1:524,288 (9 minutes)\n1000=1:131,072 (135 seconds)\n0111=1:32,768 (34 seconds)\n0110=1:8,192 (8.5 seconds)\n0101=1:2,048 (2.1 seconds)\n0100=1:512 (528 ms)\n0011=1:128 (132 ms)\n0010=1:32 (33 ms)\n0001=1:8 (8.3 ms)\n0000=1:2 (2.1 ms)\n""}"
"DSWDTEN[3]"
"{Deep Sleep Watchdog Timer Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"DSBOREN[2]"
"{Deep Sleep BOR Enable bit\n"
"1=Zero-Power BOR enabled in Deep Sleep\n0=Zero-Power BOR disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)\n""}"
"RTCOSC[1]"
"{RTCC Reference Clock Select bit\n"
"1=RTCC uses T1OSC/T1CKI as reference clock\n0=RTCC uses INTOSC/INTRC as reference clock\n""}"
"DSWDTOSC[0]"
"{DSWDT Reference Clock Select bit\n"
"1=DSWDT uses INTOSC/INTRC as reference clock\n0=DSWDT uses T1OSC/T1CKI as reference clock\n""}"

";"

// CONFIG4H (0xffff)
"RESERVED[15-12]"
"{\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"WPDIS[8]"
"{Write Protect Disable bit\n"
"1=WPFP[5:0], WPEND, and WPCFG bits ignored\n0=WPFP[5:0], WPEND, and WPCFG bits enabled, write protect active\n""}"


// CONFIG4L (0xfffe)
"WPCFG[7]"
"{Write/Erase Protect Last Page In User Flash bit\n"
"1=Write/Erase Protection of last page Disabled\n0=Write/Erase Protection of last page Enabled\n""}"
"WPEND[6]"
"{Write Protection End Page (valid when WPDIS = 0)\n"
"1=Write/Erase protect Flash Memory pages starting at page WPFP[5:0] and ending with the last page in\n0=Write/Erase protect Flash Memory pages starting at page 0 and ending with page WPFP[5:0]\n""}"
"WPFP[5-0]"
"{Write Protect Program Flash Pages\n"
"000000=Write Protect Program Flash Page 0\n000001=Write Protect Program Flash Page 1\n000010=Write Protect Program Flash Page 2\n000011=Write Protect Program Flash Page 3\n000100=Write Protect Program Flash Page 4\n000101=Write Protect Program Flash Page 5\n000110=Write Protect Program Flash Page 6\n000111=Write Protect Program Flash Page 7\n001000=Write Protect Program Flash Page 8\n001001=Write Protect Program Flash Page 9\n001010=Write Protect Program Flash Page 10\n001011=Write Protect Program Flash Page 11\n001100=Write Protect Program Flash Page 12\n001101=Write Protect Program Flash Page 13\n001110=Write Protect Program Flash Page 14\n001111=Write Protect Program Flash Page 15\n010000=Write Protect Program Flash Page 16\n010001=Write Protect Program Flash Page 17\n010010=Write Protect Program Flash Page 18\n010011=Write Protect Program Flash Page 19\n010100=Write Protect Program Flash Page 20\n010101=Write Protect Program Flash Page 21\n010110=Write Protect Program Flash Page 22\n010111=Write Protect Program Flash Page 23\n011000=Write Protect Program Flash Page 24\n011001=Write Protect Program Flash Page 25\n011010=Write Protect Program Flash Page 26\n011011=Write Protect Program Flash Page 27\n011100=Write Protect Program Flash Page 28\n011101=Write Protect Program Flash Page 29\n011110=Write Protect Program Flash Page 30\n011111=Write Protect Program Flash Page 31\n100000=Write Protect Program Flash Page 32\n100001=Write Protect Program Flash Page 33\n100010=Write Protect Program Flash Page 34\n100011=Write Protect Program Flash Page 35\n100100=Write Protect Program Flash Page 36\n100101=Write Protect Program Flash Page 37\n100110=Write Protect Program Flash Page 38\n100111=Write Protect Program Flash Page 39\n101000=Write Protect Program Flash Page 40\n101001=Write Protect Program Flash Page 41\n101010=Write Protect Program Flash Page 42\n101011=Write Protect Program Flash Page 43\n101100=Write Protect Program Flash Page 44\n101101=Write Protect Program Flash Page 45\n101110=Write Protect Program Flash Page 46\n101111=Write Protect Program Flash Page 47\n110000=Write Protect Program Flash Page 48\n110001=Write Protect Program Flash Page 49\n110010=Write Protect Program Flash Page 50\n110011=Write Protect Program Flash Page 51\n110100=Write Protect Program Flash Page 52\n110101=Write Protect Program Flash Page 53\n110110=Write Protect Program Flash Page 54\n110111=Write Protect Program Flash Page 55\n111000=Write Protect Program Flash Page 56\n111001=Write Protect Program Flash Page 57\n111010=Write Protect Program Flash Page 58\n111011=Write Protect Program Flash Page 59\n111100=Write Protect Program Flash Page 60\n111101=Write Protect Program Flash Page 61\n111110=Write Protect Program Flash Page 62\n111111=Write Protect Program Flash Page 63\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff6/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f46k20"
, 0xa0c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled, RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6310"
, 0x8be0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in microcontroller mode\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6390"
, 0x8ba0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6393"
, 0x9a00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000c)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f63j11"
, 0xb900  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-001FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1ff8/2, 0x1fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f63j90"
, 0xb800  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1ff8/2, 0x1fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6410"
, 0x86e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in microcontroller mode\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6490"
, 0x86a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6493"
, 0x8e00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000c)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f64j11"
, 0xb920  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-003FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x3ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f64j90"
, 0xb820  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x3ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6520"
, 0x8b20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-10)"
"{Unused\n}"
"T1OSCMX[9]"
"{Timer1 OSC\n"
"1=Legacy\n0=Low Power\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n""}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n""}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6525"
, 0x8ae0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=ECCP1 and ECCP3 are muxed onto RE6 through RE3\n0=ECCP1 and ECCP3 are muxed onto RH7 through RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBfff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6527"
, 0x9340  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L (0x300004)
"0(7-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6585"
, 0x8a60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=P1B and P1C muxed with RE6 and RE5\n0=P1B and P1C muxed with RH7 and RH6\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBfff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f65j10"
, 0x9520  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"0(7-6)"
"{Unused\n}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n""}"
"0(3-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f65j11"
, 0xb960  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f65j15"
, 0x9540  // device ID 

// config bits descriptor
,
// CONFIG1H (0xbff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00BFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xbff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xbffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xbffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0xbffd)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xbffc)
"0(7-6)"
"{Unused\n}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n""}"
"0(3-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xBff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xBff8/2, 0xBfff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f65j50"
, 0xc100  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP MUX\n"
"1=PMP ports on PORTD and PORTE\n0=PMP ports on PORTA,PORTF and PORTH\n""}"
"RESERVED2[9]"
"{RESERVED\n"
"1=RESERVED\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x7ffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f65j90"
, 0xb860  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6620"
, 0x8660  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6621"
, 0x8aa0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=ECCP1 and ECCP3 are muxed onto RE6 through RE3\n0=ECCP1 and ECCP3 are muxed onto RH7 through RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6622"
, 0x9380  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L (0x300004)
"0(7-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xFFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6627"
, 0x93c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L (0x300004)
"0(7-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6628"
, 0xc9c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6680"
, 0x8a20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=P1B and P1C muxed with RE6 and RE5\n0=P1B and P1C muxed with RH7 and RH6\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j10"
, 0x9560  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0xfffd)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xfffc)
"0(7-6)"
"{Unused\n}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n""}"
"0(3-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j11"
, 0xc440  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-0FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xfffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j15"
, 0x9580  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-017FF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x17ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x17ffc)
"0(7-6)"
"{Unused\n}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n""}"
"0(3-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j16"
, 0xc460  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-017FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0x17ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x17ffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j50"
, 0xc140  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP MUX\n"
"1=PMP ports on PORTD and PORTE\n0=PMP ports on PORTA,PORTF and PORTH\n""}"
"RESERVED2[9]"
"{RESERVED\n"
"1=RESERVED\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller>\n""}"


// CONFIG3L (0xfffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j55"
, 0xc160  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-0017FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x17ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP MUX\n"
"1=PMP ports on PORTD and PORTE\n0=PMP ports on PORTA,PORTF and PORTH\n""}"
"RESERVED2[9]"
"{RESERVED\n"
"1=RESERVED\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller>\n""}"


// CONFIG3L (0x17ffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j60"
, 0x9800  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"CP_0[10]"
"{Code Protect 000000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n000=INTOSC as Primary, HS Osc\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7\n""}"


// CONFIG3L (0xfffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f66j65"
, 0x9f00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x17ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x17ffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6720"
, 0x8620  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1ffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6722"
, 0x9400  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L (0x300004)
"0(7-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f6723"
, 0xca00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=CCP2 muxed with RC1\n0=CCP2 muxed with RE7\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1ffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f67j10"
, 0x95a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1fffd)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1fffc)
"0(7-6)"
"{Unused\n}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n""}"
"0(3-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f67j11"
, 0xc480  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0x1fffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1fffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f67j50"
, 0xc180  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x1fffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP MUX\n"
"1=PMP ports on PORTD and PORTE\n0=PMP ports on PORTA,PORTF and PORTH\n""}"
"RESERVED2[9]"
"{RESERVED\n"
"1=RESERVED\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller>\n""}"


// CONFIG3L (0x1fffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f67j60"
, 0x9f20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x1fffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x1fffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8310"
, 0x8bc0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in microcontroller mode - RB3 in others\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8390"
, 0x8b80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8393"
, 0x9a20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000c)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f83j11"
, 0xb980  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-001FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1ff8/2, 0x1fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f83j90"
, 0xb880  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x1ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1ff8/2, 0x1fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8410"
, 0x86c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in microcontroller mode - RB3 in others\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8490"
, 0x8680  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000C)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8493"
, 0x8e20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external\n0=8-bit external\n""}"
"0(5-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L (0x300008)
"0(7-1)"
"{Unused\n}"
"CP_0[0]"
"{Code Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L (0x30000c)
"0(7-1)"
"{Unused\n}"
"EBTR_0[0]"
"{Table Read Protect 00000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, -1, -1 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 16/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f84j11"
, 0xb9a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-003FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x3ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f84j90"
, 0xb8a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x3ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-003FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x3ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x3ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x3ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x3ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7\n""}"


// CONFIG3L (0x3ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x3ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x3ff8/2, 0x3fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8520"
, 0x8b00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-10)"
"{Unused\n}"
"T1OSCMX[9]"
"{Timer1 OSC\n"
"1=Legacy\n0=Low Power\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in Microcontroller Mode / RB3 otherwise\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n""}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n""}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8525"
, 0x8ac0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=ECCP1 and ECCP3 are muxed onto RE6 through RE3\n0=ECCP1 and ECCP3 are muxed onto RH7 through RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in Microcontroller Mode / RB3 otherwise\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBfff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8527"
, 0x9360  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7-Microcontroller Mode/RB3-All other modes\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external bus\n0=8-bit external bus\n""}"
"ABW[5-4]"
"{Address Bus Width\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-3)"
"{Unused\n}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-3)"
"{Unused\n}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-3)"
"{Unused\n}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8585"
, 0x8a40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=P1B and P1C muxed with RE6 and RE5\n0=P1B and P1C muxed with RH7 and RH6\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in Microcontroller Mode / RB3 otherwise\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xBfff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f85j10"
, 0x95e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f85j11"
, 0xb9e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f85j15"
, 0x9700  // device ID 

// config bits descriptor
,
// CONFIG1H (0xbff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00BFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xbff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xbffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xbffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0xbffd)
"0(15-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xbffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xBff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xBff8/2, 0xBfff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f85j50"
, 0xc1a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{CCP2 Mux\n"
"1=PMP on EMB\n0=PMP elsewhere\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x7ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f85j90"
, 0xb8e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-007ff7\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x7ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x7ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"0(11-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 \n""}"


// CONFIG3L (0x7ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8620"
, 0x8640  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8621"
, 0x8a80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=ECCP1 and ECCP3 are muxed onto RE6 through RE3\n0=ECCP1 and ECCP3 are muxed onto RH7 through RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in Microcontroller Mode / RB3 otherwise\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8622"
, 0x93a0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"FOSC[11-8]"
"{Oscillator Select\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Timer Postscale Select\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDTEN[8]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BORV[4-3]"
"{Brown-out Reset Voltage\n"
"11=2.0 V\n10=2.7 V\n01=4.2 V\n00=4.5 V\n""}"
"BOREN[2-1]"
"{Brown-out Reset Enable\n"
"11=Brown-out Reset Enabled, SBOREN Disabled\n10=Brown-out Reset Enabled When Not in SLEEP, SBOREN Disabled\n01=Brown-out Controlled by SBOREN\n00=Brown-out Disabled, SBOREN Disabled\n""}"
"PWRTEN[0]"
"{Power-up Timer Enable\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR Pin Enable\n"
"1=MCLR Enabled, RG5 Input Pin Disabled\n0=MCLR Disabled, RG5 Input Pin Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low-Power Timer1 Oscillator Enable\n"
"1=Low Power Consumption, Low Noise Immunity\n0=High Power Consumption, High Noise Immunity\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 I/O Muxed With RB3 or RE7\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=MEMCON.WAIT Ignored, Device Will Not Wait\n0=Wait Programmed by MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-bit\n0=8-bit\n""}"
"ABW[5-4]"
"{Address Bus Width Select\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PM[1-0]"
"{Processor Data Memory Mode Select\n"
"11=Microcontroller Mode\n10=Microprocessor Mode\n01=Microprocessor With Boot Block Mode\n00=Extended Microcontroller Mode\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Programming Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVREN[0]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"0=Enabled\n1=Disabled\n""}"
"WRTB[14]"
"{Boot Block Write Protect\n"
"0=Enabled\n1=Disabled\n""}"
"WRTC[13]"
"{Config Memory Write Protect\n"
"0=Enabled\n1=Disabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Boot Block Table Read Protect\n"
"1=Unprotected From Reads in Other Blocks\n0=Protected From Reads in Other Blocks\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8627"
, 0x93e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7-Microcontroller Mode/RB3-All other modes\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external bus\n0=8-bit external bus\n""}"
"ABW[5-4]"
"{Address Bus Width\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8628"
, 0xc9e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7-Microcontroller Mode/RB3-All other modes\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external bus\n0=8-bit external bus\n""}"
"ABW[5-4]"
"{Address Bus Width\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-6)"
"{Unused\n}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"0(7-6)"
"{Unused\n}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"0(7-6)"
"{Unused\n}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x17fff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8680"
, 0x8a00  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"0=Enabled\n1=Disabled\n""}"
"0(12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1111=RC-OSC2 as RA6\n1110=HS oscillator with SW enabled 4x PLL\n1101=EC-OSC2 as RA6, software enabled 4X PLL\n1100=EC-OSC2 as RA6, hardware enabled 4X PLL\n0111=RC-OSC2 as RA6\n0110=HS-hardware enabled 4X PLL\n0101=EC-OSC2 as RA6\n0100=EC-OSC2 as divide by 4 CLKOUT\n0011=RC-OSC2 as divide by 4 CLKOUT\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{MCLR enable\n"
"1=MCLR Enabled, RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=P1B and P1C muxed with RE6 and RE5\n0=P1B and P1C muxed with RH7 and RH6\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 in Microcontroller Mode / RB3 otherwise\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 00C000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 008000-00BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 0004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 000800-0003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 004000-007FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 004000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-003FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0xffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j10"
, 0x9720  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0xfffd)
"0(15-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xfffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j11"
, 0xc4e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-0FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xfffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j15"
, 0x9740  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-017FF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x17ffd)
"0(15-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j16"
, 0xc500  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-017FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0x17ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j50"
, 0xc1e0  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-00FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{CCP2 Mux\n"
"1=PMP on EMB\n0=PMP elsewhere\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0xfffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j55"
, 0xc200  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-017FF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x17ffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x17ffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP V3 7 bit address masking bit mode\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{CCP2 Mux\n"
"1=PMP on EMB\n0=PMP elsewhere\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j60"
, 0x9820  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"CP_0[10]"
"{Code Protect 000000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n000=INTOSC as Primary, HS Osc\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7\n""}"


// CONFIG3L (0xfffc)
"RES[7-3]"
"{Reserved\n"
"11111=maintain these bits as 1\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f86j65"
, 0x9f40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x17ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x17ffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8720"
, 0x8600  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"0(15-14)"
"{Unused\n}"
"OSCS[13]"
"{Osc. Switch Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-11)"
"{Unused\n}"
"OSC[10-8]"
"{Oscillator\n"
"111=RC-OSC2 as RA6\n110=HS-PLL Enabled\n101=EC-OSC2 as RA6\n100=EC-OSC2 as Clock Out\n011=RC-OSC2 as Clock Out\n010=HS\n001=XT\n000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-9]"
"{Watchdog Postscaler\n"
"111=1:128\n110=1:64\n101=1:32\n100=1:16\n011=1:8\n010=1:4\n001=1:2\n000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-4)"
"{Unused\n}"
"BODENV[3-2]"
"{Brown Out Voltage\n"
"11=2.5V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[1]"
"{Brown Out Detect\n"
"1=Enabled\n0=Disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"0(15-9)"
"{Unused\n}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"0(6-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00200-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1ffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8722"
, 0x9420  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7-Microcontroller Mode/RB3-All other modes\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external bus\n0=8-bit external bus\n""}"
"ABW[5-4]"
"{Address Bus Width\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1FFFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f8723"
, 0xca20  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RG5 Disabled\n0=MCLR Disabled, RG5 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7-Microcontroller Mode/RB3-All other modes\n""}"


// CONFIG3L (0x300004)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Bus Width\n"
"1=16-bit external bus\n0=8-bit external bus\n""}"
"ABW[5-4]"
"{Address Bus Width\n"
"11=20-bit\n10=16-bit\n01=12-bit\n00=8-bit\n""}"
"0(3-2)"
"{Unused\n}"
"PMODE[1-0]"
"{Processor Mode\n"
"11=Microcontroller\n10=Microprocessor\n01=Microprocessor w/Boot\n00=Ext Microcontroller\n""}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"BBSIZ[5-4]"
"{Boot Block Size\n"
"10=4K Words (8 Kbytes)\n01=2K Words (4 Kbytes)\n00=1K Words (2 Kbytes)\n""}"
"0(3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EE Read Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"CP_7[7]"
"{Code Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_6[6]"
"{Code Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_5[5]"
"{Code Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_4[4]"
"{Code Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_3[3]"
"{Code Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000b)
"WRTD[15]"
"{Data EE Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000a)
"WRT_7[7]"
"{Table Write Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_6[6]"
"{Table Write Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_5[5]"
"{Table Write Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_4[4]"
"{Table Write Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_3[3]"
"{Table Write Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000d)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000c)
"EBTR_7[7]"
"{Table Read Protect 1C000-1FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_6[6]"
"{Table Read Protect 18000-1BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_5[5]"
"{Table Read Protect 14000-17FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_4[4]"
"{Table Read Protect 10000-13FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_3[3]"
"{Table Read Protect 0C000-0FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 08000-0BFFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 04000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-03FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x1ffff/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0x3ff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000d/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f87j10"
, 0x9760  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF6\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 EC+PLL\n110=OSC1/OSC2 EC\n101=OSC1/OSC2 HS+PLL\n100=OSC1/OSC2 HS\n011=INTOSC EC+PLL\n010=INTOSC EC\n001=INTOSC HS+PLL\n000=INTOSC HS\n""}"

";"

// CONFIG3H (0x1fffd)
"0(15-10)"
"{Unused\n}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f87j11"
, 0xc520  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=ECPLL\n110=EC\n101=HSPLL\n100=HS\n011=INTPLL1\n010=INTPLL2\n001=INTIO1\n000=INTIO2\n""}"

";"

// CONFIG3H (0x1fffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP Mux\n"
"1=PMP on PORTD and PORTE\n0=PMP on PORTA, PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f87j50"
, 0xc220  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFF7\n"
"1=Disabled\n0=Enabled\n""}"
"CPUDIV[9-8]"
"{CPU DIV\n"
"11=No CPU system clock divide\n10=CPU system clock divide by 2\n01=CPU system clock divide by 3\n00=CPU system clock divide by 6\n""}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVR[5]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"
"0(4)"
"{Unused\n}"
"PLLDIV[3-1]"
"{PLL DIV\n"
"111=No Divide (4MHz input)\n110=Divide by 2 (8MHz input)\n101=Divide by 3 (12MHz input)\n100=Divide by 4 (16MHz input)\n011=Divide by 5 (20MHz input)\n010=Divide by 6 (24MHz input)\n001=Divide by 10 (40MHz input)\n000=Divide by 12 (48MHz input)\n""}"
"WDT[0]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"

";"

// CONFIG2H (0x1fffb)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[6]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(5-3)"
"{Unused\n}"
"OSC[2-0]"
"{Oscillator\n"
"111=EC+PLL(CLKO-RA6),USB-EC+PLL\n110=EC(CLKO-RA6),USB-EC\n101=HS+PLL,USB-HS+PLL\n100=HS,USB-HS\n011=INTOSCPLLO(CLKO-RA6)\n010=INTOSCPLL\n001=INTOSCO(CLKO-RA6)\n000=INTOSC\n""}"

";"

// CONFIG3H (0x1fffd)
"RESERVED[15-12]"
"{RESERVED\n"
"1111=RESERVED\n""}"
"MSSP7B_EN[11]"
"{MSSP address masking\n"
"1=7 bit address masking mode\n0=5 bit address masking mode\n""}"
"PMPMX[10]"
"{PMP MUX\n"
"1=PMP ports on PORTD and PORTE\n0=PMP ports on PORTA,PORTF and PORTH\n""}"
"ECCPMX[9]"
"{ECCP Mux\n"
"1=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3\n0=Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RE7 <Microcontroller> / RB3\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait\n"
"1=Disabled\n0=Enabled\n""}"
"BW[6]"
"{Data Bus Width\n"
"1=16-bit external bus mode\n0=8-bit external bus mode\n""}"
"PMODE[5-4]"
"{External Memory Bus\n"
"11=Microcontroller\n10=Ext Microcontroller 12-bit\n01=Ext Microcontroller 16-bit\n00=Ext Microcontroller 20-bit\n""}"
"EASHFT[3]"
"{External Address Bus Shift\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f87j60"
, 0x9f60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x1fffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x1fffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f96j60"
, 0x9840  // device ID 

// config bits descriptor
,
// CONFIG1H (0xfff9)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"CP_0[10]"
"{Code Protect 000000-00FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0xfff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"XINST[6]"
"{Extended Instruction Set Enable bit\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0xfffb)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0xfffa)
"IESO[7]"
"{Internal External Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n000=INTOSC as Primary, HS Osc\n""}"

";"

// CONFIG3H (0xfffd)
"RESERVED[15-12]"
"{RESERVED\n"
"0000=RESERVED\n""}"
"0(11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0xfffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0xfff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0xfff8/2, 0xffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f96j65"
, 0x9f80  // device ID 

// config bits descriptor
,
// CONFIG1H (0x17ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x17ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x17ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x17ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x17ffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x17ffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x17ff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x17ff8/2, 0x17fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18f97j60"
, 0x9fa0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x1fff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP_0[10]"
"{Code Protect 000000-01FFFF\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x1fff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x1fffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x1fffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC[2-0]"
"{Oscillator Select\n"
"111=OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function\n110=OSC1/OSC2 as Primary, EC Osc with CLKOUT Function\n101=OSC1/OSC2 as primary, HS+PLL Osc\n100=OSC1/OSC2 as primary, HS Osc\n011=INTOSC as Primary, EC+PLL Osc with CLKOUT\n010=INTOSC as Primary, EC Osc with CLKOUT\n001=INTOSC as Primary, HS+PLL Osc\n""}"

";"

// CONFIG3H (0x1fffd)
"0(15-11)"
"{Unused\n}"
"ETHLED[10]"
"{Ethernet LED Enable\n"
"1=LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without\n0=RA0 On RA0/AN0), RA1 On RA1/AN1\n""}"
"ECCPXM[9]"
"{ECCP Mux\n"
"1=P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3\n0=P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4\n""}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=ECCP2 I/O Muxed With RC1\n0=ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode)\n""}"


// CONFIG3L (0x1fffc)
"WAIT[7]"
"{External Bus Wait Enable\n"
"1=Ignore MEMCON.WAIT, Device Will Not Wait\n0=Observe MEMCON.WAIT\n""}"
"BW[6]"
"{Data Bus Width Select\n"
"1=16-Bit\n0=8-Bit\n""}"
"EMB[5-4]"
"{External Memory Bus Address Mode\n"
"11=Microcontroller Mode, External Bus Disabled\n10=Extended Microcontroller Mode, 12-Bit Addr\n01=Extended Microcontroller Mode, 16-Bit Addr\n00=Extended Microcontroller Mode, 20-Bit Addr\n""}"
"EASHFT[3]"
"{External Address Bus Shift Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(2-0)"
"{Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x1fff7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x1fff8/2, 0x1ffff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf2423"
, 0x9140  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf2523"
, 0x9100  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf25j10"
, 0x9c40  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf4423"
, 0x90c0  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-2)"
"{Unused\n}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-2)"
"{Unused\n}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-2)"
"{Unused\n}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x3FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x0/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 32/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf4523"
, 0x9080  // device ID 

// config bits descriptor
,
// CONFIG1H (0x300001)
"IESO[15]"
"{Internal External Switch Over Mode\n"
"0=Disabled\n1=Enabled\n""}"
"FCMEN[14]"
"{Fail-Safe Clock Monitor Enable\n"
"0=Disabled\n1=Enabled\n""}"
"0(13-12)"
"{Unused\n}"
"OSC[11-8]"
"{Oscillator\n"
"1100=11XX EXT RC-CLKOUT on RA6\n1010=101X EXT RC-CLKOUT on RA6\n1001=INT RC-CLKOUT on RA6,Port on RA7\n1000=INT RC-Port on RA6,Port on RA7\n0111=EXT RC-Port on RA6\n0110=HS-PLL enabled freq=4xFosc1\n0101=EC-Port on RA6\n0100=EC-CLKOUT on RA6\n0011=0011 EXT RC-CLKOUT on RA6\n0010=HS\n0001=XT\n0000=LP\n""}"


// CONFIG1L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG2H (0x300003)
"0(15-13)"
"{Unused\n}"
"WDTPS[12-9]"
"{Watchdog Postscaler\n"
"1111=1:32768\n1110=1:16384\n1101=1:8192\n1100=1:4096\n1011=1:2048\n1010=1:1024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"
"WDT[8]"
"{Watchdog Timer\n"
"1=Enabled\n0=Disabled-Controlled by SWDTEN bit\n""}"


// CONFIG2L (0x300002)
"0(7-5)"
"{Unused\n}"
"BODENV[4-3]"
"{Brown Out Voltage\n"
"11=2.0V\n10=2.7V\n01=4.2V\n00=4.5V\n""}"
"BODEN[2-1]"
"{Brown Out Detect\n"
"11=Enabled in hardware, SBOREN disabled\n10=Enabled while active,disabled in SLEEP,SBOREN disabled\n01=Controlled with SBOREN bit\n00=Disabled in hardware, SBOREN disabled\n""}"
"PUT[0]"
"{Power Up Timer\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG3H (0x300005)
"MCLRE[15]"
"{Master Clear Enable\n"
"1=MCLR Enabled,RE3 Disabled\n0=MCLR Disabled,RE3 Enabled\n""}"
"0(14-11)"
"{Unused\n}"
"LPT1OSC[10]"
"{Low Power Timer1 Osc enable\n"
"1=Enabled\n0=Disabled\n""}"
"PBADEN[9]"
"{PortB A/D Enable\n"
"1=PORTB<4:0> configured as analog inputs on RESET\n0=PORTB<4:0> configured as digital I/O on RESET\n""}"
"CCP2MUX[8]"
"{CCP2 Mux\n"
"1=RC1\n0=RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L (0x300006)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Extended CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"LVP[2]"
"{Low Voltage Program\n"
"1=Enabled\n0=Disabled\n""}"
"0(1)"
"{Unused\n}"
"STVR[0]"
"{Stack Overflow Reset\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG5H (0x300009)
"CPD[15]"
"{Data EEPROM Code Protect\n"
"1=Disabled\n0=Enabled\n""}"
"CPB[14]"
"{Code Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG5L (0x300008)
"0(7-4)"
"{Unused\n}"
"CP_3[3]"
"{Code Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_2[2]"
"{Code Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_1[1]"
"{Code Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"CP_0[0]"
"{Code Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG6H (0x30000B)
"WRTD[15]"
"{Data EEPROM Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"WRTB[14]"
"{Table Write Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"WRTC[13]"
"{Config. Write Protect\n"
"1=Disabled\n0=Enabled\n""}"
"0(12-8)"
"{Unused\n}"


// CONFIG6L (0x30000A)
"0(7-4)"
"{Unused\n}"
"WRT_3[3]"
"{Table Write Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_2[2]"
"{Table Write Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_1[1]"
"{Table Write Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"WRT_0[0]"
"{Table Write Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

";"

// CONFIG7H (0x30000D)
"0(15)"
"{Unused\n}"
"EBTRB[14]"
"{Table Read Protect Boot\n"
"1=Disabled\n0=Enabled\n""}"
"0(13-8)"
"{Unused\n}"


// CONFIG7L (0x30000C)
"0(7-4)"
"{Unused\n}"
"EBTR_3[3]"
"{Table Read Protect 06000-07FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_2[2]"
"{Table Read Protect 04000-05FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_1[1]"
"{Table Read Protect 02000-03FFF\n"
"1=Disabled\n0=Enabled\n""}"
"EBTR_0[0]"
"{Table Read Protect 00800-01FFF\n"
"1=Disabled\n0=Enabled\n""}"

, 0x0/2, 0x7FFF/2 // program memory 
, 0x200000/2, 0x200007/2 // user ID data
, 0x00/2+0xF00000/2, 0xff/2+0xF00000/2 // EEPROM data
, 0x300000/2, 0x30000D/2 // CONFIG data
, -1, -1 // calibration data words
, 8/2 // write buffer size 

, 16 // bits per word 
}
,
{
"p18lf45j10"
, 0x9c60  // device ID 

// config bits descriptor
,
// CONFIG1H (0x7ff9)
"0(15-12)"
"{Unused\n}"
"SIGN[11]"
"{Config Word Signature Bit\n"
"1=Bulk erase of memory not conducated\n0=Bulk erase of memory area complete\n""}"
"CP0[10]"
"{Code Protect Enable\n"
"1=Disabled\n0=Enabled\n""}"
"0(9-8)"
"{Unused\n}"


// CONFIG1L (0x7ff8)
"BACKBUG[7]"
"{Background Debug\n"
"1=Disabled\n0=Enabled\n""}"
"ENHCPU[6]"
"{Enhanced CPU Enable\n"
"1=Enabled\n0=Disabled\n""}"
"STVREN[5]"
"{Stack Overflow Reset Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(4-1)"
"{Unused\n}"
"WDTEN[0]"
"{Watchdog Timer Enable\n"
"1=Enabled\n0=Disabled\n""}"

";"

// CONFIG2H (0x7ffb)
"0(15-12)"
"{Unused\n}"
"WDTPS[11-8]"
"{Watchdog Timer Postscale\n"
"1111=1:32,768\n1110=1:16,384\n1101=1:8,192\n1100=1:4,096\n1011=1:2,048\n1010=1:1,024\n1001=1:512\n1000=1:256\n0111=1:128\n0110=1:64\n0101=1:32\n0100=1:16\n0011=1:8\n0010=1:4\n0001=1:2\n0000=1:1\n""}"


// CONFIG2L (0x7ffa)
"IESO[7]"
"{Internal Exteranl Switch Over Enable\n"
"1=Enabled\n0=Disabled\n""}"
"FCMEN[6]"
"{Fail Safe Monitor Clock Enable\n"
"1=Enabled\n0=Disabled\n""}"
"0(5-3)"
"{Unused\n}"
"FOSC2[2]"
"{Default/Reset System Clock Select\n"
"1=Clock Select by FOSC\n0=INTRC enabled\n""}"
"FOSC[1-0]"
"{Oscillator Select\n"
"11=EC OSC with software PLL and CLKOUT on OSC2\n10=EC OSC with CLKOUT on OSC2\n01=HS OSC with software PLL\n00=HS OSC\n""}"

";"

// CONFIG3H (0x7ffd)
"0(15-9)"
"{Unused\n}"
"CCP2MX[8]"
"{CCP2 Mux\n"
"1=CCP2 I/O Muxed with RC1\n0=CCP2 I/O Muxed with RB3\n""}"


// CONFIG3L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG4H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG4L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG5H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG5L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG6H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG6L ( Not defined for this device )
"0(7-0){Unused\n}"

";"

// CONFIG7H ( Not defined for this device )
"0(15-8){Unused\n}"


// CONFIG7L ( Not defined for this device )
"0(7-0){Unused\n}"

, 0x0/2, 0x7FF7/2 // program memory 
, -1, -1 // user ID data
, -1, -1 // EEPROM data
, 0x7ff8/2, 0x7fff/2 // CONFIG data
, -1, -1 // calibration data words
, 64/2 // write buffer size 

, 16 // bits per word 
}

} ;
