/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright(c) 2024 MediaTek. All rights reserved.
 *
 * Author: Darren Ye <darren.ye@mediatek.com>
 */

#ifndef _MT_8196_AFE_COMMON_H_
#define _MT_8196_AFE_COMMON_H_

enum {
	MT8196_MEMIF_START,
	MT8196_MEMIF_DL_START = MT8196_MEMIF_START,
	MT8196_MEMIF_DL1 = MT8196_MEMIF_DL_START,
	MT8196_MEMIF_DL_24CH,
	MT8196_MEMIF_DL_END,
	MT8196_MEMIF_UL_START = MT8196_MEMIF_DL_END,
	MT8196_MEMIF_UL0 = MT8196_MEMIF_UL_START,
	MT8196_MEMIF_UL1,
	MT8196_MEMIF_UL2,
	MT8196_MEMIF_UL_END,
	MT8196_MEMIF_END = MT8196_MEMIF_UL_END,
	MT8196_MEMIF_DL_NUM = (MT8196_MEMIF_DL_END - MT8196_MEMIF_DL_START),
	MT8196_MEMIF_UL_NUM = (MT8196_MEMIF_UL_END - MT8196_MEMIF_UL_START),
	MT8196_MEMIF_NUM = (MT8196_MEMIF_END - MT8196_MEMIF_START),
};

/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
enum {
	MT8196_IRQ_0,
	MT8196_IRQ_1,
	MT8196_IRQ_2,
	MT8196_IRQ_3,
	MT8196_IRQ_4,
	MT8196_IRQ_5,
	MT8196_IRQ_6,
	MT8196_IRQ_7,
	MT8196_IRQ_8,
	MT8196_IRQ_9,
	MT8196_IRQ_10,
	MT8196_IRQ_11,
	MT8196_IRQ_12,
	MT8196_IRQ_13,
	MT8196_IRQ_14,
	MT8196_IRQ_15,
	MT8196_IRQ_16,
	MT8196_IRQ_17,
	MT8196_IRQ_18,
	MT8196_IRQ_19,
	MT8196_IRQ_20,
	MT8196_IRQ_21,
	MT8196_IRQ_22,
	MT8196_IRQ_23,
	MT8196_IRQ_24,
	MT8196_IRQ_25,
	MT8196_IRQ_26,
	MT8196_IRQ_31,  /* used only for TDM */
	MT8196_IRQ_NUM,
};

enum {
	MT8196_DAI_I2S_OUT4, /* speaker */
	MT8196_DAI_I2S_OUT6, /* headset out */
	MT8196_DAI_AP_DMIC, /* DMIC */
	MT8196_DAI_I2S_IN6, /* headset mic */
	MT8196_DAI_AP_DMIC_CH34,
	MT8196_DAI_NUM,
};

#endif
