/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright(c) 2021 MediaTek. All rights reserved.
 *
 * Author: YC Hung <yc.hung@mediatek.com>
 *         Allen-KH Cheng <allen-kh.cheng@mediatek.com>
 */

#ifndef MT_REG_BASE_H
#define MT_REG_BASE_H

#define MTK_DSP_IRQ_BASE 0x10009000
#define MTK_DSP_IRQ_SIZE 0x1000

#define MTK_TOPCKGEN_REG_BASE 0x1001B000
#define MTK_TOPCKGEN_REG_SIZE 0x00001000

#define MTK_DSP_REG_REMAP_BASE 0x10800000
#define MTK_DSP_REG_REMAP_SIZE 0xE000
#define MTK_DSP_TIMER_BASE 0x10800000
#define MTK_DSP_UART0_BASE 0x10801000
#define MTK_DSP_REG_BASE 0x10803000 /* DSPCFG base */
#define MTK_DSP_WDT_BASE 0x10803400
#define MTK_DSP_OSTIMER_BASE 0x1080D000

#define MTK_DSP_JTAGMUX (MTK_DSP_REG_BASE + 0x0000)
#define MTK_DSP_ALTRESETVEC (MTK_DSP_REG_BASE + 0x0004)
#define MTK_DSP_PDEBUGDATA (MTK_DSP_REG_BASE + 0x0008)
#define MTK_DSP_PDEBUGBUS0 (MTK_DSP_REG_BASE + 0x000c)
#define MTK_DSP_PDEBUGBUS1 (MTK_DSP_REG_BASE + 0x0010)
#define MTK_DSP_PDEBUGINST (MTK_DSP_REG_BASE + 0x0014)
#define MTK_DSP_PDEBUGLS0STAT (MTK_DSP_REG_BASE + 0x0018)
#define MTK_DSP_PDEBUGLS1STAT (MTK_DSP_REG_BASE + 0x001c)
#define MTK_DSP_PDEBUGPC (MTK_DSP_REG_BASE + 0x0020)
#define MTK_DSP_RESET_SW (MTK_DSP_REG_BASE + 0x0024)
#define MTK_DSP_PFAULTBUS (MTK_DSP_REG_BASE + 0x0028)
#define MTK_DSP_PFAULTINFO (MTK_DSP_REG_BASE + 0x002c)
#define MTK_DSP_GPR00 (MTK_DSP_REG_BASE + 0x0030)
#define MTK_DSP_GPR01 (MTK_DSP_REG_BASE + 0x0034)
#define MTK_DSP_GPR02 (MTK_DSP_REG_BASE + 0x0038)
#define MTK_DSP_GPR03 (MTK_DSP_REG_BASE + 0x003c)
#define MTK_DSP_GPR04 (MTK_DSP_REG_BASE + 0x0040)
#define MTK_DSP_GPR05 (MTK_DSP_REG_BASE + 0x0044)
#define MTK_DSP_GPR06 (MTK_DSP_REG_BASE + 0x0048)
#define MTK_DSP_GPR07 (MTK_DSP_REG_BASE + 0x004c)
#define MTK_DSP_GPR08 (MTK_DSP_REG_BASE + 0x0050)
#define MTK_DSP_GPR09 (MTK_DSP_REG_BASE + 0x0054)
#define MTK_DSP_GPR0A (MTK_DSP_REG_BASE + 0x0058)
#define MTK_DSP_GPR0B (MTK_DSP_REG_BASE + 0x005c)
#define MTK_DSP_GPR0C (MTK_DSP_REG_BASE + 0x0060)
#define MTK_DSP_GPR0D (MTK_DSP_REG_BASE + 0x0064)
#define MTK_DSP_GPR0E (MTK_DSP_REG_BASE + 0x0068)
#define MTK_DSP_GPR0F (MTK_DSP_REG_BASE + 0x006c)
#define MTK_DSP_GPR10 (MTK_DSP_REG_BASE + 0x0070)
#define MTK_DSP_GPR11 (MTK_DSP_REG_BASE + 0x0074)
#define MTK_DSP_GPR12 (MTK_DSP_REG_BASE + 0x0078)
#define MTK_DSP_GPR13 (MTK_DSP_REG_BASE + 0x007c)
#define MTK_DSP_GPR14 (MTK_DSP_REG_BASE + 0x0080)
#define MTK_DSP_GPR15 (MTK_DSP_REG_BASE + 0x0084)
#define MTK_DSP_GPR16 (MTK_DSP_REG_BASE + 0x0088)
#define MTK_DSP_GPR17 (MTK_DSP_REG_BASE + 0x008c)
#define MTK_DSP_GPR18 (MTK_DSP_REG_BASE + 0x0090)
#define MTK_DSP_GPR19 (MTK_DSP_REG_BASE + 0x0094)
#define MTK_DSP_GPR1A (MTK_DSP_REG_BASE + 0x0098)
#define MTK_DSP_GPR1B (MTK_DSP_REG_BASE + 0x009c)
#define MTK_DSP_GPR1C (MTK_DSP_REG_BASE + 0x00a0)
#define MTK_DSP_GPR1D (MTK_DSP_REG_BASE + 0x00a4)
#define MTK_DSP_GPR1E (MTK_DSP_REG_BASE + 0x00a8)
#define MTK_DSP_GPR1F (MTK_DSP_REG_BASE + 0x00ac)
#define MTK_DSP_TCM_OFFSET (MTK_DSP_REG_BASE + 0x00b0) /* not used */
#define MTK_DSP_DDR_OFFSET (MTK_DSP_REG_BASE + 0x00b4) /* not used */
#define MTK_DSP_INTFDSP (MTK_DSP_REG_BASE + 0x00d0)
#define MTK_DSP_INTFDSP_CLR (MTK_DSP_REG_BASE + 0x00d4)
#define MTK_DSP_SRAM_PD_SW1 (MTK_DSP_REG_BASE + 0x00d8)
#define MTK_DSP_SRAM_PD_SW2 (MTK_DSP_REG_BASE + 0x00dc)
#define MTK_DSP_OCD (MTK_DSP_REG_BASE + 0x00e0)
#define MTK_DSP_RG_DSP_IRQ_POL (MTK_DSP_REG_BASE + 0x00f0)
#define MTK_DSP_DSP_IRQ_EN (MTK_DSP_REG_BASE + 0x00f4)
#define MTK_DSP_DSP_IRQ_LEVEL (MTK_DSP_REG_BASE + 0x00f8)
#define MTK_DSP_DSP_IRQ_STATUS (MTK_DSP_REG_BASE + 0x00fc)
#define MTK_DSP_RG_INT2CIRQ (MTK_DSP_REG_BASE + 0x0114)
#define MTK_DSP_RG_INT_POL_CTL0 (MTK_DSP_REG_BASE + 0x0120)
#define MTK_DSP_RG_INT_EN_CTL0 (MTK_DSP_REG_BASE + 0x0130)
#define MTK_DSP_RG_INT_LV_CTL0 (MTK_DSP_REG_BASE + 0x0140)
#define MTK_DSP_RG_INT_STATUS0 (MTK_DSP_REG_BASE + 0x0150)
#define MTK_DSP_PDEBUGSTATUS0 (MTK_DSP_REG_BASE + 0x0200)
#define MTK_DSP_PDEBUGSTATUS1 (MTK_DSP_REG_BASE + 0x0204)
#define MTK_DSP_PDEBUGSTATUS2 (MTK_DSP_REG_BASE + 0x0208)
#define MTK_DSP_PDEBUGSTATUS3 (MTK_DSP_REG_BASE + 0x020c)
#define MTK_DSP_PDEBUGSTATUS4 (MTK_DSP_REG_BASE + 0x0210)
#define MTK_DSP_PDEBUGSTATUS5 (MTK_DSP_REG_BASE + 0x0214)
#define MTK_DSP_PDEBUGSTATUS6 (MTK_DSP_REG_BASE + 0x0218)
#define MTK_DSP_PDEBUGSTATUS7 (MTK_DSP_REG_BASE + 0x021c)
#define MTK_DSP_DSP2PSRAM_PRIORITY (MTK_DSP_REG_BASE + 0x0220) /* not used */
#define MTK_DSP_AUDIO_DSP2SPM_INT (MTK_DSP_REG_BASE + 0x0224)
#define MTK_DSP_AUDIO_DSP2SPM_INT_ACK (MTK_DSP_REG_BASE + 0x0228)
#define MTK_DSP_AUDIO_DSP_DEBUG_SEL (MTK_DSP_REG_BASE + 0x022C)
#define MTK_DSP_AUDIO_DSP_EMI_BASE_ADDR (MTK_DSP_REG_BASE + 0x02E0) /* not used */
#define MTK_DSP_AUDIO_DSP_SHARED_IRAM (MTK_DSP_REG_BASE + 0x02E4)
#define MTK_DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (MTK_DSP_REG_BASE + 0x02F0)
#define MTK_DSP_RG_SEMAPHORE00 (MTK_DSP_REG_BASE + 0x0300)
#define MTK_DSP_RG_SEMAPHORE01 (MTK_DSP_REG_BASE + 0x0304)
#define MTK_DSP_RG_SEMAPHORE02 (MTK_DSP_REG_BASE + 0x0308)
#define MTK_DSP_RG_SEMAPHORE03 (MTK_DSP_REG_BASE + 0x030C)
#define MTK_DSP_RG_SEMAPHORE04 (MTK_DSP_REG_BASE + 0x0310)
#define MTK_DSP_RG_SEMAPHORE05 (MTK_DSP_REG_BASE + 0x0314)
#define MTK_DSP_RG_SEMAPHORE06 (MTK_DSP_REG_BASE + 0x0318)
#define MTK_DSP_RG_SEMAPHORE07 (MTK_DSP_REG_BASE + 0x031C)
#define MTK_DSP_RESERVED_0 (MTK_DSP_REG_BASE + 0x03F0)
#define MTK_DSP_RESERVED_1 (MTK_DSP_REG_BASE + 0x03F4)

/*MBOX registers*/
#define MTK_DSP_MBOX_REG_BASE(x) (0x10816000 + (0x1000 * (x)))
#define MTK_DSP_MBOX_REG_SIZE (0x5000)
#define MTK_DSP_MBOX_IN_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x0)
#define MTK_DSP_MBOX_IN_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x04)
#define MTK_DSP_MBOX_OUT_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x1c)
#define MTK_DSP_MBOX_OUT_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x20)
#define MTK_DSP_MBOX_OUT_CMD_MSG0(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x24)
#define MTK_DSP_MBOX_OUT_CMD_MSG1(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x28)
#define MTK_DSP_MBOX_OUT_CMD_MSG2(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x2c)
#define MTK_DSP_MBOX_OUT_CMD_MSG3(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x30)
#define MTK_DSP_MBOX_OUT_CMD_MSG4(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x34)

/* Redefinition for using Special registers */
#define MTK_TICKLESS_STATUS_REG (DSP_RESERVED_1)

/* WDT CONFIGS */
#define MTK_ADSP_WDT_MODE (MTK_DSP_WDT_BASE + 0x00)
#define MTK_ADSP_WDT_LENGTH (MTK_DSP_WDT_BASE + 0x04)
#define MTK_ADSP_WDT_RESTART (MTK_DSP_WDT_BASE + 0x08)
#define MTK_ADSP_WDT_STA (MTK_DSP_WDT_BASE + 0x0C)
#define MTK_ADSP_WDT_SWRST (MTK_DSP_WDT_BASE + 0x14)

#define MTK_ADSP_WDT_SWRST_KEY 0x1209
#define MTK_ADSP_WDT_RESTART_RELOAD 0x1971
#define MTK_ADSP_WDT_LENGTH_KEY 0x8

#define MTK_WDT_LENGTH_TIMEOUT(n) ((n) << 5)

#endif /* MT_REG_BASE_H */
