/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright(c) 2024 MediaTek. All rights reserved.
 *
 * Author: Hailong Fan <hailong.fan@mediatek.com>
 *
 */

#ifndef MT_REG_BASE_H
#define MT_REG_BASE_H

#define MTK_DSP_CFGREG_BASE		0x1A000000 /* DSP Register base */
#define MTK_DSP_CFGREG_SIZE		0x1000
#define MTK_ADSP_CFGREG_SW_RSTN		(MTK_DSP_CFGREG_BASE + 0x0000)
#define MTK_ADSP_HIFI_IO_CONFIG		(MTK_DSP_CFGREG_BASE + 0x000c)
#define MTK_ADSP_IRQ_STATUS		(MTK_DSP_CFGREG_BASE + 0x0010)
#define MTK_ADSP_SW_INT_SET		(MTK_DSP_CFGREG_BASE + 0x0018)
#define MTK_ADSP_SW_INT_CLR		(MTK_DSP_CFGREG_BASE + 0x001c)
#define MTK_ADSP_SW_INT_32A		(MTK_DSP_CFGREG_BASE + 0x0020)
#define MTK_ADSP_IRQ_MASK		(MTK_DSP_CFGREG_BASE + 0x0030)
#define MTK_ADSP_GENERAL_IRQ_SET	(MTK_DSP_CFGREG_BASE + 0x0034)
#define MTK_ADSP_GENERAL_IRQ_CLR	(MTK_DSP_CFGREG_BASE + 0x0038)
#define MTK_ADSP_DVFSRC_STATE		(MTK_DSP_CFGREG_BASE + 0x003c)
#define MTK_ADSP_DVFSRC_REQ		(MTK_DSP_CFGREG_BASE + 0x0040)
#define MTK_ADSP_DDREN_REQ_0		(MTK_DSP_CFGREG_BASE + 0x0044)
#define MTK_ADSP_SPM_ACK		(MTK_DSP_CFGREG_BASE + 0x004c)
#define MTK_ADSP_IRQ_EN			(MTK_DSP_CFGREG_BASE + 0x0050)
#define MTK_ADSP_IRQ_POL_FIX		(MTK_DSP_CFGREG_BASE + 0x0054)
#define MTK_ADSP_SPM_WAKEUPSRC_CORE0	(MTK_DSP_CFGREG_BASE + 0x005c)
#define MTK_ADSP_SEMAPHORE		(MTK_DSP_CFGREG_BASE + 0x0064)
#define MTK_ADSP_DBG_SEL		(MTK_DSP_CFGREG_BASE + 0x0074)
#define MTK_ADSP_DBG_INFO		(MTK_DSP_CFGREG_BASE + 0x0078)
#define MTK_ADSP_WDT_CON_C0		(MTK_DSP_CFGREG_BASE + 0x007c)
#define MTK_ADSP_WDT_INIT_VALUE_C0	(MTK_DSP_CFGREG_BASE + 0x0080)
#define MTK_ADSP_WDT_CNT_C0		(MTK_DSP_CFGREG_BASE + 0x0084)
#define MTK_ADSP_WAKEUPSRC_MASK_C0	(MTK_DSP_CFGREG_BASE + 0x00a0)
#define MTK_ADSP_WAKEUPSRC_IRQ_C0	(MTK_DSP_CFGREG_BASE + 0x00a4)
#define MTK_ADSP2SPM_MBOX		(MTK_DSP_CFGREG_BASE + 0x00bc)
#define MTK_SPM2ADSP_MBOX		(MTK_DSP_CFGREG_BASE + 0x00c0)

/* intc */
#define MTK_ADSP_INTC_BASE                   (MTK_DSP_CFGREG_BASE + 0x14000)

#define INTC_IRQ_RAW_STA0                (MTK_ADSP_INTC_BASE + 0x000)
#define INTC_IRQ_STA0                    (MTK_ADSP_INTC_BASE + 0x008)
#define INTC_IRQ_STA1                    (MTK_ADSP_INTC_BASE + 0x00c)
#define INTC_IRQ_EN0                     (MTK_ADSP_INTC_BASE + 0x010)
#define INTC_IRQ_POL0                    (MTK_ADSP_INTC_BASE + 0x018)
#define INTC_IRQ_WAKE_EN0                (MTK_ADSP_INTC_BASE + 0x020)
#define INTC_IRQ_STAGE1_EN0              (MTK_ADSP_INTC_BASE + 0x030)
#define INTC_IRQ_GRP0_0                  (MTK_ADSP_INTC_BASE + 0x040)
#define INTC_IRQ_GRP0_STA0               (MTK_ADSP_INTC_BASE + 0x0C0)
#define INTC_GRP_IRQ_OUT_STA             (MTK_ADSP_INTC_BASE + 0x140)

#define MTK_GPR_RW_REG0			(MTK_DSP_CFGREG_BASE + 0x0440)
#define MTK_GPR_RW_REG1			(MTK_DSP_CFGREG_BASE + 0x0444)
#define MTK_GPR_RW_REG2			(MTK_DSP_CFGREG_BASE + 0x0448)
#define MTK_GPR_RW_REG3			(MTK_DSP_CFGREG_BASE + 0x044c)
#define MTK_GPR_RW_REG4			(MTK_DSP_CFGREG_BASE + 0x0450)
#define MTK_GPR_RW_REG5			(MTK_DSP_CFGREG_BASE + 0x0454)
#define MTK_GPR_RW_REG6			(MTK_DSP_CFGREG_BASE + 0x0458)
#define MTK_GPR_RW_REG7			(MTK_DSP_CFGREG_BASE + 0x045c)
#define MTK_GPR_RW_REG8			(MTK_DSP_CFGREG_BASE + 0x0460)
#define MTK_GPR_RW_REG9			(MTK_DSP_CFGREG_BASE + 0x0464)
#define MTK_GPR_RW_REG10		(MTK_DSP_CFGREG_BASE + 0x0468)
#define MTK_GPR_RW_REG11		(MTK_DSP_CFGREG_BASE + 0x046c)
#define MTK_GPR_RW_REG12		(MTK_DSP_CFGREG_BASE + 0x0470)
#define MTK_GPR_RW_REG13		(MTK_DSP_CFGREG_BASE + 0x0474)
#define MTK_GPR_RW_REG14		(MTK_DSP_CFGREG_BASE + 0x0478)
#define MTK_GPR_RW_REG15		(MTK_DSP_CFGREG_BASE + 0x047c)
#define MTK_GPR_RW_REG16		(MTK_DSP_CFGREG_BASE + 0x0480)
#define MTK_GPR_RW_REG17		(MTK_DSP_CFGREG_BASE + 0x0484)
#define MTK_GPR_RW_REG18		(MTK_DSP_CFGREG_BASE + 0x0488)
#define MTK_GPR_RW_REG19		(MTK_DSP_CFGREG_BASE + 0x048c)
#define MTK_GPR_RW_REG20		(MTK_DSP_CFGREG_BASE + 0x0490)
#define MTK_GPR_RW_REG21		(MTK_DSP_CFGREG_BASE + 0x0494)
#define MTK_GPR_RW_REG22		(MTK_DSP_CFGREG_BASE + 0x0498)
#define MTK_GPR_RW_REG23		(MTK_DSP_CFGREG_BASE + 0x049c)
#define MTK_GPR_RW_REG24		(MTK_DSP_CFGREG_BASE + 0x04a0)
#define MTK_GPR_RW_REG25		(MTK_DSP_CFGREG_BASE + 0x04a4)
#define MTK_GPR_RW_REG26		(MTK_DSP_CFGREG_BASE + 0x04a8)
#define MTK_GPR_RW_REG27		(MTK_DSP_CFGREG_BASE + 0x04ac)
/* use for tickless status */
#define MTK_GPR_RW_REG28		(MTK_DSP_CFGREG_BASE + 0x04b0)
#define MTK_GPR_RW_REG29		(MTK_DSP_CFGREG_BASE + 0x04b4)

#define MTK_ADSP_IRQ_OUT_MASK		(MTK_DSP_CFGREG_BASE + 0x0500)

#define MTK_DSP_CKCTRL_BASE		(MTK_DSP_CFGREG_BASE + 0x1000)
#define MTK_DSP_CKCTRL_SIZE		0x1000

#define MTK_DSP_OS_TIMER_BASE		(MTK_DSP_CFGREG_BASE + 0xB000)
#define MTK_DSP_OS_TIMER_SIZE		0x1000

#define MTK_DSP_UART0_BASE		(MTK_DSP_CFGREG_BASE + 0xD000)
#define MTK_DSP_UART0_SIZE		0x1000
#define MTK_DSP_BT_UART_BASE           (MTK_DSP_CFGREG_BASE + 0xE000)
#define MTK_DSP_BT_UART_SIZE		0x1000

#define MTK_DSP_BUS_BASE		(MTK_DSP_CFGREG_BASE + 0xF000)
#define MTK_DSP_BUS_SIZE		0x1000

#define MTK_DSP_SECURE_BASE		(MTK_DSP_CFGREG_BASE + 0x345000)
#define MTK_MBOX_IRQ_IN                 (MTK_DSP_SECURE_BASE + 0x70)

/* MBOX registers */
#define MTK_ADSP_MBOX_BASE		(MTK_DSP_CFGREG_BASE + 0x350000)
#define MTK_ADSP_MBOX_REG_BASE(x)	(MTK_ADSP_MBOX_BASE + (0x10000 * (x)))
#define MTK_ADSP_MBOX_REG_SIZE		(0x50000)
#define MTK_ADSP_MBOX_IN_CMD(x)		(MTK_ADSP_MBOX_REG_BASE(x) + 0x100)
#define MTK_ADSP_MBOX_IN_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x108)
#define MTK_ADSP_MBOX_OUT_CMD(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x104)
#define MTK_ADSP_MBOX_OUT_CMD_CLR(x)	(MTK_ADSP_MBOX_REG_BASE(x) + 0x10c)

#endif /* MT_REG_BASE_H */
