/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright(c) 2021 MediaTek. All rights reserved.
 *
 * Author: YC Hung <yc.hung@mediatek.com>
 */

#ifndef _MT_8195_AFE_COMMON_H_
#define _MT_8195_AFE_COMMON_H_

/* AFE: the abbreviation for Audio Front End  */

enum {
	MT8195_MEMIF_START,
	MT8195_MEMIF_DL_START = MT8195_MEMIF_START,
	MT8195_MEMIF_DL2 = MT8195_MEMIF_DL_START,
	MT8195_MEMIF_DL3,
	MT8195_MEMIF_DL_END,
	MT8195_MEMIF_UL_START = MT8195_MEMIF_DL_END,
	MT8195_MEMIF_UL4 = MT8195_MEMIF_UL_START,
	MT8195_MEMIF_UL5,
	MT8195_MEMIF_UL_END,
	MT8195_MEMIF_END = MT8195_MEMIF_UL_END,
	MT8195_MEMIF_DL_NUM = (MT8195_MEMIF_DL_END - MT8195_MEMIF_DL_START),
	MT8195_MEMIF_UL_NUM = (MT8195_MEMIF_UL_END - MT8195_MEMIF_UL_START),
	MT8195_MEMIF_NUM = (MT8195_MEMIF_END - MT8195_MEMIF_START),
};

enum {
	MT8195_IRQ_0,
	MT8195_IRQ_1,
	MT8195_IRQ_2,
	MT8195_IRQ_3,
	MT8195_IRQ_4,
	MT8195_IRQ_5,
	MT8195_IRQ_6,
	MT8195_IRQ_7,
	MT8195_IRQ_8,
	MT8195_IRQ_9,
	MT8195_IRQ_10,
	MT8195_IRQ_11,
	MT8195_IRQ_12,
	MT8195_IRQ_13,
	MT8195_IRQ_14,
	MT8195_IRQ_15,
	MT8195_IRQ_16,
	MT8195_IRQ_17,
	MT8195_IRQ_18,
	MT8195_IRQ_19,
	MT8195_IRQ_20,
	MT8195_IRQ_21,
	MT8195_IRQ_22,
	MT8195_IRQ_23,
	MT8195_IRQ_24,
	MT8195_IRQ_25,
	MT8195_IRQ_26,
	MT8195_IRQ_31, /* used only for TDM */
	MT8195_IRQ_NUM,
};

enum {
	MT8195_AFE_IO_ETDM2_OUT,
	MT8195_AFE_IO_ETDM1_OUT,
	MT8195_AFE_IO_UL_SRC1,
	MT8195_AFE_IO_ETDM2_IN,
	MT8195_DAI_NUM,
};

#endif
