// Copyright 2010 fail0verflow <master@fail0verflow.com>
// Licensed under the terms of the GNU GPL, version 2
// http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
#ifndef EMULATE_INSTRS_H__
#define EMULATE_INSTRS_H__

#include <stdio.h>
#include <stdint.h>
#include "config.h"
#include "types.h"
#include "emulate.h"

int instr_cdd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_rotqmbii(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_clgt(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fcgt(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_nand(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_iohl(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_gb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpyhh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_frds(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_cdx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_andbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_dfms(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_orbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_clz(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_absdb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_dfma(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_brhz(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_cntb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_stop(spe_ctx_t *ctx, uint32_t opcode);
int instr_ceqi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_ceqh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_biz(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ceq(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ceqb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqbyi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_nop(spe_ctx_t *ctx, uint32_t opcode);
int instr_sumb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_nor(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpy(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_dsync(spe_ctx_t *ctx, uint32_t opcode);
int instr_mpys(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_gbb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpyu(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotmai(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_gbh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_roti(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_mpya(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_rdch(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotm(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_xsbh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ilhu(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_cgti(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_mpyh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpyi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_shl(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_brsl(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_shlqbybi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_clgthi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_sync(spe_ctx_t *ctx, uint32_t opcode);
int instr_cflts(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i8);
int instr_cfltu(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i8);
int instr_heqi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_cwx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_xor(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqmbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_bihz(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ceqhi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_mpyhhau(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_avgb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_addx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqmby(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mfspr(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_stopd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_xorhi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_cwd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_bg(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_orx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_bi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_csflt(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i8);
int instr_cgx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_sfhi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_br(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_ori(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_andi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_orc(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_frsqest(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ila(spe_ctx_t *ctx, uint32_t rt, uint32_t i18);
int instr_xswd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_ilh(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_bisl(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqmbyi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_bgx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_or(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_hbr(spe_ctx_t *ctx, uint32_t opcode);
int instr_brz(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_selb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_brhnz(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_ahi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_cg(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_hbrr(spe_ctx_t *ctx, uint32_t rt, uint32_t i18);
int instr_mpyui(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_xori(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_fsmbi(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_dfs(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_shufb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_bihnz(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_bra(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_chd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_rchcnt(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fsmh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpyhhu(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_xorbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_lnop(spe_ctx_t *ctx, uint32_t opcode);
int instr_fsmb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fms(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_andc(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_eqv(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_dfm(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mpyhha(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotma(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_chx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rothmi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_rotmi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_clgtbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_fma(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_dfnms(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fesd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_clgtb(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_clgti(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_clgth(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_shli(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_fnms(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb, uint32_t rc);
int instr_shlqbii(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_ceqbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_dfa(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_shlqby(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_shlqbyi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_fceq(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_shlqbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_and(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_stqd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_cbd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);
int instr_stqa(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_ai(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_ah(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqby(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_hbra(spe_ctx_t *ctx, uint32_t rt, uint32_t i18);
int instr_stqr(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_il(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_cbx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_mtspr(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_stqx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_cgt(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_lqx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqbybi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_lqr(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_rotqbi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_wrch(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_lqd(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_cgthi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_rotqmbybi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_lqa(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_fs(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_brasl(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_sfx(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_brnz(spe_ctx_t *ctx, uint32_t rt, uint32_t i16);
int instr_andhi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_fa(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_orhi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_sfh(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_sfi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i10);
int instr_xshw(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fi(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fm(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_a(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_frest(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_fsm(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_binz(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_sf(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t rb);
int instr_rotqbii(spe_ctx_t *ctx, uint32_t rt, uint32_t ra, uint32_t i7);


enum spu_instr_type {
	SPU_INSTR_RR,
	SPU_INSTR_RRR,
	SPU_INSTR_RI7,
	SPU_INSTR_RI8,
	SPU_INSTR_RI10,
	SPU_INSTR_RI16,
	SPU_INSTR_RI18,
	SPU_INSTR_SPECIAL,
	SPU_INSTR_NONE
};

static const struct {
	enum spu_instr_type type;
	void *ptr;
} instr_tbl[] =
{
	{SPU_INSTR_SPECIAL, instr_stop}, // 00000000
	{SPU_INSTR_SPECIAL, instr_lnop}, // 02000000
	{SPU_INSTR_SPECIAL, instr_sync}, // 04000000
	{SPU_INSTR_SPECIAL, instr_dsync}, // 06000000
	{SPU_INSTR_NONE, NULL}, // 08000000
	{SPU_INSTR_NONE, NULL}, // 0a000000
	{SPU_INSTR_NONE, NULL}, // 0c000000
	{SPU_INSTR_NONE, NULL}, // 0e000000
	{SPU_INSTR_NONE, NULL}, // 10000000
	{SPU_INSTR_NONE, NULL}, // 12000000
	{SPU_INSTR_NONE, NULL}, // 14000000
	{SPU_INSTR_NONE, NULL}, // 16000000
	{SPU_INSTR_RR, instr_mfspr}, // 18000000
	{SPU_INSTR_RR, instr_rdch}, // 1a000000
	{SPU_INSTR_NONE, NULL}, // 1c000000
	{SPU_INSTR_RR, instr_rchcnt}, // 1e000000
	{SPU_INSTR_NONE, NULL}, // 20000000
	{SPU_INSTR_NONE, NULL}, // 22000000
	{SPU_INSTR_NONE, NULL}, // 24000000
	{SPU_INSTR_NONE, NULL}, // 26000000
	{SPU_INSTR_NONE, NULL}, // 28000000
	{SPU_INSTR_NONE, NULL}, // 2a000000
	{SPU_INSTR_NONE, NULL}, // 2c000000
	{SPU_INSTR_NONE, NULL}, // 2e000000
	{SPU_INSTR_NONE, NULL}, // 30000000
	{SPU_INSTR_NONE, NULL}, // 32000000
	{SPU_INSTR_NONE, NULL}, // 34000000
	{SPU_INSTR_NONE, NULL}, // 36000000
	{SPU_INSTR_NONE, NULL}, // 38000000
	{SPU_INSTR_NONE, NULL}, // 3a000000
	{SPU_INSTR_NONE, NULL}, // 3c000000
	{SPU_INSTR_NONE, NULL}, // 3e000000
	{SPU_INSTR_RI10, instr_ori}, // 40000000
	{SPU_INSTR_RI10, instr_ori}, // 42000000
	{SPU_INSTR_RI10, instr_ori}, // 44000000
	{SPU_INSTR_RI10, instr_ori}, // 46000000
	{SPU_INSTR_RI10, instr_ori}, // 48000000
	{SPU_INSTR_RI10, instr_ori}, // 4a000000
	{SPU_INSTR_RI10, instr_ori}, // 4c000000
	{SPU_INSTR_RI10, instr_ori}, // 4e000000
	{SPU_INSTR_RI10, instr_orhi}, // 50000000
	{SPU_INSTR_RI10, instr_orhi}, // 52000000
	{SPU_INSTR_RI10, instr_orhi}, // 54000000
	{SPU_INSTR_RI10, instr_orhi}, // 56000000
	{SPU_INSTR_RI10, instr_orhi}, // 58000000
	{SPU_INSTR_RI10, instr_orhi}, // 5a000000
	{SPU_INSTR_RI10, instr_orhi}, // 5c000000
	{SPU_INSTR_RI10, instr_orhi}, // 5e000000
	{SPU_INSTR_RI10, instr_orbi}, // 60000000
	{SPU_INSTR_RI10, instr_orbi}, // 62000000
	{SPU_INSTR_RI10, instr_orbi}, // 64000000
	{SPU_INSTR_RI10, instr_orbi}, // 66000000
	{SPU_INSTR_RI10, instr_orbi}, // 68000000
	{SPU_INSTR_RI10, instr_orbi}, // 6a000000
	{SPU_INSTR_RI10, instr_orbi}, // 6c000000
	{SPU_INSTR_RI10, instr_orbi}, // 6e000000
	{SPU_INSTR_NONE, NULL}, // 70000000
	{SPU_INSTR_NONE, NULL}, // 72000000
	{SPU_INSTR_NONE, NULL}, // 74000000
	{SPU_INSTR_NONE, NULL}, // 76000000
	{SPU_INSTR_NONE, NULL}, // 78000000
	{SPU_INSTR_NONE, NULL}, // 7a000000
	{SPU_INSTR_NONE, NULL}, // 7c000000
	{SPU_INSTR_NONE, NULL}, // 7e000000
	{SPU_INSTR_RR, instr_sf}, // 80000000
	{SPU_INSTR_RR, instr_or}, // 82000000
	{SPU_INSTR_RR, instr_bg}, // 84000000
	{SPU_INSTR_NONE, NULL}, // 86000000
	{SPU_INSTR_NONE, NULL}, // 88000000
	{SPU_INSTR_NONE, NULL}, // 8a000000
	{SPU_INSTR_NONE, NULL}, // 8c000000
	{SPU_INSTR_NONE, NULL}, // 8e000000
	{SPU_INSTR_RR, instr_sfh}, // 90000000
	{SPU_INSTR_RR, instr_nor}, // 92000000
	{SPU_INSTR_NONE, NULL}, // 94000000
	{SPU_INSTR_NONE, NULL}, // 96000000
	{SPU_INSTR_NONE, NULL}, // 98000000
	{SPU_INSTR_NONE, NULL}, // 9a000000
	{SPU_INSTR_NONE, NULL}, // 9c000000
	{SPU_INSTR_NONE, NULL}, // 9e000000
	{SPU_INSTR_NONE, NULL}, // a0000000
	{SPU_INSTR_NONE, NULL}, // a2000000
	{SPU_INSTR_NONE, NULL}, // a4000000
	{SPU_INSTR_RR, instr_absdb}, // a6000000
	{SPU_INSTR_NONE, NULL}, // a8000000
	{SPU_INSTR_NONE, NULL}, // aa000000
	{SPU_INSTR_NONE, NULL}, // ac000000
	{SPU_INSTR_NONE, NULL}, // ae000000
	{SPU_INSTR_NONE, NULL}, // b0000000
	{SPU_INSTR_RR, instr_rotm}, // b2000000
	{SPU_INSTR_RR, instr_rotma}, // b4000000
	{SPU_INSTR_RR, instr_shl}, // b6000000
	{SPU_INSTR_NONE, NULL}, // b8000000
	{SPU_INSTR_NONE, NULL}, // ba000000
	{SPU_INSTR_NONE, NULL}, // bc000000
	{SPU_INSTR_NONE, NULL}, // be000000
	{SPU_INSTR_RI10, instr_sfi}, // c0000000
	{SPU_INSTR_RI10, instr_sfi}, // c2000000
	{SPU_INSTR_RI10, instr_sfi}, // c4000000
	{SPU_INSTR_RI10, instr_sfi}, // c6000000
	{SPU_INSTR_RI10, instr_sfi}, // c8000000
	{SPU_INSTR_RI10, instr_sfi}, // ca000000
	{SPU_INSTR_RI10, instr_sfi}, // cc000000
	{SPU_INSTR_RI10, instr_sfi}, // ce000000
	{SPU_INSTR_RI10, instr_sfhi}, // d0000000
	{SPU_INSTR_RI10, instr_sfhi}, // d2000000
	{SPU_INSTR_RI10, instr_sfhi}, // d4000000
	{SPU_INSTR_RI10, instr_sfhi}, // d6000000
	{SPU_INSTR_RI10, instr_sfhi}, // d8000000
	{SPU_INSTR_RI10, instr_sfhi}, // da000000
	{SPU_INSTR_RI10, instr_sfhi}, // dc000000
	{SPU_INSTR_RI10, instr_sfhi}, // de000000
	{SPU_INSTR_NONE, NULL}, // e0000000
	{SPU_INSTR_NONE, NULL}, // e2000000
	{SPU_INSTR_NONE, NULL}, // e4000000
	{SPU_INSTR_NONE, NULL}, // e6000000
	{SPU_INSTR_NONE, NULL}, // e8000000
	{SPU_INSTR_NONE, NULL}, // ea000000
	{SPU_INSTR_NONE, NULL}, // ec000000
	{SPU_INSTR_NONE, NULL}, // ee000000
	{SPU_INSTR_RI7, instr_roti}, // f0000000
	{SPU_INSTR_RI7, instr_rotmi}, // f2000000
	{SPU_INSTR_RI7, instr_rotmai}, // f4000000
	{SPU_INSTR_RI7, instr_shli}, // f6000000
	{SPU_INSTR_NONE, NULL}, // f8000000
	{SPU_INSTR_RI7, instr_rothmi}, // fa000000
	{SPU_INSTR_NONE, NULL}, // fc000000
	{SPU_INSTR_NONE, NULL}, // fe000000
	{SPU_INSTR_RI18, instr_hbra}, // 100000000
	{SPU_INSTR_RI18, instr_hbra}, // 102000000
	{SPU_INSTR_RI18, instr_hbra}, // 104000000
	{SPU_INSTR_RI18, instr_hbra}, // 106000000
	{SPU_INSTR_RI18, instr_hbra}, // 108000000
	{SPU_INSTR_RI18, instr_hbra}, // 10a000000
	{SPU_INSTR_RI18, instr_hbra}, // 10c000000
	{SPU_INSTR_RI18, instr_hbra}, // 10e000000
	{SPU_INSTR_RI18, instr_hbra}, // 110000000
	{SPU_INSTR_RI18, instr_hbra}, // 112000000
	{SPU_INSTR_RI18, instr_hbra}, // 114000000
	{SPU_INSTR_RI18, instr_hbra}, // 116000000
	{SPU_INSTR_RI18, instr_hbra}, // 118000000
	{SPU_INSTR_RI18, instr_hbra}, // 11a000000
	{SPU_INSTR_RI18, instr_hbra}, // 11c000000
	{SPU_INSTR_RI18, instr_hbra}, // 11e000000
	{SPU_INSTR_RI18, instr_hbrr}, // 120000000
	{SPU_INSTR_RI18, instr_hbrr}, // 122000000
	{SPU_INSTR_RI18, instr_hbrr}, // 124000000
	{SPU_INSTR_RI18, instr_hbrr}, // 126000000
	{SPU_INSTR_RI18, instr_hbrr}, // 128000000
	{SPU_INSTR_RI18, instr_hbrr}, // 12a000000
	{SPU_INSTR_RI18, instr_hbrr}, // 12c000000
	{SPU_INSTR_RI18, instr_hbrr}, // 12e000000
	{SPU_INSTR_RI18, instr_hbrr}, // 130000000
	{SPU_INSTR_RI18, instr_hbrr}, // 132000000
	{SPU_INSTR_RI18, instr_hbrr}, // 134000000
	{SPU_INSTR_RI18, instr_hbrr}, // 136000000
	{SPU_INSTR_RI18, instr_hbrr}, // 138000000
	{SPU_INSTR_RI18, instr_hbrr}, // 13a000000
	{SPU_INSTR_RI18, instr_hbrr}, // 13c000000
	{SPU_INSTR_RI18, instr_hbrr}, // 13e000000
	{SPU_INSTR_RI10, instr_andi}, // 140000000
	{SPU_INSTR_RI10, instr_andi}, // 142000000
	{SPU_INSTR_RI10, instr_andi}, // 144000000
	{SPU_INSTR_RI10, instr_andi}, // 146000000
	{SPU_INSTR_RI10, instr_andi}, // 148000000
	{SPU_INSTR_RI10, instr_andi}, // 14a000000
	{SPU_INSTR_RI10, instr_andi}, // 14c000000
	{SPU_INSTR_RI10, instr_andi}, // 14e000000
	{SPU_INSTR_RI10, instr_andhi}, // 150000000
	{SPU_INSTR_RI10, instr_andhi}, // 152000000
	{SPU_INSTR_RI10, instr_andhi}, // 154000000
	{SPU_INSTR_RI10, instr_andhi}, // 156000000
	{SPU_INSTR_RI10, instr_andhi}, // 158000000
	{SPU_INSTR_RI10, instr_andhi}, // 15a000000
	{SPU_INSTR_RI10, instr_andhi}, // 15c000000
	{SPU_INSTR_RI10, instr_andhi}, // 15e000000
	{SPU_INSTR_RI10, instr_andbi}, // 160000000
	{SPU_INSTR_RI10, instr_andbi}, // 162000000
	{SPU_INSTR_RI10, instr_andbi}, // 164000000
	{SPU_INSTR_RI10, instr_andbi}, // 166000000
	{SPU_INSTR_RI10, instr_andbi}, // 168000000
	{SPU_INSTR_RI10, instr_andbi}, // 16a000000
	{SPU_INSTR_RI10, instr_andbi}, // 16c000000
	{SPU_INSTR_RI10, instr_andbi}, // 16e000000
	{SPU_INSTR_NONE, NULL}, // 170000000
	{SPU_INSTR_NONE, NULL}, // 172000000
	{SPU_INSTR_NONE, NULL}, // 174000000
	{SPU_INSTR_NONE, NULL}, // 176000000
	{SPU_INSTR_NONE, NULL}, // 178000000
	{SPU_INSTR_NONE, NULL}, // 17a000000
	{SPU_INSTR_NONE, NULL}, // 17c000000
	{SPU_INSTR_NONE, NULL}, // 17e000000
	{SPU_INSTR_RR, instr_a}, // 180000000
	{SPU_INSTR_RR, instr_and}, // 182000000
	{SPU_INSTR_RR, instr_cg}, // 184000000
	{SPU_INSTR_NONE, NULL}, // 186000000
	{SPU_INSTR_NONE, NULL}, // 188000000
	{SPU_INSTR_NONE, NULL}, // 18a000000
	{SPU_INSTR_NONE, NULL}, // 18c000000
	{SPU_INSTR_NONE, NULL}, // 18e000000
	{SPU_INSTR_RR, instr_ah}, // 190000000
	{SPU_INSTR_RR, instr_nand}, // 192000000
	{SPU_INSTR_NONE, NULL}, // 194000000
	{SPU_INSTR_NONE, NULL}, // 196000000
	{SPU_INSTR_NONE, NULL}, // 198000000
	{SPU_INSTR_NONE, NULL}, // 19a000000
	{SPU_INSTR_NONE, NULL}, // 19c000000
	{SPU_INSTR_NONE, NULL}, // 19e000000
	{SPU_INSTR_NONE, NULL}, // 1a0000000
	{SPU_INSTR_NONE, NULL}, // 1a2000000
	{SPU_INSTR_NONE, NULL}, // 1a4000000
	{SPU_INSTR_RR, instr_avgb}, // 1a6000000
	{SPU_INSTR_NONE, NULL}, // 1a8000000
	{SPU_INSTR_NONE, NULL}, // 1aa000000
	{SPU_INSTR_NONE, NULL}, // 1ac000000
	{SPU_INSTR_NONE, NULL}, // 1ae000000
	{SPU_INSTR_NONE, NULL}, // 1b0000000
	{SPU_INSTR_NONE, NULL}, // 1b2000000
	{SPU_INSTR_NONE, NULL}, // 1b4000000
	{SPU_INSTR_NONE, NULL}, // 1b6000000
	{SPU_INSTR_NONE, NULL}, // 1b8000000
	{SPU_INSTR_NONE, NULL}, // 1ba000000
	{SPU_INSTR_NONE, NULL}, // 1bc000000
	{SPU_INSTR_NONE, NULL}, // 1be000000
	{SPU_INSTR_RI10, instr_ai}, // 1c0000000
	{SPU_INSTR_RI10, instr_ai}, // 1c2000000
	{SPU_INSTR_RI10, instr_ai}, // 1c4000000
	{SPU_INSTR_RI10, instr_ai}, // 1c6000000
	{SPU_INSTR_RI10, instr_ai}, // 1c8000000
	{SPU_INSTR_RI10, instr_ai}, // 1ca000000
	{SPU_INSTR_RI10, instr_ai}, // 1cc000000
	{SPU_INSTR_RI10, instr_ai}, // 1ce000000
	{SPU_INSTR_RI10, instr_ahi}, // 1d0000000
	{SPU_INSTR_RI10, instr_ahi}, // 1d2000000
	{SPU_INSTR_RI10, instr_ahi}, // 1d4000000
	{SPU_INSTR_RI10, instr_ahi}, // 1d6000000
	{SPU_INSTR_RI10, instr_ahi}, // 1d8000000
	{SPU_INSTR_RI10, instr_ahi}, // 1da000000
	{SPU_INSTR_RI10, instr_ahi}, // 1dc000000
	{SPU_INSTR_RI10, instr_ahi}, // 1de000000
	{SPU_INSTR_NONE, NULL}, // 1e0000000
	{SPU_INSTR_NONE, NULL}, // 1e2000000
	{SPU_INSTR_NONE, NULL}, // 1e4000000
	{SPU_INSTR_NONE, NULL}, // 1e6000000
	{SPU_INSTR_NONE, NULL}, // 1e8000000
	{SPU_INSTR_NONE, NULL}, // 1ea000000
	{SPU_INSTR_NONE, NULL}, // 1ec000000
	{SPU_INSTR_NONE, NULL}, // 1ee000000
	{SPU_INSTR_NONE, NULL}, // 1f0000000
	{SPU_INSTR_NONE, NULL}, // 1f2000000
	{SPU_INSTR_NONE, NULL}, // 1f4000000
	{SPU_INSTR_NONE, NULL}, // 1f6000000
	{SPU_INSTR_NONE, NULL}, // 1f8000000
	{SPU_INSTR_NONE, NULL}, // 1fa000000
	{SPU_INSTR_NONE, NULL}, // 1fc000000
	{SPU_INSTR_NONE, NULL}, // 1fe000000
	{SPU_INSTR_RI16, instr_brz}, // 200000000
	{SPU_INSTR_RI16, instr_brz}, // 202000000
	{SPU_INSTR_RI16, instr_brz}, // 204000000
	{SPU_INSTR_RI16, instr_brz}, // 206000000
	{SPU_INSTR_RI16, instr_stqa}, // 208000000
	{SPU_INSTR_RI16, instr_stqa}, // 20a000000
	{SPU_INSTR_RI16, instr_stqa}, // 20c000000
	{SPU_INSTR_RI16, instr_stqa}, // 20e000000
	{SPU_INSTR_RI16, instr_brnz}, // 210000000
	{SPU_INSTR_RI16, instr_brnz}, // 212000000
	{SPU_INSTR_RI16, instr_brnz}, // 214000000
	{SPU_INSTR_RI16, instr_brnz}, // 216000000
	{SPU_INSTR_RR, instr_mtspr}, // 218000000
	{SPU_INSTR_RR, instr_wrch}, // 21a000000
	{SPU_INSTR_NONE, NULL}, // 21c000000
	{SPU_INSTR_NONE, NULL}, // 21e000000
	{SPU_INSTR_RI16, instr_brhz}, // 220000000
	{SPU_INSTR_RI16, instr_brhz}, // 222000000
	{SPU_INSTR_RI16, instr_brhz}, // 224000000
	{SPU_INSTR_RI16, instr_brhz}, // 226000000
	{SPU_INSTR_NONE, NULL}, // 228000000
	{SPU_INSTR_NONE, NULL}, // 22a000000
	{SPU_INSTR_NONE, NULL}, // 22c000000
	{SPU_INSTR_NONE, NULL}, // 22e000000
	{SPU_INSTR_RI16, instr_brhnz}, // 230000000
	{SPU_INSTR_RI16, instr_brhnz}, // 232000000
	{SPU_INSTR_RI16, instr_brhnz}, // 234000000
	{SPU_INSTR_RI16, instr_brhnz}, // 236000000
	{SPU_INSTR_RI16, instr_stqr}, // 238000000
	{SPU_INSTR_RI16, instr_stqr}, // 23a000000
	{SPU_INSTR_RI16, instr_stqr}, // 23c000000
	{SPU_INSTR_RI16, instr_stqr}, // 23e000000
	{SPU_INSTR_RI10, instr_stqd}, // 240000000
	{SPU_INSTR_RI10, instr_stqd}, // 242000000
	{SPU_INSTR_RI10, instr_stqd}, // 244000000
	{SPU_INSTR_RI10, instr_stqd}, // 246000000
	{SPU_INSTR_RI10, instr_stqd}, // 248000000
	{SPU_INSTR_RI10, instr_stqd}, // 24a000000
	{SPU_INSTR_RI10, instr_stqd}, // 24c000000
	{SPU_INSTR_RI10, instr_stqd}, // 24e000000
	{SPU_INSTR_RR, instr_biz}, // 250000000
	{SPU_INSTR_RR, instr_binz}, // 252000000
	{SPU_INSTR_RR, instr_bihz}, // 254000000
	{SPU_INSTR_RR, instr_bihnz}, // 256000000
	{SPU_INSTR_NONE, NULL}, // 258000000
	{SPU_INSTR_NONE, NULL}, // 25a000000
	{SPU_INSTR_NONE, NULL}, // 25c000000
	{SPU_INSTR_NONE, NULL}, // 25e000000
	{SPU_INSTR_NONE, NULL}, // 260000000
	{SPU_INSTR_NONE, NULL}, // 262000000
	{SPU_INSTR_NONE, NULL}, // 264000000
	{SPU_INSTR_NONE, NULL}, // 266000000
	{SPU_INSTR_NONE, NULL}, // 268000000
	{SPU_INSTR_NONE, NULL}, // 26a000000
	{SPU_INSTR_NONE, NULL}, // 26c000000
	{SPU_INSTR_NONE, NULL}, // 26e000000
	{SPU_INSTR_NONE, NULL}, // 270000000
	{SPU_INSTR_NONE, NULL}, // 272000000
	{SPU_INSTR_NONE, NULL}, // 274000000
	{SPU_INSTR_NONE, NULL}, // 276000000
	{SPU_INSTR_NONE, NULL}, // 278000000
	{SPU_INSTR_NONE, NULL}, // 27a000000
	{SPU_INSTR_NONE, NULL}, // 27c000000
	{SPU_INSTR_NONE, NULL}, // 27e000000
	{SPU_INSTR_RR, instr_stopd}, // 280000000
	{SPU_INSTR_NONE, NULL}, // 282000000
	{SPU_INSTR_NONE, NULL}, // 284000000
	{SPU_INSTR_NONE, NULL}, // 286000000
	{SPU_INSTR_RR, instr_stqx}, // 288000000
	{SPU_INSTR_NONE, NULL}, // 28a000000
	{SPU_INSTR_NONE, NULL}, // 28c000000
	{SPU_INSTR_NONE, NULL}, // 28e000000
	{SPU_INSTR_NONE, NULL}, // 290000000
	{SPU_INSTR_NONE, NULL}, // 292000000
	{SPU_INSTR_NONE, NULL}, // 294000000
	{SPU_INSTR_NONE, NULL}, // 296000000
	{SPU_INSTR_NONE, NULL}, // 298000000
	{SPU_INSTR_NONE, NULL}, // 29a000000
	{SPU_INSTR_NONE, NULL}, // 29c000000
	{SPU_INSTR_NONE, NULL}, // 29e000000
	{SPU_INSTR_NONE, NULL}, // 2a0000000
	{SPU_INSTR_NONE, NULL}, // 2a2000000
	{SPU_INSTR_NONE, NULL}, // 2a4000000
	{SPU_INSTR_NONE, NULL}, // 2a6000000
	{SPU_INSTR_NONE, NULL}, // 2a8000000
	{SPU_INSTR_NONE, NULL}, // 2aa000000
	{SPU_INSTR_NONE, NULL}, // 2ac000000
	{SPU_INSTR_NONE, NULL}, // 2ae000000
	{SPU_INSTR_NONE, NULL}, // 2b0000000
	{SPU_INSTR_NONE, NULL}, // 2b2000000
	{SPU_INSTR_NONE, NULL}, // 2b4000000
	{SPU_INSTR_NONE, NULL}, // 2b6000000
	{SPU_INSTR_NONE, NULL}, // 2b8000000
	{SPU_INSTR_NONE, NULL}, // 2ba000000
	{SPU_INSTR_NONE, NULL}, // 2bc000000
	{SPU_INSTR_NONE, NULL}, // 2be000000
	{SPU_INSTR_NONE, NULL}, // 2c0000000
	{SPU_INSTR_NONE, NULL}, // 2c2000000
	{SPU_INSTR_NONE, NULL}, // 2c4000000
	{SPU_INSTR_NONE, NULL}, // 2c6000000
	{SPU_INSTR_NONE, NULL}, // 2c8000000
	{SPU_INSTR_NONE, NULL}, // 2ca000000
	{SPU_INSTR_NONE, NULL}, // 2cc000000
	{SPU_INSTR_NONE, NULL}, // 2ce000000
	{SPU_INSTR_NONE, NULL}, // 2d0000000
	{SPU_INSTR_NONE, NULL}, // 2d2000000
	{SPU_INSTR_NONE, NULL}, // 2d4000000
	{SPU_INSTR_NONE, NULL}, // 2d6000000
	{SPU_INSTR_NONE, NULL}, // 2d8000000
	{SPU_INSTR_NONE, NULL}, // 2da000000
	{SPU_INSTR_NONE, NULL}, // 2dc000000
	{SPU_INSTR_NONE, NULL}, // 2de000000
	{SPU_INSTR_NONE, NULL}, // 2e0000000
	{SPU_INSTR_NONE, NULL}, // 2e2000000
	{SPU_INSTR_NONE, NULL}, // 2e4000000
	{SPU_INSTR_NONE, NULL}, // 2e6000000
	{SPU_INSTR_NONE, NULL}, // 2e8000000
	{SPU_INSTR_NONE, NULL}, // 2ea000000
	{SPU_INSTR_NONE, NULL}, // 2ec000000
	{SPU_INSTR_NONE, NULL}, // 2ee000000
	{SPU_INSTR_NONE, NULL}, // 2f0000000
	{SPU_INSTR_NONE, NULL}, // 2f2000000
	{SPU_INSTR_NONE, NULL}, // 2f4000000
	{SPU_INSTR_NONE, NULL}, // 2f6000000
	{SPU_INSTR_NONE, NULL}, // 2f8000000
	{SPU_INSTR_NONE, NULL}, // 2fa000000
	{SPU_INSTR_NONE, NULL}, // 2fc000000
	{SPU_INSTR_NONE, NULL}, // 2fe000000
	{SPU_INSTR_RI16, instr_bra}, // 300000000
	{SPU_INSTR_RI16, instr_bra}, // 302000000
	{SPU_INSTR_RI16, instr_bra}, // 304000000
	{SPU_INSTR_RI16, instr_bra}, // 306000000
	{SPU_INSTR_RI16, instr_lqa}, // 308000000
	{SPU_INSTR_RI16, instr_lqa}, // 30a000000
	{SPU_INSTR_RI16, instr_lqa}, // 30c000000
	{SPU_INSTR_RI16, instr_lqa}, // 30e000000
	{SPU_INSTR_RI16, instr_brasl}, // 310000000
	{SPU_INSTR_RI16, instr_brasl}, // 312000000
	{SPU_INSTR_RI16, instr_brasl}, // 314000000
	{SPU_INSTR_RI16, instr_brasl}, // 316000000
	{SPU_INSTR_NONE, NULL}, // 318000000
	{SPU_INSTR_NONE, NULL}, // 31a000000
	{SPU_INSTR_NONE, NULL}, // 31c000000
	{SPU_INSTR_NONE, NULL}, // 31e000000
	{SPU_INSTR_RI16, instr_br}, // 320000000
	{SPU_INSTR_RI16, instr_br}, // 322000000
	{SPU_INSTR_RI16, instr_br}, // 324000000
	{SPU_INSTR_RI16, instr_br}, // 326000000
	{SPU_INSTR_RI16, instr_fsmbi}, // 328000000
	{SPU_INSTR_RI16, instr_fsmbi}, // 32a000000
	{SPU_INSTR_RI16, instr_fsmbi}, // 32c000000
	{SPU_INSTR_RI16, instr_fsmbi}, // 32e000000
	{SPU_INSTR_RI16, instr_brsl}, // 330000000
	{SPU_INSTR_RI16, instr_brsl}, // 332000000
	{SPU_INSTR_RI16, instr_brsl}, // 334000000
	{SPU_INSTR_RI16, instr_brsl}, // 336000000
	{SPU_INSTR_RI16, instr_lqr}, // 338000000
	{SPU_INSTR_RI16, instr_lqr}, // 33a000000
	{SPU_INSTR_RI16, instr_lqr}, // 33c000000
	{SPU_INSTR_RI16, instr_lqr}, // 33e000000
	{SPU_INSTR_RI10, instr_lqd}, // 340000000
	{SPU_INSTR_RI10, instr_lqd}, // 342000000
	{SPU_INSTR_RI10, instr_lqd}, // 344000000
	{SPU_INSTR_RI10, instr_lqd}, // 346000000
	{SPU_INSTR_RI10, instr_lqd}, // 348000000
	{SPU_INSTR_RI10, instr_lqd}, // 34a000000
	{SPU_INSTR_RI10, instr_lqd}, // 34c000000
	{SPU_INSTR_RI10, instr_lqd}, // 34e000000
	{SPU_INSTR_RR, instr_bi}, // 350000000
	{SPU_INSTR_RR, instr_bisl}, // 352000000
	{SPU_INSTR_NONE, NULL}, // 354000000
	{SPU_INSTR_NONE, NULL}, // 356000000
	{SPU_INSTR_SPECIAL, instr_hbr}, // 358000000
	{SPU_INSTR_NONE, NULL}, // 35a000000
	{SPU_INSTR_NONE, NULL}, // 35c000000
	{SPU_INSTR_NONE, NULL}, // 35e000000
	{SPU_INSTR_RR, instr_gb}, // 360000000
	{SPU_INSTR_RR, instr_gbh}, // 362000000
	{SPU_INSTR_RR, instr_gbb}, // 364000000
	{SPU_INSTR_NONE, NULL}, // 366000000
	{SPU_INSTR_RR, instr_fsm}, // 368000000
	{SPU_INSTR_RR, instr_fsmh}, // 36a000000
	{SPU_INSTR_RR, instr_fsmb}, // 36c000000
	{SPU_INSTR_NONE, NULL}, // 36e000000
	{SPU_INSTR_RR, instr_frest}, // 370000000
	{SPU_INSTR_RR, instr_frsqest}, // 372000000
	{SPU_INSTR_NONE, NULL}, // 374000000
	{SPU_INSTR_NONE, NULL}, // 376000000
	{SPU_INSTR_NONE, NULL}, // 378000000
	{SPU_INSTR_NONE, NULL}, // 37a000000
	{SPU_INSTR_NONE, NULL}, // 37c000000
	{SPU_INSTR_NONE, NULL}, // 37e000000
	{SPU_INSTR_NONE, NULL}, // 380000000
	{SPU_INSTR_NONE, NULL}, // 382000000
	{SPU_INSTR_NONE, NULL}, // 384000000
	{SPU_INSTR_NONE, NULL}, // 386000000
	{SPU_INSTR_RR, instr_lqx}, // 388000000
	{SPU_INSTR_NONE, NULL}, // 38a000000
	{SPU_INSTR_NONE, NULL}, // 38c000000
	{SPU_INSTR_NONE, NULL}, // 38e000000
	{SPU_INSTR_NONE, NULL}, // 390000000
	{SPU_INSTR_NONE, NULL}, // 392000000
	{SPU_INSTR_NONE, NULL}, // 394000000
	{SPU_INSTR_NONE, NULL}, // 396000000
	{SPU_INSTR_RR, instr_rotqbybi}, // 398000000
	{SPU_INSTR_RR, instr_rotqmbybi}, // 39a000000
	{SPU_INSTR_NONE, NULL}, // 39c000000
	{SPU_INSTR_RR, instr_shlqbybi}, // 39e000000
	{SPU_INSTR_NONE, NULL}, // 3a0000000
	{SPU_INSTR_NONE, NULL}, // 3a2000000
	{SPU_INSTR_NONE, NULL}, // 3a4000000
	{SPU_INSTR_NONE, NULL}, // 3a6000000
	{SPU_INSTR_RR, instr_cbx}, // 3a8000000
	{SPU_INSTR_RR, instr_chx}, // 3aa000000
	{SPU_INSTR_RR, instr_cwx}, // 3ac000000
	{SPU_INSTR_RR, instr_cdx}, // 3ae000000
	{SPU_INSTR_RR, instr_rotqbi}, // 3b0000000
	{SPU_INSTR_RR, instr_rotqmbi}, // 3b2000000
	{SPU_INSTR_NONE, NULL}, // 3b4000000
	{SPU_INSTR_RR, instr_shlqbi}, // 3b6000000
	{SPU_INSTR_RR, instr_rotqby}, // 3b8000000
	{SPU_INSTR_RR, instr_rotqmby}, // 3ba000000
	{SPU_INSTR_NONE, NULL}, // 3bc000000
	{SPU_INSTR_RR, instr_shlqby}, // 3be000000
	{SPU_INSTR_NONE, NULL}, // 3c0000000
	{SPU_INSTR_NONE, NULL}, // 3c2000000
	{SPU_INSTR_NONE, NULL}, // 3c4000000
	{SPU_INSTR_NONE, NULL}, // 3c6000000
	{SPU_INSTR_NONE, NULL}, // 3c8000000
	{SPU_INSTR_NONE, NULL}, // 3ca000000
	{SPU_INSTR_NONE, NULL}, // 3cc000000
	{SPU_INSTR_NONE, NULL}, // 3ce000000
	{SPU_INSTR_NONE, NULL}, // 3d0000000
	{SPU_INSTR_NONE, NULL}, // 3d2000000
	{SPU_INSTR_NONE, NULL}, // 3d4000000
	{SPU_INSTR_NONE, NULL}, // 3d6000000
	{SPU_INSTR_NONE, NULL}, // 3d8000000
	{SPU_INSTR_NONE, NULL}, // 3da000000
	{SPU_INSTR_NONE, NULL}, // 3dc000000
	{SPU_INSTR_NONE, NULL}, // 3de000000
	{SPU_INSTR_RR, instr_orx}, // 3e0000000
	{SPU_INSTR_NONE, NULL}, // 3e2000000
	{SPU_INSTR_NONE, NULL}, // 3e4000000
	{SPU_INSTR_NONE, NULL}, // 3e6000000
	{SPU_INSTR_RI7, instr_cbd}, // 3e8000000
	{SPU_INSTR_RI7, instr_chd}, // 3ea000000
	{SPU_INSTR_RI7, instr_cwd}, // 3ec000000
	{SPU_INSTR_RI7, instr_cdd}, // 3ee000000
	{SPU_INSTR_RI7, instr_rotqbii}, // 3f0000000
	{SPU_INSTR_RI7, instr_rotqmbii}, // 3f2000000
	{SPU_INSTR_NONE, NULL}, // 3f4000000
	{SPU_INSTR_RI7, instr_shlqbii}, // 3f6000000
	{SPU_INSTR_RI7, instr_rotqbyi}, // 3f8000000
	{SPU_INSTR_RI7, instr_rotqmbyi}, // 3fa000000
	{SPU_INSTR_NONE, NULL}, // 3fc000000
	{SPU_INSTR_RI7, instr_shlqbyi}, // 3fe000000
	{SPU_INSTR_NONE, NULL}, // 400000000
	{SPU_INSTR_SPECIAL, instr_nop}, // 402000000
	{SPU_INSTR_NONE, NULL}, // 404000000
	{SPU_INSTR_NONE, NULL}, // 406000000
	{SPU_INSTR_RI16, instr_il}, // 408000000
	{SPU_INSTR_RI16, instr_il}, // 40a000000
	{SPU_INSTR_RI16, instr_il}, // 40c000000
	{SPU_INSTR_RI16, instr_il}, // 40e000000
	{SPU_INSTR_RI16, instr_ilhu}, // 410000000
	{SPU_INSTR_RI16, instr_ilhu}, // 412000000
	{SPU_INSTR_RI16, instr_ilhu}, // 414000000
	{SPU_INSTR_RI16, instr_ilhu}, // 416000000
	{SPU_INSTR_RI16, instr_ilh}, // 418000000
	{SPU_INSTR_RI16, instr_ilh}, // 41a000000
	{SPU_INSTR_RI16, instr_ilh}, // 41c000000
	{SPU_INSTR_RI16, instr_ilh}, // 41e000000
	{SPU_INSTR_RI18, instr_ila}, // 420000000
	{SPU_INSTR_RI18, instr_ila}, // 422000000
	{SPU_INSTR_RI18, instr_ila}, // 424000000
	{SPU_INSTR_RI18, instr_ila}, // 426000000
	{SPU_INSTR_RI18, instr_ila}, // 428000000
	{SPU_INSTR_RI18, instr_ila}, // 42a000000
	{SPU_INSTR_RI18, instr_ila}, // 42c000000
	{SPU_INSTR_RI18, instr_ila}, // 42e000000
	{SPU_INSTR_RI18, instr_ila}, // 430000000
	{SPU_INSTR_RI18, instr_ila}, // 432000000
	{SPU_INSTR_RI18, instr_ila}, // 434000000
	{SPU_INSTR_RI18, instr_ila}, // 436000000
	{SPU_INSTR_RI18, instr_ila}, // 438000000
	{SPU_INSTR_RI18, instr_ila}, // 43a000000
	{SPU_INSTR_RI18, instr_ila}, // 43c000000
	{SPU_INSTR_RI18, instr_ila}, // 43e000000
	{SPU_INSTR_RI10, instr_xori}, // 440000000
	{SPU_INSTR_RI10, instr_xori}, // 442000000
	{SPU_INSTR_RI10, instr_xori}, // 444000000
	{SPU_INSTR_RI10, instr_xori}, // 446000000
	{SPU_INSTR_RI10, instr_xori}, // 448000000
	{SPU_INSTR_RI10, instr_xori}, // 44a000000
	{SPU_INSTR_RI10, instr_xori}, // 44c000000
	{SPU_INSTR_RI10, instr_xori}, // 44e000000
	{SPU_INSTR_RI10, instr_xorhi}, // 450000000
	{SPU_INSTR_RI10, instr_xorhi}, // 452000000
	{SPU_INSTR_RI10, instr_xorhi}, // 454000000
	{SPU_INSTR_RI10, instr_xorhi}, // 456000000
	{SPU_INSTR_RI10, instr_xorhi}, // 458000000
	{SPU_INSTR_RI10, instr_xorhi}, // 45a000000
	{SPU_INSTR_RI10, instr_xorhi}, // 45c000000
	{SPU_INSTR_RI10, instr_xorhi}, // 45e000000
	{SPU_INSTR_RI10, instr_xorbi}, // 460000000
	{SPU_INSTR_RI10, instr_xorbi}, // 462000000
	{SPU_INSTR_RI10, instr_xorbi}, // 464000000
	{SPU_INSTR_RI10, instr_xorbi}, // 466000000
	{SPU_INSTR_RI10, instr_xorbi}, // 468000000
	{SPU_INSTR_RI10, instr_xorbi}, // 46a000000
	{SPU_INSTR_RI10, instr_xorbi}, // 46c000000
	{SPU_INSTR_RI10, instr_xorbi}, // 46e000000
	{SPU_INSTR_NONE, NULL}, // 470000000
	{SPU_INSTR_NONE, NULL}, // 472000000
	{SPU_INSTR_NONE, NULL}, // 474000000
	{SPU_INSTR_NONE, NULL}, // 476000000
	{SPU_INSTR_NONE, NULL}, // 478000000
	{SPU_INSTR_NONE, NULL}, // 47a000000
	{SPU_INSTR_NONE, NULL}, // 47c000000
	{SPU_INSTR_NONE, NULL}, // 47e000000
	{SPU_INSTR_RR, instr_cgt}, // 480000000
	{SPU_INSTR_RR, instr_xor}, // 482000000
	{SPU_INSTR_NONE, NULL}, // 484000000
	{SPU_INSTR_NONE, NULL}, // 486000000
	{SPU_INSTR_NONE, NULL}, // 488000000
	{SPU_INSTR_NONE, NULL}, // 48a000000
	{SPU_INSTR_NONE, NULL}, // 48c000000
	{SPU_INSTR_NONE, NULL}, // 48e000000
	{SPU_INSTR_NONE, NULL}, // 490000000
	{SPU_INSTR_RR, instr_eqv}, // 492000000
	{SPU_INSTR_NONE, NULL}, // 494000000
	{SPU_INSTR_NONE, NULL}, // 496000000
	{SPU_INSTR_NONE, NULL}, // 498000000
	{SPU_INSTR_NONE, NULL}, // 49a000000
	{SPU_INSTR_NONE, NULL}, // 49c000000
	{SPU_INSTR_NONE, NULL}, // 49e000000
	{SPU_INSTR_NONE, NULL}, // 4a0000000
	{SPU_INSTR_NONE, NULL}, // 4a2000000
	{SPU_INSTR_NONE, NULL}, // 4a4000000
	{SPU_INSTR_RR, instr_sumb}, // 4a6000000
	{SPU_INSTR_NONE, NULL}, // 4a8000000
	{SPU_INSTR_NONE, NULL}, // 4aa000000
	{SPU_INSTR_NONE, NULL}, // 4ac000000
	{SPU_INSTR_NONE, NULL}, // 4ae000000
	{SPU_INSTR_NONE, NULL}, // 4b0000000
	{SPU_INSTR_NONE, NULL}, // 4b2000000
	{SPU_INSTR_NONE, NULL}, // 4b4000000
	{SPU_INSTR_NONE, NULL}, // 4b6000000
	{SPU_INSTR_NONE, NULL}, // 4b8000000
	{SPU_INSTR_NONE, NULL}, // 4ba000000
	{SPU_INSTR_NONE, NULL}, // 4bc000000
	{SPU_INSTR_NONE, NULL}, // 4be000000
	{SPU_INSTR_RI10, instr_cgti}, // 4c0000000
	{SPU_INSTR_RI10, instr_cgti}, // 4c2000000
	{SPU_INSTR_RI10, instr_cgti}, // 4c4000000
	{SPU_INSTR_RI10, instr_cgti}, // 4c6000000
	{SPU_INSTR_RI10, instr_cgti}, // 4c8000000
	{SPU_INSTR_RI10, instr_cgti}, // 4ca000000
	{SPU_INSTR_RI10, instr_cgti}, // 4cc000000
	{SPU_INSTR_RI10, instr_cgti}, // 4ce000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4d0000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4d2000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4d4000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4d6000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4d8000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4da000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4dc000000
	{SPU_INSTR_RI10, instr_cgthi}, // 4de000000
	{SPU_INSTR_NONE, NULL}, // 4e0000000
	{SPU_INSTR_NONE, NULL}, // 4e2000000
	{SPU_INSTR_NONE, NULL}, // 4e4000000
	{SPU_INSTR_NONE, NULL}, // 4e6000000
	{SPU_INSTR_NONE, NULL}, // 4e8000000
	{SPU_INSTR_NONE, NULL}, // 4ea000000
	{SPU_INSTR_NONE, NULL}, // 4ec000000
	{SPU_INSTR_NONE, NULL}, // 4ee000000
	{SPU_INSTR_NONE, NULL}, // 4f0000000
	{SPU_INSTR_NONE, NULL}, // 4f2000000
	{SPU_INSTR_NONE, NULL}, // 4f4000000
	{SPU_INSTR_NONE, NULL}, // 4f6000000
	{SPU_INSTR_NONE, NULL}, // 4f8000000
	{SPU_INSTR_NONE, NULL}, // 4fa000000
	{SPU_INSTR_NONE, NULL}, // 4fc000000
	{SPU_INSTR_NONE, NULL}, // 4fe000000
	{SPU_INSTR_NONE, NULL}, // 500000000
	{SPU_INSTR_NONE, NULL}, // 502000000
	{SPU_INSTR_NONE, NULL}, // 504000000
	{SPU_INSTR_NONE, NULL}, // 506000000
	{SPU_INSTR_NONE, NULL}, // 508000000
	{SPU_INSTR_NONE, NULL}, // 50a000000
	{SPU_INSTR_NONE, NULL}, // 50c000000
	{SPU_INSTR_NONE, NULL}, // 50e000000
	{SPU_INSTR_NONE, NULL}, // 510000000
	{SPU_INSTR_NONE, NULL}, // 512000000
	{SPU_INSTR_NONE, NULL}, // 514000000
	{SPU_INSTR_NONE, NULL}, // 516000000
	{SPU_INSTR_NONE, NULL}, // 518000000
	{SPU_INSTR_NONE, NULL}, // 51a000000
	{SPU_INSTR_NONE, NULL}, // 51c000000
	{SPU_INSTR_NONE, NULL}, // 51e000000
	{SPU_INSTR_NONE, NULL}, // 520000000
	{SPU_INSTR_NONE, NULL}, // 522000000
	{SPU_INSTR_NONE, NULL}, // 524000000
	{SPU_INSTR_NONE, NULL}, // 526000000
	{SPU_INSTR_NONE, NULL}, // 528000000
	{SPU_INSTR_NONE, NULL}, // 52a000000
	{SPU_INSTR_NONE, NULL}, // 52c000000
	{SPU_INSTR_NONE, NULL}, // 52e000000
	{SPU_INSTR_NONE, NULL}, // 530000000
	{SPU_INSTR_NONE, NULL}, // 532000000
	{SPU_INSTR_NONE, NULL}, // 534000000
	{SPU_INSTR_NONE, NULL}, // 536000000
	{SPU_INSTR_NONE, NULL}, // 538000000
	{SPU_INSTR_NONE, NULL}, // 53a000000
	{SPU_INSTR_NONE, NULL}, // 53c000000
	{SPU_INSTR_NONE, NULL}, // 53e000000
	{SPU_INSTR_NONE, NULL}, // 540000000
	{SPU_INSTR_NONE, NULL}, // 542000000
	{SPU_INSTR_NONE, NULL}, // 544000000
	{SPU_INSTR_NONE, NULL}, // 546000000
	{SPU_INSTR_NONE, NULL}, // 548000000
	{SPU_INSTR_RR, instr_clz}, // 54a000000
	{SPU_INSTR_RR, instr_xswd}, // 54c000000
	{SPU_INSTR_NONE, NULL}, // 54e000000
	{SPU_INSTR_NONE, NULL}, // 550000000
	{SPU_INSTR_NONE, NULL}, // 552000000
	{SPU_INSTR_NONE, NULL}, // 554000000
	{SPU_INSTR_NONE, NULL}, // 556000000
	{SPU_INSTR_NONE, NULL}, // 558000000
	{SPU_INSTR_NONE, NULL}, // 55a000000
	{SPU_INSTR_RR, instr_xshw}, // 55c000000
	{SPU_INSTR_NONE, NULL}, // 55e000000
	{SPU_INSTR_NONE, NULL}, // 560000000
	{SPU_INSTR_NONE, NULL}, // 562000000
	{SPU_INSTR_NONE, NULL}, // 564000000
	{SPU_INSTR_NONE, NULL}, // 566000000
	{SPU_INSTR_RR, instr_cntb}, // 568000000
	{SPU_INSTR_NONE, NULL}, // 56a000000
	{SPU_INSTR_RR, instr_xsbh}, // 56c000000
	{SPU_INSTR_NONE, NULL}, // 56e000000
	{SPU_INSTR_NONE, NULL}, // 570000000
	{SPU_INSTR_NONE, NULL}, // 572000000
	{SPU_INSTR_NONE, NULL}, // 574000000
	{SPU_INSTR_NONE, NULL}, // 576000000
	{SPU_INSTR_NONE, NULL}, // 578000000
	{SPU_INSTR_NONE, NULL}, // 57a000000
	{SPU_INSTR_NONE, NULL}, // 57c000000
	{SPU_INSTR_NONE, NULL}, // 57e000000
	{SPU_INSTR_RR, instr_clgt}, // 580000000
	{SPU_INSTR_RR, instr_andc}, // 582000000
	{SPU_INSTR_RR, instr_fcgt}, // 584000000
	{SPU_INSTR_NONE, NULL}, // 586000000
	{SPU_INSTR_RR, instr_fa}, // 588000000
	{SPU_INSTR_RR, instr_fs}, // 58a000000
	{SPU_INSTR_RR, instr_fm}, // 58c000000
	{SPU_INSTR_NONE, NULL}, // 58e000000
	{SPU_INSTR_RR, instr_clgth}, // 590000000
	{SPU_INSTR_RR, instr_orc}, // 592000000
	{SPU_INSTR_NONE, NULL}, // 594000000
	{SPU_INSTR_NONE, NULL}, // 596000000
	{SPU_INSTR_RR, instr_dfa}, // 598000000
	{SPU_INSTR_RR, instr_dfs}, // 59a000000
	{SPU_INSTR_RR, instr_dfm}, // 59c000000
	{SPU_INSTR_NONE, NULL}, // 59e000000
	{SPU_INSTR_RR, instr_clgtb}, // 5a0000000
	{SPU_INSTR_NONE, NULL}, // 5a2000000
	{SPU_INSTR_NONE, NULL}, // 5a4000000
	{SPU_INSTR_NONE, NULL}, // 5a6000000
	{SPU_INSTR_NONE, NULL}, // 5a8000000
	{SPU_INSTR_NONE, NULL}, // 5aa000000
	{SPU_INSTR_NONE, NULL}, // 5ac000000
	{SPU_INSTR_NONE, NULL}, // 5ae000000
	{SPU_INSTR_NONE, NULL}, // 5b0000000
	{SPU_INSTR_NONE, NULL}, // 5b2000000
	{SPU_INSTR_NONE, NULL}, // 5b4000000
	{SPU_INSTR_NONE, NULL}, // 5b6000000
	{SPU_INSTR_NONE, NULL}, // 5b8000000
	{SPU_INSTR_NONE, NULL}, // 5ba000000
	{SPU_INSTR_NONE, NULL}, // 5bc000000
	{SPU_INSTR_NONE, NULL}, // 5be000000
	{SPU_INSTR_RI10, instr_clgti}, // 5c0000000
	{SPU_INSTR_RI10, instr_clgti}, // 5c2000000
	{SPU_INSTR_RI10, instr_clgti}, // 5c4000000
	{SPU_INSTR_RI10, instr_clgti}, // 5c6000000
	{SPU_INSTR_RI10, instr_clgti}, // 5c8000000
	{SPU_INSTR_RI10, instr_clgti}, // 5ca000000
	{SPU_INSTR_RI10, instr_clgti}, // 5cc000000
	{SPU_INSTR_RI10, instr_clgti}, // 5ce000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5d0000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5d2000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5d4000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5d6000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5d8000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5da000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5dc000000
	{SPU_INSTR_RI10, instr_clgthi}, // 5de000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5e0000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5e2000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5e4000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5e6000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5e8000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5ea000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5ec000000
	{SPU_INSTR_RI10, instr_clgtbi}, // 5ee000000
	{SPU_INSTR_NONE, NULL}, // 5f0000000
	{SPU_INSTR_NONE, NULL}, // 5f2000000
	{SPU_INSTR_NONE, NULL}, // 5f4000000
	{SPU_INSTR_NONE, NULL}, // 5f6000000
	{SPU_INSTR_NONE, NULL}, // 5f8000000
	{SPU_INSTR_NONE, NULL}, // 5fa000000
	{SPU_INSTR_NONE, NULL}, // 5fc000000
	{SPU_INSTR_NONE, NULL}, // 5fe000000
	{SPU_INSTR_NONE, NULL}, // 600000000
	{SPU_INSTR_NONE, NULL}, // 602000000
	{SPU_INSTR_NONE, NULL}, // 604000000
	{SPU_INSTR_NONE, NULL}, // 606000000
	{SPU_INSTR_RI16, instr_iohl}, // 608000000
	{SPU_INSTR_RI16, instr_iohl}, // 60a000000
	{SPU_INSTR_RI16, instr_iohl}, // 60c000000
	{SPU_INSTR_RI16, instr_iohl}, // 60e000000
	{SPU_INSTR_NONE, NULL}, // 610000000
	{SPU_INSTR_NONE, NULL}, // 612000000
	{SPU_INSTR_NONE, NULL}, // 614000000
	{SPU_INSTR_NONE, NULL}, // 616000000
	{SPU_INSTR_NONE, NULL}, // 618000000
	{SPU_INSTR_NONE, NULL}, // 61a000000
	{SPU_INSTR_NONE, NULL}, // 61c000000
	{SPU_INSTR_NONE, NULL}, // 61e000000
	{SPU_INSTR_NONE, NULL}, // 620000000
	{SPU_INSTR_NONE, NULL}, // 622000000
	{SPU_INSTR_NONE, NULL}, // 624000000
	{SPU_INSTR_NONE, NULL}, // 626000000
	{SPU_INSTR_NONE, NULL}, // 628000000
	{SPU_INSTR_NONE, NULL}, // 62a000000
	{SPU_INSTR_NONE, NULL}, // 62c000000
	{SPU_INSTR_NONE, NULL}, // 62e000000
	{SPU_INSTR_NONE, NULL}, // 630000000
	{SPU_INSTR_NONE, NULL}, // 632000000
	{SPU_INSTR_NONE, NULL}, // 634000000
	{SPU_INSTR_NONE, NULL}, // 636000000
	{SPU_INSTR_NONE, NULL}, // 638000000
	{SPU_INSTR_NONE, NULL}, // 63a000000
	{SPU_INSTR_NONE, NULL}, // 63c000000
	{SPU_INSTR_NONE, NULL}, // 63e000000
	{SPU_INSTR_NONE, NULL}, // 640000000
	{SPU_INSTR_NONE, NULL}, // 642000000
	{SPU_INSTR_NONE, NULL}, // 644000000
	{SPU_INSTR_NONE, NULL}, // 646000000
	{SPU_INSTR_NONE, NULL}, // 648000000
	{SPU_INSTR_NONE, NULL}, // 64a000000
	{SPU_INSTR_NONE, NULL}, // 64c000000
	{SPU_INSTR_NONE, NULL}, // 64e000000
	{SPU_INSTR_NONE, NULL}, // 650000000
	{SPU_INSTR_NONE, NULL}, // 652000000
	{SPU_INSTR_NONE, NULL}, // 654000000
	{SPU_INSTR_NONE, NULL}, // 656000000
	{SPU_INSTR_NONE, NULL}, // 658000000
	{SPU_INSTR_NONE, NULL}, // 65a000000
	{SPU_INSTR_NONE, NULL}, // 65c000000
	{SPU_INSTR_NONE, NULL}, // 65e000000
	{SPU_INSTR_NONE, NULL}, // 660000000
	{SPU_INSTR_NONE, NULL}, // 662000000
	{SPU_INSTR_NONE, NULL}, // 664000000
	{SPU_INSTR_NONE, NULL}, // 666000000
	{SPU_INSTR_NONE, NULL}, // 668000000
	{SPU_INSTR_NONE, NULL}, // 66a000000
	{SPU_INSTR_NONE, NULL}, // 66c000000
	{SPU_INSTR_NONE, NULL}, // 66e000000
	{SPU_INSTR_NONE, NULL}, // 670000000
	{SPU_INSTR_NONE, NULL}, // 672000000
	{SPU_INSTR_NONE, NULL}, // 674000000
	{SPU_INSTR_NONE, NULL}, // 676000000
	{SPU_INSTR_NONE, NULL}, // 678000000
	{SPU_INSTR_NONE, NULL}, // 67a000000
	{SPU_INSTR_NONE, NULL}, // 67c000000
	{SPU_INSTR_NONE, NULL}, // 67e000000
	{SPU_INSTR_RR, instr_addx}, // 680000000
	{SPU_INSTR_RR, instr_sfx}, // 682000000
	{SPU_INSTR_RR, instr_cgx}, // 684000000
	{SPU_INSTR_RR, instr_bgx}, // 686000000
	{SPU_INSTR_NONE, NULL}, // 688000000
	{SPU_INSTR_NONE, NULL}, // 68a000000
	{SPU_INSTR_RR, instr_mpyhha}, // 68c000000
	{SPU_INSTR_NONE, NULL}, // 68e000000
	{SPU_INSTR_NONE, NULL}, // 690000000
	{SPU_INSTR_NONE, NULL}, // 692000000
	{SPU_INSTR_NONE, NULL}, // 694000000
	{SPU_INSTR_NONE, NULL}, // 696000000
	{SPU_INSTR_NONE, NULL}, // 698000000
	{SPU_INSTR_NONE, NULL}, // 69a000000
	{SPU_INSTR_RR, instr_mpyhhau}, // 69c000000
	{SPU_INSTR_NONE, NULL}, // 69e000000
	{SPU_INSTR_NONE, NULL}, // 6a0000000
	{SPU_INSTR_NONE, NULL}, // 6a2000000
	{SPU_INSTR_NONE, NULL}, // 6a4000000
	{SPU_INSTR_NONE, NULL}, // 6a6000000
	{SPU_INSTR_NONE, NULL}, // 6a8000000
	{SPU_INSTR_NONE, NULL}, // 6aa000000
	{SPU_INSTR_NONE, NULL}, // 6ac000000
	{SPU_INSTR_NONE, NULL}, // 6ae000000
	{SPU_INSTR_NONE, NULL}, // 6b0000000
	{SPU_INSTR_NONE, NULL}, // 6b2000000
	{SPU_INSTR_NONE, NULL}, // 6b4000000
	{SPU_INSTR_NONE, NULL}, // 6b6000000
	{SPU_INSTR_RR, instr_dfma}, // 6b8000000
	{SPU_INSTR_RR, instr_dfms}, // 6ba000000
	{SPU_INSTR_RR, instr_dfnms}, // 6bc000000
	{SPU_INSTR_NONE, NULL}, // 6be000000
	{SPU_INSTR_NONE, NULL}, // 6c0000000
	{SPU_INSTR_NONE, NULL}, // 6c2000000
	{SPU_INSTR_NONE, NULL}, // 6c4000000
	{SPU_INSTR_NONE, NULL}, // 6c6000000
	{SPU_INSTR_NONE, NULL}, // 6c8000000
	{SPU_INSTR_NONE, NULL}, // 6ca000000
	{SPU_INSTR_NONE, NULL}, // 6cc000000
	{SPU_INSTR_NONE, NULL}, // 6ce000000
	{SPU_INSTR_NONE, NULL}, // 6d0000000
	{SPU_INSTR_NONE, NULL}, // 6d2000000
	{SPU_INSTR_NONE, NULL}, // 6d4000000
	{SPU_INSTR_NONE, NULL}, // 6d6000000
	{SPU_INSTR_NONE, NULL}, // 6d8000000
	{SPU_INSTR_NONE, NULL}, // 6da000000
	{SPU_INSTR_NONE, NULL}, // 6dc000000
	{SPU_INSTR_NONE, NULL}, // 6de000000
	{SPU_INSTR_NONE, NULL}, // 6e0000000
	{SPU_INSTR_NONE, NULL}, // 6e2000000
	{SPU_INSTR_NONE, NULL}, // 6e4000000
	{SPU_INSTR_NONE, NULL}, // 6e6000000
	{SPU_INSTR_NONE, NULL}, // 6e8000000
	{SPU_INSTR_NONE, NULL}, // 6ea000000
	{SPU_INSTR_NONE, NULL}, // 6ec000000
	{SPU_INSTR_NONE, NULL}, // 6ee000000
	{SPU_INSTR_NONE, NULL}, // 6f0000000
	{SPU_INSTR_NONE, NULL}, // 6f2000000
	{SPU_INSTR_NONE, NULL}, // 6f4000000
	{SPU_INSTR_NONE, NULL}, // 6f6000000
	{SPU_INSTR_NONE, NULL}, // 6f8000000
	{SPU_INSTR_NONE, NULL}, // 6fa000000
	{SPU_INSTR_NONE, NULL}, // 6fc000000
	{SPU_INSTR_NONE, NULL}, // 6fe000000
	{SPU_INSTR_NONE, NULL}, // 700000000
	{SPU_INSTR_NONE, NULL}, // 702000000
	{SPU_INSTR_NONE, NULL}, // 704000000
	{SPU_INSTR_NONE, NULL}, // 706000000
	{SPU_INSTR_NONE, NULL}, // 708000000
	{SPU_INSTR_NONE, NULL}, // 70a000000
	{SPU_INSTR_NONE, NULL}, // 70c000000
	{SPU_INSTR_NONE, NULL}, // 70e000000
	{SPU_INSTR_NONE, NULL}, // 710000000
	{SPU_INSTR_NONE, NULL}, // 712000000
	{SPU_INSTR_NONE, NULL}, // 714000000
	{SPU_INSTR_NONE, NULL}, // 716000000
	{SPU_INSTR_NONE, NULL}, // 718000000
	{SPU_INSTR_NONE, NULL}, // 71a000000
	{SPU_INSTR_NONE, NULL}, // 71c000000
	{SPU_INSTR_NONE, NULL}, // 71e000000
	{SPU_INSTR_NONE, NULL}, // 720000000
	{SPU_INSTR_NONE, NULL}, // 722000000
	{SPU_INSTR_NONE, NULL}, // 724000000
	{SPU_INSTR_NONE, NULL}, // 726000000
	{SPU_INSTR_NONE, NULL}, // 728000000
	{SPU_INSTR_NONE, NULL}, // 72a000000
	{SPU_INSTR_NONE, NULL}, // 72c000000
	{SPU_INSTR_NONE, NULL}, // 72e000000
	{SPU_INSTR_NONE, NULL}, // 730000000
	{SPU_INSTR_NONE, NULL}, // 732000000
	{SPU_INSTR_NONE, NULL}, // 734000000
	{SPU_INSTR_NONE, NULL}, // 736000000
	{SPU_INSTR_NONE, NULL}, // 738000000
	{SPU_INSTR_NONE, NULL}, // 73a000000
	{SPU_INSTR_NONE, NULL}, // 73c000000
	{SPU_INSTR_NONE, NULL}, // 73e000000
	{SPU_INSTR_RI10, instr_mpyi}, // 740000000
	{SPU_INSTR_RI10, instr_mpyi}, // 742000000
	{SPU_INSTR_RI10, instr_mpyi}, // 744000000
	{SPU_INSTR_RI10, instr_mpyi}, // 746000000
	{SPU_INSTR_RI10, instr_mpyi}, // 748000000
	{SPU_INSTR_RI10, instr_mpyi}, // 74a000000
	{SPU_INSTR_RI10, instr_mpyi}, // 74c000000
	{SPU_INSTR_RI10, instr_mpyi}, // 74e000000
	{SPU_INSTR_RI10, instr_mpyui}, // 750000000
	{SPU_INSTR_RI10, instr_mpyui}, // 752000000
	{SPU_INSTR_RI10, instr_mpyui}, // 754000000
	{SPU_INSTR_RI10, instr_mpyui}, // 756000000
	{SPU_INSTR_RI10, instr_mpyui}, // 758000000
	{SPU_INSTR_RI10, instr_mpyui}, // 75a000000
	{SPU_INSTR_RI10, instr_mpyui}, // 75c000000
	{SPU_INSTR_RI10, instr_mpyui}, // 75e000000
	{SPU_INSTR_RI8, instr_cflts}, // 760000000
	{SPU_INSTR_RI8, instr_cflts}, // 762000000
	{SPU_INSTR_RI8, instr_cfltu}, // 764000000
	{SPU_INSTR_RI8, instr_cfltu}, // 766000000
	{SPU_INSTR_RI8, instr_csflt}, // 768000000
	{SPU_INSTR_RI8, instr_csflt}, // 76a000000
	{SPU_INSTR_NONE, NULL}, // 76c000000
	{SPU_INSTR_NONE, NULL}, // 76e000000
	{SPU_INSTR_RR, instr_fesd}, // 770000000
	{SPU_INSTR_RR, instr_frds}, // 772000000
	{SPU_INSTR_NONE, NULL}, // 774000000
	{SPU_INSTR_NONE, NULL}, // 776000000
	{SPU_INSTR_NONE, NULL}, // 778000000
	{SPU_INSTR_NONE, NULL}, // 77a000000
	{SPU_INSTR_NONE, NULL}, // 77c000000
	{SPU_INSTR_NONE, NULL}, // 77e000000
	{SPU_INSTR_RR, instr_ceq}, // 780000000
	{SPU_INSTR_NONE, NULL}, // 782000000
	{SPU_INSTR_RR, instr_fceq}, // 784000000
	{SPU_INSTR_NONE, NULL}, // 786000000
	{SPU_INSTR_RR, instr_mpy}, // 788000000
	{SPU_INSTR_RR, instr_mpyh}, // 78a000000
	{SPU_INSTR_RR, instr_mpyhh}, // 78c000000
	{SPU_INSTR_RR, instr_mpys}, // 78e000000
	{SPU_INSTR_RR, instr_ceqh}, // 790000000
	{SPU_INSTR_NONE, NULL}, // 792000000
	{SPU_INSTR_NONE, NULL}, // 794000000
	{SPU_INSTR_NONE, NULL}, // 796000000
	{SPU_INSTR_RR, instr_mpyu}, // 798000000
	{SPU_INSTR_NONE, NULL}, // 79a000000
	{SPU_INSTR_RR, instr_mpyhhu}, // 79c000000
	{SPU_INSTR_NONE, NULL}, // 79e000000
	{SPU_INSTR_RR, instr_ceqb}, // 7a0000000
	{SPU_INSTR_NONE, NULL}, // 7a2000000
	{SPU_INSTR_NONE, NULL}, // 7a4000000
	{SPU_INSTR_NONE, NULL}, // 7a6000000
	{SPU_INSTR_RR, instr_fi}, // 7a8000000
	{SPU_INSTR_NONE, NULL}, // 7aa000000
	{SPU_INSTR_NONE, NULL}, // 7ac000000
	{SPU_INSTR_NONE, NULL}, // 7ae000000
	{SPU_INSTR_NONE, NULL}, // 7b0000000
	{SPU_INSTR_NONE, NULL}, // 7b2000000
	{SPU_INSTR_NONE, NULL}, // 7b4000000
	{SPU_INSTR_NONE, NULL}, // 7b6000000
	{SPU_INSTR_NONE, NULL}, // 7b8000000
	{SPU_INSTR_NONE, NULL}, // 7ba000000
	{SPU_INSTR_NONE, NULL}, // 7bc000000
	{SPU_INSTR_NONE, NULL}, // 7be000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7c0000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7c2000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7c4000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7c6000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7c8000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7ca000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7cc000000
	{SPU_INSTR_RI10, instr_ceqi}, // 7ce000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7d0000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7d2000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7d4000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7d6000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7d8000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7da000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7dc000000
	{SPU_INSTR_RI10, instr_ceqhi}, // 7de000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7e0000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7e2000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7e4000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7e6000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7e8000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7ea000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7ec000000
	{SPU_INSTR_RI10, instr_ceqbi}, // 7ee000000
	{SPU_INSTR_RI10, instr_heqi}, // 7f0000000
	{SPU_INSTR_RI10, instr_heqi}, // 7f2000000
	{SPU_INSTR_RI10, instr_heqi}, // 7f4000000
	{SPU_INSTR_RI10, instr_heqi}, // 7f6000000
	{SPU_INSTR_RI10, instr_heqi}, // 7f8000000
	{SPU_INSTR_RI10, instr_heqi}, // 7fa000000
	{SPU_INSTR_RI10, instr_heqi}, // 7fc000000
	{SPU_INSTR_RI10, instr_heqi}, // 7fe000000
	{SPU_INSTR_RRR, instr_selb}, // 800000000
	{SPU_INSTR_RRR, instr_selb}, // 802000000
	{SPU_INSTR_RRR, instr_selb}, // 804000000
	{SPU_INSTR_RRR, instr_selb}, // 806000000
	{SPU_INSTR_RRR, instr_selb}, // 808000000
	{SPU_INSTR_RRR, instr_selb}, // 80a000000
	{SPU_INSTR_RRR, instr_selb}, // 80c000000
	{SPU_INSTR_RRR, instr_selb}, // 80e000000
	{SPU_INSTR_RRR, instr_selb}, // 810000000
	{SPU_INSTR_RRR, instr_selb}, // 812000000
	{SPU_INSTR_RRR, instr_selb}, // 814000000
	{SPU_INSTR_RRR, instr_selb}, // 816000000
	{SPU_INSTR_RRR, instr_selb}, // 818000000
	{SPU_INSTR_RRR, instr_selb}, // 81a000000
	{SPU_INSTR_RRR, instr_selb}, // 81c000000
	{SPU_INSTR_RRR, instr_selb}, // 81e000000
	{SPU_INSTR_RRR, instr_selb}, // 820000000
	{SPU_INSTR_RRR, instr_selb}, // 822000000
	{SPU_INSTR_RRR, instr_selb}, // 824000000
	{SPU_INSTR_RRR, instr_selb}, // 826000000
	{SPU_INSTR_RRR, instr_selb}, // 828000000
	{SPU_INSTR_RRR, instr_selb}, // 82a000000
	{SPU_INSTR_RRR, instr_selb}, // 82c000000
	{SPU_INSTR_RRR, instr_selb}, // 82e000000
	{SPU_INSTR_RRR, instr_selb}, // 830000000
	{SPU_INSTR_RRR, instr_selb}, // 832000000
	{SPU_INSTR_RRR, instr_selb}, // 834000000
	{SPU_INSTR_RRR, instr_selb}, // 836000000
	{SPU_INSTR_RRR, instr_selb}, // 838000000
	{SPU_INSTR_RRR, instr_selb}, // 83a000000
	{SPU_INSTR_RRR, instr_selb}, // 83c000000
	{SPU_INSTR_RRR, instr_selb}, // 83e000000
	{SPU_INSTR_RRR, instr_selb}, // 840000000
	{SPU_INSTR_RRR, instr_selb}, // 842000000
	{SPU_INSTR_RRR, instr_selb}, // 844000000
	{SPU_INSTR_RRR, instr_selb}, // 846000000
	{SPU_INSTR_RRR, instr_selb}, // 848000000
	{SPU_INSTR_RRR, instr_selb}, // 84a000000
	{SPU_INSTR_RRR, instr_selb}, // 84c000000
	{SPU_INSTR_RRR, instr_selb}, // 84e000000
	{SPU_INSTR_RRR, instr_selb}, // 850000000
	{SPU_INSTR_RRR, instr_selb}, // 852000000
	{SPU_INSTR_RRR, instr_selb}, // 854000000
	{SPU_INSTR_RRR, instr_selb}, // 856000000
	{SPU_INSTR_RRR, instr_selb}, // 858000000
	{SPU_INSTR_RRR, instr_selb}, // 85a000000
	{SPU_INSTR_RRR, instr_selb}, // 85c000000
	{SPU_INSTR_RRR, instr_selb}, // 85e000000
	{SPU_INSTR_RRR, instr_selb}, // 860000000
	{SPU_INSTR_RRR, instr_selb}, // 862000000
	{SPU_INSTR_RRR, instr_selb}, // 864000000
	{SPU_INSTR_RRR, instr_selb}, // 866000000
	{SPU_INSTR_RRR, instr_selb}, // 868000000
	{SPU_INSTR_RRR, instr_selb}, // 86a000000
	{SPU_INSTR_RRR, instr_selb}, // 86c000000
	{SPU_INSTR_RRR, instr_selb}, // 86e000000
	{SPU_INSTR_RRR, instr_selb}, // 870000000
	{SPU_INSTR_RRR, instr_selb}, // 872000000
	{SPU_INSTR_RRR, instr_selb}, // 874000000
	{SPU_INSTR_RRR, instr_selb}, // 876000000
	{SPU_INSTR_RRR, instr_selb}, // 878000000
	{SPU_INSTR_RRR, instr_selb}, // 87a000000
	{SPU_INSTR_RRR, instr_selb}, // 87c000000
	{SPU_INSTR_RRR, instr_selb}, // 87e000000
	{SPU_INSTR_RRR, instr_selb}, // 880000000
	{SPU_INSTR_RRR, instr_selb}, // 882000000
	{SPU_INSTR_RRR, instr_selb}, // 884000000
	{SPU_INSTR_RRR, instr_selb}, // 886000000
	{SPU_INSTR_RRR, instr_selb}, // 888000000
	{SPU_INSTR_RRR, instr_selb}, // 88a000000
	{SPU_INSTR_RRR, instr_selb}, // 88c000000
	{SPU_INSTR_RRR, instr_selb}, // 88e000000
	{SPU_INSTR_RRR, instr_selb}, // 890000000
	{SPU_INSTR_RRR, instr_selb}, // 892000000
	{SPU_INSTR_RRR, instr_selb}, // 894000000
	{SPU_INSTR_RRR, instr_selb}, // 896000000
	{SPU_INSTR_RRR, instr_selb}, // 898000000
	{SPU_INSTR_RRR, instr_selb}, // 89a000000
	{SPU_INSTR_RRR, instr_selb}, // 89c000000
	{SPU_INSTR_RRR, instr_selb}, // 89e000000
	{SPU_INSTR_RRR, instr_selb}, // 8a0000000
	{SPU_INSTR_RRR, instr_selb}, // 8a2000000
	{SPU_INSTR_RRR, instr_selb}, // 8a4000000
	{SPU_INSTR_RRR, instr_selb}, // 8a6000000
	{SPU_INSTR_RRR, instr_selb}, // 8a8000000
	{SPU_INSTR_RRR, instr_selb}, // 8aa000000
	{SPU_INSTR_RRR, instr_selb}, // 8ac000000
	{SPU_INSTR_RRR, instr_selb}, // 8ae000000
	{SPU_INSTR_RRR, instr_selb}, // 8b0000000
	{SPU_INSTR_RRR, instr_selb}, // 8b2000000
	{SPU_INSTR_RRR, instr_selb}, // 8b4000000
	{SPU_INSTR_RRR, instr_selb}, // 8b6000000
	{SPU_INSTR_RRR, instr_selb}, // 8b8000000
	{SPU_INSTR_RRR, instr_selb}, // 8ba000000
	{SPU_INSTR_RRR, instr_selb}, // 8bc000000
	{SPU_INSTR_RRR, instr_selb}, // 8be000000
	{SPU_INSTR_RRR, instr_selb}, // 8c0000000
	{SPU_INSTR_RRR, instr_selb}, // 8c2000000
	{SPU_INSTR_RRR, instr_selb}, // 8c4000000
	{SPU_INSTR_RRR, instr_selb}, // 8c6000000
	{SPU_INSTR_RRR, instr_selb}, // 8c8000000
	{SPU_INSTR_RRR, instr_selb}, // 8ca000000
	{SPU_INSTR_RRR, instr_selb}, // 8cc000000
	{SPU_INSTR_RRR, instr_selb}, // 8ce000000
	{SPU_INSTR_RRR, instr_selb}, // 8d0000000
	{SPU_INSTR_RRR, instr_selb}, // 8d2000000
	{SPU_INSTR_RRR, instr_selb}, // 8d4000000
	{SPU_INSTR_RRR, instr_selb}, // 8d6000000
	{SPU_INSTR_RRR, instr_selb}, // 8d8000000
	{SPU_INSTR_RRR, instr_selb}, // 8da000000
	{SPU_INSTR_RRR, instr_selb}, // 8dc000000
	{SPU_INSTR_RRR, instr_selb}, // 8de000000
	{SPU_INSTR_RRR, instr_selb}, // 8e0000000
	{SPU_INSTR_RRR, instr_selb}, // 8e2000000
	{SPU_INSTR_RRR, instr_selb}, // 8e4000000
	{SPU_INSTR_RRR, instr_selb}, // 8e6000000
	{SPU_INSTR_RRR, instr_selb}, // 8e8000000
	{SPU_INSTR_RRR, instr_selb}, // 8ea000000
	{SPU_INSTR_RRR, instr_selb}, // 8ec000000
	{SPU_INSTR_RRR, instr_selb}, // 8ee000000
	{SPU_INSTR_RRR, instr_selb}, // 8f0000000
	{SPU_INSTR_RRR, instr_selb}, // 8f2000000
	{SPU_INSTR_RRR, instr_selb}, // 8f4000000
	{SPU_INSTR_RRR, instr_selb}, // 8f6000000
	{SPU_INSTR_RRR, instr_selb}, // 8f8000000
	{SPU_INSTR_RRR, instr_selb}, // 8fa000000
	{SPU_INSTR_RRR, instr_selb}, // 8fc000000
	{SPU_INSTR_RRR, instr_selb}, // 8fe000000
	{SPU_INSTR_NONE, NULL}, // 900000000
	{SPU_INSTR_NONE, NULL}, // 902000000
	{SPU_INSTR_NONE, NULL}, // 904000000
	{SPU_INSTR_NONE, NULL}, // 906000000
	{SPU_INSTR_NONE, NULL}, // 908000000
	{SPU_INSTR_NONE, NULL}, // 90a000000
	{SPU_INSTR_NONE, NULL}, // 90c000000
	{SPU_INSTR_NONE, NULL}, // 90e000000
	{SPU_INSTR_NONE, NULL}, // 910000000
	{SPU_INSTR_NONE, NULL}, // 912000000
	{SPU_INSTR_NONE, NULL}, // 914000000
	{SPU_INSTR_NONE, NULL}, // 916000000
	{SPU_INSTR_NONE, NULL}, // 918000000
	{SPU_INSTR_NONE, NULL}, // 91a000000
	{SPU_INSTR_NONE, NULL}, // 91c000000
	{SPU_INSTR_NONE, NULL}, // 91e000000
	{SPU_INSTR_NONE, NULL}, // 920000000
	{SPU_INSTR_NONE, NULL}, // 922000000
	{SPU_INSTR_NONE, NULL}, // 924000000
	{SPU_INSTR_NONE, NULL}, // 926000000
	{SPU_INSTR_NONE, NULL}, // 928000000
	{SPU_INSTR_NONE, NULL}, // 92a000000
	{SPU_INSTR_NONE, NULL}, // 92c000000
	{SPU_INSTR_NONE, NULL}, // 92e000000
	{SPU_INSTR_NONE, NULL}, // 930000000
	{SPU_INSTR_NONE, NULL}, // 932000000
	{SPU_INSTR_NONE, NULL}, // 934000000
	{SPU_INSTR_NONE, NULL}, // 936000000
	{SPU_INSTR_NONE, NULL}, // 938000000
	{SPU_INSTR_NONE, NULL}, // 93a000000
	{SPU_INSTR_NONE, NULL}, // 93c000000
	{SPU_INSTR_NONE, NULL}, // 93e000000
	{SPU_INSTR_NONE, NULL}, // 940000000
	{SPU_INSTR_NONE, NULL}, // 942000000
	{SPU_INSTR_NONE, NULL}, // 944000000
	{SPU_INSTR_NONE, NULL}, // 946000000
	{SPU_INSTR_NONE, NULL}, // 948000000
	{SPU_INSTR_NONE, NULL}, // 94a000000
	{SPU_INSTR_NONE, NULL}, // 94c000000
	{SPU_INSTR_NONE, NULL}, // 94e000000
	{SPU_INSTR_NONE, NULL}, // 950000000
	{SPU_INSTR_NONE, NULL}, // 952000000
	{SPU_INSTR_NONE, NULL}, // 954000000
	{SPU_INSTR_NONE, NULL}, // 956000000
	{SPU_INSTR_NONE, NULL}, // 958000000
	{SPU_INSTR_NONE, NULL}, // 95a000000
	{SPU_INSTR_NONE, NULL}, // 95c000000
	{SPU_INSTR_NONE, NULL}, // 95e000000
	{SPU_INSTR_NONE, NULL}, // 960000000
	{SPU_INSTR_NONE, NULL}, // 962000000
	{SPU_INSTR_NONE, NULL}, // 964000000
	{SPU_INSTR_NONE, NULL}, // 966000000
	{SPU_INSTR_NONE, NULL}, // 968000000
	{SPU_INSTR_NONE, NULL}, // 96a000000
	{SPU_INSTR_NONE, NULL}, // 96c000000
	{SPU_INSTR_NONE, NULL}, // 96e000000
	{SPU_INSTR_NONE, NULL}, // 970000000
	{SPU_INSTR_NONE, NULL}, // 972000000
	{SPU_INSTR_NONE, NULL}, // 974000000
	{SPU_INSTR_NONE, NULL}, // 976000000
	{SPU_INSTR_NONE, NULL}, // 978000000
	{SPU_INSTR_NONE, NULL}, // 97a000000
	{SPU_INSTR_NONE, NULL}, // 97c000000
	{SPU_INSTR_NONE, NULL}, // 97e000000
	{SPU_INSTR_NONE, NULL}, // 980000000
	{SPU_INSTR_NONE, NULL}, // 982000000
	{SPU_INSTR_NONE, NULL}, // 984000000
	{SPU_INSTR_NONE, NULL}, // 986000000
	{SPU_INSTR_NONE, NULL}, // 988000000
	{SPU_INSTR_NONE, NULL}, // 98a000000
	{SPU_INSTR_NONE, NULL}, // 98c000000
	{SPU_INSTR_NONE, NULL}, // 98e000000
	{SPU_INSTR_NONE, NULL}, // 990000000
	{SPU_INSTR_NONE, NULL}, // 992000000
	{SPU_INSTR_NONE, NULL}, // 994000000
	{SPU_INSTR_NONE, NULL}, // 996000000
	{SPU_INSTR_NONE, NULL}, // 998000000
	{SPU_INSTR_NONE, NULL}, // 99a000000
	{SPU_INSTR_NONE, NULL}, // 99c000000
	{SPU_INSTR_NONE, NULL}, // 99e000000
	{SPU_INSTR_NONE, NULL}, // 9a0000000
	{SPU_INSTR_NONE, NULL}, // 9a2000000
	{SPU_INSTR_NONE, NULL}, // 9a4000000
	{SPU_INSTR_NONE, NULL}, // 9a6000000
	{SPU_INSTR_NONE, NULL}, // 9a8000000
	{SPU_INSTR_NONE, NULL}, // 9aa000000
	{SPU_INSTR_NONE, NULL}, // 9ac000000
	{SPU_INSTR_NONE, NULL}, // 9ae000000
	{SPU_INSTR_NONE, NULL}, // 9b0000000
	{SPU_INSTR_NONE, NULL}, // 9b2000000
	{SPU_INSTR_NONE, NULL}, // 9b4000000
	{SPU_INSTR_NONE, NULL}, // 9b6000000
	{SPU_INSTR_NONE, NULL}, // 9b8000000
	{SPU_INSTR_NONE, NULL}, // 9ba000000
	{SPU_INSTR_NONE, NULL}, // 9bc000000
	{SPU_INSTR_NONE, NULL}, // 9be000000
	{SPU_INSTR_NONE, NULL}, // 9c0000000
	{SPU_INSTR_NONE, NULL}, // 9c2000000
	{SPU_INSTR_NONE, NULL}, // 9c4000000
	{SPU_INSTR_NONE, NULL}, // 9c6000000
	{SPU_INSTR_NONE, NULL}, // 9c8000000
	{SPU_INSTR_NONE, NULL}, // 9ca000000
	{SPU_INSTR_NONE, NULL}, // 9cc000000
	{SPU_INSTR_NONE, NULL}, // 9ce000000
	{SPU_INSTR_NONE, NULL}, // 9d0000000
	{SPU_INSTR_NONE, NULL}, // 9d2000000
	{SPU_INSTR_NONE, NULL}, // 9d4000000
	{SPU_INSTR_NONE, NULL}, // 9d6000000
	{SPU_INSTR_NONE, NULL}, // 9d8000000
	{SPU_INSTR_NONE, NULL}, // 9da000000
	{SPU_INSTR_NONE, NULL}, // 9dc000000
	{SPU_INSTR_NONE, NULL}, // 9de000000
	{SPU_INSTR_NONE, NULL}, // 9e0000000
	{SPU_INSTR_NONE, NULL}, // 9e2000000
	{SPU_INSTR_NONE, NULL}, // 9e4000000
	{SPU_INSTR_NONE, NULL}, // 9e6000000
	{SPU_INSTR_NONE, NULL}, // 9e8000000
	{SPU_INSTR_NONE, NULL}, // 9ea000000
	{SPU_INSTR_NONE, NULL}, // 9ec000000
	{SPU_INSTR_NONE, NULL}, // 9ee000000
	{SPU_INSTR_NONE, NULL}, // 9f0000000
	{SPU_INSTR_NONE, NULL}, // 9f2000000
	{SPU_INSTR_NONE, NULL}, // 9f4000000
	{SPU_INSTR_NONE, NULL}, // 9f6000000
	{SPU_INSTR_NONE, NULL}, // 9f8000000
	{SPU_INSTR_NONE, NULL}, // 9fa000000
	{SPU_INSTR_NONE, NULL}, // 9fc000000
	{SPU_INSTR_NONE, NULL}, // 9fe000000
	{SPU_INSTR_NONE, NULL}, // a00000000
	{SPU_INSTR_NONE, NULL}, // a02000000
	{SPU_INSTR_NONE, NULL}, // a04000000
	{SPU_INSTR_NONE, NULL}, // a06000000
	{SPU_INSTR_NONE, NULL}, // a08000000
	{SPU_INSTR_NONE, NULL}, // a0a000000
	{SPU_INSTR_NONE, NULL}, // a0c000000
	{SPU_INSTR_NONE, NULL}, // a0e000000
	{SPU_INSTR_NONE, NULL}, // a10000000
	{SPU_INSTR_NONE, NULL}, // a12000000
	{SPU_INSTR_NONE, NULL}, // a14000000
	{SPU_INSTR_NONE, NULL}, // a16000000
	{SPU_INSTR_NONE, NULL}, // a18000000
	{SPU_INSTR_NONE, NULL}, // a1a000000
	{SPU_INSTR_NONE, NULL}, // a1c000000
	{SPU_INSTR_NONE, NULL}, // a1e000000
	{SPU_INSTR_NONE, NULL}, // a20000000
	{SPU_INSTR_NONE, NULL}, // a22000000
	{SPU_INSTR_NONE, NULL}, // a24000000
	{SPU_INSTR_NONE, NULL}, // a26000000
	{SPU_INSTR_NONE, NULL}, // a28000000
	{SPU_INSTR_NONE, NULL}, // a2a000000
	{SPU_INSTR_NONE, NULL}, // a2c000000
	{SPU_INSTR_NONE, NULL}, // a2e000000
	{SPU_INSTR_NONE, NULL}, // a30000000
	{SPU_INSTR_NONE, NULL}, // a32000000
	{SPU_INSTR_NONE, NULL}, // a34000000
	{SPU_INSTR_NONE, NULL}, // a36000000
	{SPU_INSTR_NONE, NULL}, // a38000000
	{SPU_INSTR_NONE, NULL}, // a3a000000
	{SPU_INSTR_NONE, NULL}, // a3c000000
	{SPU_INSTR_NONE, NULL}, // a3e000000
	{SPU_INSTR_NONE, NULL}, // a40000000
	{SPU_INSTR_NONE, NULL}, // a42000000
	{SPU_INSTR_NONE, NULL}, // a44000000
	{SPU_INSTR_NONE, NULL}, // a46000000
	{SPU_INSTR_NONE, NULL}, // a48000000
	{SPU_INSTR_NONE, NULL}, // a4a000000
	{SPU_INSTR_NONE, NULL}, // a4c000000
	{SPU_INSTR_NONE, NULL}, // a4e000000
	{SPU_INSTR_NONE, NULL}, // a50000000
	{SPU_INSTR_NONE, NULL}, // a52000000
	{SPU_INSTR_NONE, NULL}, // a54000000
	{SPU_INSTR_NONE, NULL}, // a56000000
	{SPU_INSTR_NONE, NULL}, // a58000000
	{SPU_INSTR_NONE, NULL}, // a5a000000
	{SPU_INSTR_NONE, NULL}, // a5c000000
	{SPU_INSTR_NONE, NULL}, // a5e000000
	{SPU_INSTR_NONE, NULL}, // a60000000
	{SPU_INSTR_NONE, NULL}, // a62000000
	{SPU_INSTR_NONE, NULL}, // a64000000
	{SPU_INSTR_NONE, NULL}, // a66000000
	{SPU_INSTR_NONE, NULL}, // a68000000
	{SPU_INSTR_NONE, NULL}, // a6a000000
	{SPU_INSTR_NONE, NULL}, // a6c000000
	{SPU_INSTR_NONE, NULL}, // a6e000000
	{SPU_INSTR_NONE, NULL}, // a70000000
	{SPU_INSTR_NONE, NULL}, // a72000000
	{SPU_INSTR_NONE, NULL}, // a74000000
	{SPU_INSTR_NONE, NULL}, // a76000000
	{SPU_INSTR_NONE, NULL}, // a78000000
	{SPU_INSTR_NONE, NULL}, // a7a000000
	{SPU_INSTR_NONE, NULL}, // a7c000000
	{SPU_INSTR_NONE, NULL}, // a7e000000
	{SPU_INSTR_NONE, NULL}, // a80000000
	{SPU_INSTR_NONE, NULL}, // a82000000
	{SPU_INSTR_NONE, NULL}, // a84000000
	{SPU_INSTR_NONE, NULL}, // a86000000
	{SPU_INSTR_NONE, NULL}, // a88000000
	{SPU_INSTR_NONE, NULL}, // a8a000000
	{SPU_INSTR_NONE, NULL}, // a8c000000
	{SPU_INSTR_NONE, NULL}, // a8e000000
	{SPU_INSTR_NONE, NULL}, // a90000000
	{SPU_INSTR_NONE, NULL}, // a92000000
	{SPU_INSTR_NONE, NULL}, // a94000000
	{SPU_INSTR_NONE, NULL}, // a96000000
	{SPU_INSTR_NONE, NULL}, // a98000000
	{SPU_INSTR_NONE, NULL}, // a9a000000
	{SPU_INSTR_NONE, NULL}, // a9c000000
	{SPU_INSTR_NONE, NULL}, // a9e000000
	{SPU_INSTR_NONE, NULL}, // aa0000000
	{SPU_INSTR_NONE, NULL}, // aa2000000
	{SPU_INSTR_NONE, NULL}, // aa4000000
	{SPU_INSTR_NONE, NULL}, // aa6000000
	{SPU_INSTR_NONE, NULL}, // aa8000000
	{SPU_INSTR_NONE, NULL}, // aaa000000
	{SPU_INSTR_NONE, NULL}, // aac000000
	{SPU_INSTR_NONE, NULL}, // aae000000
	{SPU_INSTR_NONE, NULL}, // ab0000000
	{SPU_INSTR_NONE, NULL}, // ab2000000
	{SPU_INSTR_NONE, NULL}, // ab4000000
	{SPU_INSTR_NONE, NULL}, // ab6000000
	{SPU_INSTR_NONE, NULL}, // ab8000000
	{SPU_INSTR_NONE, NULL}, // aba000000
	{SPU_INSTR_NONE, NULL}, // abc000000
	{SPU_INSTR_NONE, NULL}, // abe000000
	{SPU_INSTR_NONE, NULL}, // ac0000000
	{SPU_INSTR_NONE, NULL}, // ac2000000
	{SPU_INSTR_NONE, NULL}, // ac4000000
	{SPU_INSTR_NONE, NULL}, // ac6000000
	{SPU_INSTR_NONE, NULL}, // ac8000000
	{SPU_INSTR_NONE, NULL}, // aca000000
	{SPU_INSTR_NONE, NULL}, // acc000000
	{SPU_INSTR_NONE, NULL}, // ace000000
	{SPU_INSTR_NONE, NULL}, // ad0000000
	{SPU_INSTR_NONE, NULL}, // ad2000000
	{SPU_INSTR_NONE, NULL}, // ad4000000
	{SPU_INSTR_NONE, NULL}, // ad6000000
	{SPU_INSTR_NONE, NULL}, // ad8000000
	{SPU_INSTR_NONE, NULL}, // ada000000
	{SPU_INSTR_NONE, NULL}, // adc000000
	{SPU_INSTR_NONE, NULL}, // ade000000
	{SPU_INSTR_NONE, NULL}, // ae0000000
	{SPU_INSTR_NONE, NULL}, // ae2000000
	{SPU_INSTR_NONE, NULL}, // ae4000000
	{SPU_INSTR_NONE, NULL}, // ae6000000
	{SPU_INSTR_NONE, NULL}, // ae8000000
	{SPU_INSTR_NONE, NULL}, // aea000000
	{SPU_INSTR_NONE, NULL}, // aec000000
	{SPU_INSTR_NONE, NULL}, // aee000000
	{SPU_INSTR_NONE, NULL}, // af0000000
	{SPU_INSTR_NONE, NULL}, // af2000000
	{SPU_INSTR_NONE, NULL}, // af4000000
	{SPU_INSTR_NONE, NULL}, // af6000000
	{SPU_INSTR_NONE, NULL}, // af8000000
	{SPU_INSTR_NONE, NULL}, // afa000000
	{SPU_INSTR_NONE, NULL}, // afc000000
	{SPU_INSTR_NONE, NULL}, // afe000000
	{SPU_INSTR_RRR, instr_shufb}, // b00000000
	{SPU_INSTR_RRR, instr_shufb}, // b02000000
	{SPU_INSTR_RRR, instr_shufb}, // b04000000
	{SPU_INSTR_RRR, instr_shufb}, // b06000000
	{SPU_INSTR_RRR, instr_shufb}, // b08000000
	{SPU_INSTR_RRR, instr_shufb}, // b0a000000
	{SPU_INSTR_RRR, instr_shufb}, // b0c000000
	{SPU_INSTR_RRR, instr_shufb}, // b0e000000
	{SPU_INSTR_RRR, instr_shufb}, // b10000000
	{SPU_INSTR_RRR, instr_shufb}, // b12000000
	{SPU_INSTR_RRR, instr_shufb}, // b14000000
	{SPU_INSTR_RRR, instr_shufb}, // b16000000
	{SPU_INSTR_RRR, instr_shufb}, // b18000000
	{SPU_INSTR_RRR, instr_shufb}, // b1a000000
	{SPU_INSTR_RRR, instr_shufb}, // b1c000000
	{SPU_INSTR_RRR, instr_shufb}, // b1e000000
	{SPU_INSTR_RRR, instr_shufb}, // b20000000
	{SPU_INSTR_RRR, instr_shufb}, // b22000000
	{SPU_INSTR_RRR, instr_shufb}, // b24000000
	{SPU_INSTR_RRR, instr_shufb}, // b26000000
	{SPU_INSTR_RRR, instr_shufb}, // b28000000
	{SPU_INSTR_RRR, instr_shufb}, // b2a000000
	{SPU_INSTR_RRR, instr_shufb}, // b2c000000
	{SPU_INSTR_RRR, instr_shufb}, // b2e000000
	{SPU_INSTR_RRR, instr_shufb}, // b30000000
	{SPU_INSTR_RRR, instr_shufb}, // b32000000
	{SPU_INSTR_RRR, instr_shufb}, // b34000000
	{SPU_INSTR_RRR, instr_shufb}, // b36000000
	{SPU_INSTR_RRR, instr_shufb}, // b38000000
	{SPU_INSTR_RRR, instr_shufb}, // b3a000000
	{SPU_INSTR_RRR, instr_shufb}, // b3c000000
	{SPU_INSTR_RRR, instr_shufb}, // b3e000000
	{SPU_INSTR_RRR, instr_shufb}, // b40000000
	{SPU_INSTR_RRR, instr_shufb}, // b42000000
	{SPU_INSTR_RRR, instr_shufb}, // b44000000
	{SPU_INSTR_RRR, instr_shufb}, // b46000000
	{SPU_INSTR_RRR, instr_shufb}, // b48000000
	{SPU_INSTR_RRR, instr_shufb}, // b4a000000
	{SPU_INSTR_RRR, instr_shufb}, // b4c000000
	{SPU_INSTR_RRR, instr_shufb}, // b4e000000
	{SPU_INSTR_RRR, instr_shufb}, // b50000000
	{SPU_INSTR_RRR, instr_shufb}, // b52000000
	{SPU_INSTR_RRR, instr_shufb}, // b54000000
	{SPU_INSTR_RRR, instr_shufb}, // b56000000
	{SPU_INSTR_RRR, instr_shufb}, // b58000000
	{SPU_INSTR_RRR, instr_shufb}, // b5a000000
	{SPU_INSTR_RRR, instr_shufb}, // b5c000000
	{SPU_INSTR_RRR, instr_shufb}, // b5e000000
	{SPU_INSTR_RRR, instr_shufb}, // b60000000
	{SPU_INSTR_RRR, instr_shufb}, // b62000000
	{SPU_INSTR_RRR, instr_shufb}, // b64000000
	{SPU_INSTR_RRR, instr_shufb}, // b66000000
	{SPU_INSTR_RRR, instr_shufb}, // b68000000
	{SPU_INSTR_RRR, instr_shufb}, // b6a000000
	{SPU_INSTR_RRR, instr_shufb}, // b6c000000
	{SPU_INSTR_RRR, instr_shufb}, // b6e000000
	{SPU_INSTR_RRR, instr_shufb}, // b70000000
	{SPU_INSTR_RRR, instr_shufb}, // b72000000
	{SPU_INSTR_RRR, instr_shufb}, // b74000000
	{SPU_INSTR_RRR, instr_shufb}, // b76000000
	{SPU_INSTR_RRR, instr_shufb}, // b78000000
	{SPU_INSTR_RRR, instr_shufb}, // b7a000000
	{SPU_INSTR_RRR, instr_shufb}, // b7c000000
	{SPU_INSTR_RRR, instr_shufb}, // b7e000000
	{SPU_INSTR_RRR, instr_shufb}, // b80000000
	{SPU_INSTR_RRR, instr_shufb}, // b82000000
	{SPU_INSTR_RRR, instr_shufb}, // b84000000
	{SPU_INSTR_RRR, instr_shufb}, // b86000000
	{SPU_INSTR_RRR, instr_shufb}, // b88000000
	{SPU_INSTR_RRR, instr_shufb}, // b8a000000
	{SPU_INSTR_RRR, instr_shufb}, // b8c000000
	{SPU_INSTR_RRR, instr_shufb}, // b8e000000
	{SPU_INSTR_RRR, instr_shufb}, // b90000000
	{SPU_INSTR_RRR, instr_shufb}, // b92000000
	{SPU_INSTR_RRR, instr_shufb}, // b94000000
	{SPU_INSTR_RRR, instr_shufb}, // b96000000
	{SPU_INSTR_RRR, instr_shufb}, // b98000000
	{SPU_INSTR_RRR, instr_shufb}, // b9a000000
	{SPU_INSTR_RRR, instr_shufb}, // b9c000000
	{SPU_INSTR_RRR, instr_shufb}, // b9e000000
	{SPU_INSTR_RRR, instr_shufb}, // ba0000000
	{SPU_INSTR_RRR, instr_shufb}, // ba2000000
	{SPU_INSTR_RRR, instr_shufb}, // ba4000000
	{SPU_INSTR_RRR, instr_shufb}, // ba6000000
	{SPU_INSTR_RRR, instr_shufb}, // ba8000000
	{SPU_INSTR_RRR, instr_shufb}, // baa000000
	{SPU_INSTR_RRR, instr_shufb}, // bac000000
	{SPU_INSTR_RRR, instr_shufb}, // bae000000
	{SPU_INSTR_RRR, instr_shufb}, // bb0000000
	{SPU_INSTR_RRR, instr_shufb}, // bb2000000
	{SPU_INSTR_RRR, instr_shufb}, // bb4000000
	{SPU_INSTR_RRR, instr_shufb}, // bb6000000
	{SPU_INSTR_RRR, instr_shufb}, // bb8000000
	{SPU_INSTR_RRR, instr_shufb}, // bba000000
	{SPU_INSTR_RRR, instr_shufb}, // bbc000000
	{SPU_INSTR_RRR, instr_shufb}, // bbe000000
	{SPU_INSTR_RRR, instr_shufb}, // bc0000000
	{SPU_INSTR_RRR, instr_shufb}, // bc2000000
	{SPU_INSTR_RRR, instr_shufb}, // bc4000000
	{SPU_INSTR_RRR, instr_shufb}, // bc6000000
	{SPU_INSTR_RRR, instr_shufb}, // bc8000000
	{SPU_INSTR_RRR, instr_shufb}, // bca000000
	{SPU_INSTR_RRR, instr_shufb}, // bcc000000
	{SPU_INSTR_RRR, instr_shufb}, // bce000000
	{SPU_INSTR_RRR, instr_shufb}, // bd0000000
	{SPU_INSTR_RRR, instr_shufb}, // bd2000000
	{SPU_INSTR_RRR, instr_shufb}, // bd4000000
	{SPU_INSTR_RRR, instr_shufb}, // bd6000000
	{SPU_INSTR_RRR, instr_shufb}, // bd8000000
	{SPU_INSTR_RRR, instr_shufb}, // bda000000
	{SPU_INSTR_RRR, instr_shufb}, // bdc000000
	{SPU_INSTR_RRR, instr_shufb}, // bde000000
	{SPU_INSTR_RRR, instr_shufb}, // be0000000
	{SPU_INSTR_RRR, instr_shufb}, // be2000000
	{SPU_INSTR_RRR, instr_shufb}, // be4000000
	{SPU_INSTR_RRR, instr_shufb}, // be6000000
	{SPU_INSTR_RRR, instr_shufb}, // be8000000
	{SPU_INSTR_RRR, instr_shufb}, // bea000000
	{SPU_INSTR_RRR, instr_shufb}, // bec000000
	{SPU_INSTR_RRR, instr_shufb}, // bee000000
	{SPU_INSTR_RRR, instr_shufb}, // bf0000000
	{SPU_INSTR_RRR, instr_shufb}, // bf2000000
	{SPU_INSTR_RRR, instr_shufb}, // bf4000000
	{SPU_INSTR_RRR, instr_shufb}, // bf6000000
	{SPU_INSTR_RRR, instr_shufb}, // bf8000000
	{SPU_INSTR_RRR, instr_shufb}, // bfa000000
	{SPU_INSTR_RRR, instr_shufb}, // bfc000000
	{SPU_INSTR_RRR, instr_shufb}, // bfe000000
	{SPU_INSTR_RRR, instr_mpya}, // c00000000
	{SPU_INSTR_RRR, instr_mpya}, // c02000000
	{SPU_INSTR_RRR, instr_mpya}, // c04000000
	{SPU_INSTR_RRR, instr_mpya}, // c06000000
	{SPU_INSTR_RRR, instr_mpya}, // c08000000
	{SPU_INSTR_RRR, instr_mpya}, // c0a000000
	{SPU_INSTR_RRR, instr_mpya}, // c0c000000
	{SPU_INSTR_RRR, instr_mpya}, // c0e000000
	{SPU_INSTR_RRR, instr_mpya}, // c10000000
	{SPU_INSTR_RRR, instr_mpya}, // c12000000
	{SPU_INSTR_RRR, instr_mpya}, // c14000000
	{SPU_INSTR_RRR, instr_mpya}, // c16000000
	{SPU_INSTR_RRR, instr_mpya}, // c18000000
	{SPU_INSTR_RRR, instr_mpya}, // c1a000000
	{SPU_INSTR_RRR, instr_mpya}, // c1c000000
	{SPU_INSTR_RRR, instr_mpya}, // c1e000000
	{SPU_INSTR_RRR, instr_mpya}, // c20000000
	{SPU_INSTR_RRR, instr_mpya}, // c22000000
	{SPU_INSTR_RRR, instr_mpya}, // c24000000
	{SPU_INSTR_RRR, instr_mpya}, // c26000000
	{SPU_INSTR_RRR, instr_mpya}, // c28000000
	{SPU_INSTR_RRR, instr_mpya}, // c2a000000
	{SPU_INSTR_RRR, instr_mpya}, // c2c000000
	{SPU_INSTR_RRR, instr_mpya}, // c2e000000
	{SPU_INSTR_RRR, instr_mpya}, // c30000000
	{SPU_INSTR_RRR, instr_mpya}, // c32000000
	{SPU_INSTR_RRR, instr_mpya}, // c34000000
	{SPU_INSTR_RRR, instr_mpya}, // c36000000
	{SPU_INSTR_RRR, instr_mpya}, // c38000000
	{SPU_INSTR_RRR, instr_mpya}, // c3a000000
	{SPU_INSTR_RRR, instr_mpya}, // c3c000000
	{SPU_INSTR_RRR, instr_mpya}, // c3e000000
	{SPU_INSTR_RRR, instr_mpya}, // c40000000
	{SPU_INSTR_RRR, instr_mpya}, // c42000000
	{SPU_INSTR_RRR, instr_mpya}, // c44000000
	{SPU_INSTR_RRR, instr_mpya}, // c46000000
	{SPU_INSTR_RRR, instr_mpya}, // c48000000
	{SPU_INSTR_RRR, instr_mpya}, // c4a000000
	{SPU_INSTR_RRR, instr_mpya}, // c4c000000
	{SPU_INSTR_RRR, instr_mpya}, // c4e000000
	{SPU_INSTR_RRR, instr_mpya}, // c50000000
	{SPU_INSTR_RRR, instr_mpya}, // c52000000
	{SPU_INSTR_RRR, instr_mpya}, // c54000000
	{SPU_INSTR_RRR, instr_mpya}, // c56000000
	{SPU_INSTR_RRR, instr_mpya}, // c58000000
	{SPU_INSTR_RRR, instr_mpya}, // c5a000000
	{SPU_INSTR_RRR, instr_mpya}, // c5c000000
	{SPU_INSTR_RRR, instr_mpya}, // c5e000000
	{SPU_INSTR_RRR, instr_mpya}, // c60000000
	{SPU_INSTR_RRR, instr_mpya}, // c62000000
	{SPU_INSTR_RRR, instr_mpya}, // c64000000
	{SPU_INSTR_RRR, instr_mpya}, // c66000000
	{SPU_INSTR_RRR, instr_mpya}, // c68000000
	{SPU_INSTR_RRR, instr_mpya}, // c6a000000
	{SPU_INSTR_RRR, instr_mpya}, // c6c000000
	{SPU_INSTR_RRR, instr_mpya}, // c6e000000
	{SPU_INSTR_RRR, instr_mpya}, // c70000000
	{SPU_INSTR_RRR, instr_mpya}, // c72000000
	{SPU_INSTR_RRR, instr_mpya}, // c74000000
	{SPU_INSTR_RRR, instr_mpya}, // c76000000
	{SPU_INSTR_RRR, instr_mpya}, // c78000000
	{SPU_INSTR_RRR, instr_mpya}, // c7a000000
	{SPU_INSTR_RRR, instr_mpya}, // c7c000000
	{SPU_INSTR_RRR, instr_mpya}, // c7e000000
	{SPU_INSTR_RRR, instr_mpya}, // c80000000
	{SPU_INSTR_RRR, instr_mpya}, // c82000000
	{SPU_INSTR_RRR, instr_mpya}, // c84000000
	{SPU_INSTR_RRR, instr_mpya}, // c86000000
	{SPU_INSTR_RRR, instr_mpya}, // c88000000
	{SPU_INSTR_RRR, instr_mpya}, // c8a000000
	{SPU_INSTR_RRR, instr_mpya}, // c8c000000
	{SPU_INSTR_RRR, instr_mpya}, // c8e000000
	{SPU_INSTR_RRR, instr_mpya}, // c90000000
	{SPU_INSTR_RRR, instr_mpya}, // c92000000
	{SPU_INSTR_RRR, instr_mpya}, // c94000000
	{SPU_INSTR_RRR, instr_mpya}, // c96000000
	{SPU_INSTR_RRR, instr_mpya}, // c98000000
	{SPU_INSTR_RRR, instr_mpya}, // c9a000000
	{SPU_INSTR_RRR, instr_mpya}, // c9c000000
	{SPU_INSTR_RRR, instr_mpya}, // c9e000000
	{SPU_INSTR_RRR, instr_mpya}, // ca0000000
	{SPU_INSTR_RRR, instr_mpya}, // ca2000000
	{SPU_INSTR_RRR, instr_mpya}, // ca4000000
	{SPU_INSTR_RRR, instr_mpya}, // ca6000000
	{SPU_INSTR_RRR, instr_mpya}, // ca8000000
	{SPU_INSTR_RRR, instr_mpya}, // caa000000
	{SPU_INSTR_RRR, instr_mpya}, // cac000000
	{SPU_INSTR_RRR, instr_mpya}, // cae000000
	{SPU_INSTR_RRR, instr_mpya}, // cb0000000
	{SPU_INSTR_RRR, instr_mpya}, // cb2000000
	{SPU_INSTR_RRR, instr_mpya}, // cb4000000
	{SPU_INSTR_RRR, instr_mpya}, // cb6000000
	{SPU_INSTR_RRR, instr_mpya}, // cb8000000
	{SPU_INSTR_RRR, instr_mpya}, // cba000000
	{SPU_INSTR_RRR, instr_mpya}, // cbc000000
	{SPU_INSTR_RRR, instr_mpya}, // cbe000000
	{SPU_INSTR_RRR, instr_mpya}, // cc0000000
	{SPU_INSTR_RRR, instr_mpya}, // cc2000000
	{SPU_INSTR_RRR, instr_mpya}, // cc4000000
	{SPU_INSTR_RRR, instr_mpya}, // cc6000000
	{SPU_INSTR_RRR, instr_mpya}, // cc8000000
	{SPU_INSTR_RRR, instr_mpya}, // cca000000
	{SPU_INSTR_RRR, instr_mpya}, // ccc000000
	{SPU_INSTR_RRR, instr_mpya}, // cce000000
	{SPU_INSTR_RRR, instr_mpya}, // cd0000000
	{SPU_INSTR_RRR, instr_mpya}, // cd2000000
	{SPU_INSTR_RRR, instr_mpya}, // cd4000000
	{SPU_INSTR_RRR, instr_mpya}, // cd6000000
	{SPU_INSTR_RRR, instr_mpya}, // cd8000000
	{SPU_INSTR_RRR, instr_mpya}, // cda000000
	{SPU_INSTR_RRR, instr_mpya}, // cdc000000
	{SPU_INSTR_RRR, instr_mpya}, // cde000000
	{SPU_INSTR_RRR, instr_mpya}, // ce0000000
	{SPU_INSTR_RRR, instr_mpya}, // ce2000000
	{SPU_INSTR_RRR, instr_mpya}, // ce4000000
	{SPU_INSTR_RRR, instr_mpya}, // ce6000000
	{SPU_INSTR_RRR, instr_mpya}, // ce8000000
	{SPU_INSTR_RRR, instr_mpya}, // cea000000
	{SPU_INSTR_RRR, instr_mpya}, // cec000000
	{SPU_INSTR_RRR, instr_mpya}, // cee000000
	{SPU_INSTR_RRR, instr_mpya}, // cf0000000
	{SPU_INSTR_RRR, instr_mpya}, // cf2000000
	{SPU_INSTR_RRR, instr_mpya}, // cf4000000
	{SPU_INSTR_RRR, instr_mpya}, // cf6000000
	{SPU_INSTR_RRR, instr_mpya}, // cf8000000
	{SPU_INSTR_RRR, instr_mpya}, // cfa000000
	{SPU_INSTR_RRR, instr_mpya}, // cfc000000
	{SPU_INSTR_RRR, instr_mpya}, // cfe000000
	{SPU_INSTR_RRR, instr_fnms}, // d00000000
	{SPU_INSTR_RRR, instr_fnms}, // d02000000
	{SPU_INSTR_RRR, instr_fnms}, // d04000000
	{SPU_INSTR_RRR, instr_fnms}, // d06000000
	{SPU_INSTR_RRR, instr_fnms}, // d08000000
	{SPU_INSTR_RRR, instr_fnms}, // d0a000000
	{SPU_INSTR_RRR, instr_fnms}, // d0c000000
	{SPU_INSTR_RRR, instr_fnms}, // d0e000000
	{SPU_INSTR_RRR, instr_fnms}, // d10000000
	{SPU_INSTR_RRR, instr_fnms}, // d12000000
	{SPU_INSTR_RRR, instr_fnms}, // d14000000
	{SPU_INSTR_RRR, instr_fnms}, // d16000000
	{SPU_INSTR_RRR, instr_fnms}, // d18000000
	{SPU_INSTR_RRR, instr_fnms}, // d1a000000
	{SPU_INSTR_RRR, instr_fnms}, // d1c000000
	{SPU_INSTR_RRR, instr_fnms}, // d1e000000
	{SPU_INSTR_RRR, instr_fnms}, // d20000000
	{SPU_INSTR_RRR, instr_fnms}, // d22000000
	{SPU_INSTR_RRR, instr_fnms}, // d24000000
	{SPU_INSTR_RRR, instr_fnms}, // d26000000
	{SPU_INSTR_RRR, instr_fnms}, // d28000000
	{SPU_INSTR_RRR, instr_fnms}, // d2a000000
	{SPU_INSTR_RRR, instr_fnms}, // d2c000000
	{SPU_INSTR_RRR, instr_fnms}, // d2e000000
	{SPU_INSTR_RRR, instr_fnms}, // d30000000
	{SPU_INSTR_RRR, instr_fnms}, // d32000000
	{SPU_INSTR_RRR, instr_fnms}, // d34000000
	{SPU_INSTR_RRR, instr_fnms}, // d36000000
	{SPU_INSTR_RRR, instr_fnms}, // d38000000
	{SPU_INSTR_RRR, instr_fnms}, // d3a000000
	{SPU_INSTR_RRR, instr_fnms}, // d3c000000
	{SPU_INSTR_RRR, instr_fnms}, // d3e000000
	{SPU_INSTR_RRR, instr_fnms}, // d40000000
	{SPU_INSTR_RRR, instr_fnms}, // d42000000
	{SPU_INSTR_RRR, instr_fnms}, // d44000000
	{SPU_INSTR_RRR, instr_fnms}, // d46000000
	{SPU_INSTR_RRR, instr_fnms}, // d48000000
	{SPU_INSTR_RRR, instr_fnms}, // d4a000000
	{SPU_INSTR_RRR, instr_fnms}, // d4c000000
	{SPU_INSTR_RRR, instr_fnms}, // d4e000000
	{SPU_INSTR_RRR, instr_fnms}, // d50000000
	{SPU_INSTR_RRR, instr_fnms}, // d52000000
	{SPU_INSTR_RRR, instr_fnms}, // d54000000
	{SPU_INSTR_RRR, instr_fnms}, // d56000000
	{SPU_INSTR_RRR, instr_fnms}, // d58000000
	{SPU_INSTR_RRR, instr_fnms}, // d5a000000
	{SPU_INSTR_RRR, instr_fnms}, // d5c000000
	{SPU_INSTR_RRR, instr_fnms}, // d5e000000
	{SPU_INSTR_RRR, instr_fnms}, // d60000000
	{SPU_INSTR_RRR, instr_fnms}, // d62000000
	{SPU_INSTR_RRR, instr_fnms}, // d64000000
	{SPU_INSTR_RRR, instr_fnms}, // d66000000
	{SPU_INSTR_RRR, instr_fnms}, // d68000000
	{SPU_INSTR_RRR, instr_fnms}, // d6a000000
	{SPU_INSTR_RRR, instr_fnms}, // d6c000000
	{SPU_INSTR_RRR, instr_fnms}, // d6e000000
	{SPU_INSTR_RRR, instr_fnms}, // d70000000
	{SPU_INSTR_RRR, instr_fnms}, // d72000000
	{SPU_INSTR_RRR, instr_fnms}, // d74000000
	{SPU_INSTR_RRR, instr_fnms}, // d76000000
	{SPU_INSTR_RRR, instr_fnms}, // d78000000
	{SPU_INSTR_RRR, instr_fnms}, // d7a000000
	{SPU_INSTR_RRR, instr_fnms}, // d7c000000
	{SPU_INSTR_RRR, instr_fnms}, // d7e000000
	{SPU_INSTR_RRR, instr_fnms}, // d80000000
	{SPU_INSTR_RRR, instr_fnms}, // d82000000
	{SPU_INSTR_RRR, instr_fnms}, // d84000000
	{SPU_INSTR_RRR, instr_fnms}, // d86000000
	{SPU_INSTR_RRR, instr_fnms}, // d88000000
	{SPU_INSTR_RRR, instr_fnms}, // d8a000000
	{SPU_INSTR_RRR, instr_fnms}, // d8c000000
	{SPU_INSTR_RRR, instr_fnms}, // d8e000000
	{SPU_INSTR_RRR, instr_fnms}, // d90000000
	{SPU_INSTR_RRR, instr_fnms}, // d92000000
	{SPU_INSTR_RRR, instr_fnms}, // d94000000
	{SPU_INSTR_RRR, instr_fnms}, // d96000000
	{SPU_INSTR_RRR, instr_fnms}, // d98000000
	{SPU_INSTR_RRR, instr_fnms}, // d9a000000
	{SPU_INSTR_RRR, instr_fnms}, // d9c000000
	{SPU_INSTR_RRR, instr_fnms}, // d9e000000
	{SPU_INSTR_RRR, instr_fnms}, // da0000000
	{SPU_INSTR_RRR, instr_fnms}, // da2000000
	{SPU_INSTR_RRR, instr_fnms}, // da4000000
	{SPU_INSTR_RRR, instr_fnms}, // da6000000
	{SPU_INSTR_RRR, instr_fnms}, // da8000000
	{SPU_INSTR_RRR, instr_fnms}, // daa000000
	{SPU_INSTR_RRR, instr_fnms}, // dac000000
	{SPU_INSTR_RRR, instr_fnms}, // dae000000
	{SPU_INSTR_RRR, instr_fnms}, // db0000000
	{SPU_INSTR_RRR, instr_fnms}, // db2000000
	{SPU_INSTR_RRR, instr_fnms}, // db4000000
	{SPU_INSTR_RRR, instr_fnms}, // db6000000
	{SPU_INSTR_RRR, instr_fnms}, // db8000000
	{SPU_INSTR_RRR, instr_fnms}, // dba000000
	{SPU_INSTR_RRR, instr_fnms}, // dbc000000
	{SPU_INSTR_RRR, instr_fnms}, // dbe000000
	{SPU_INSTR_RRR, instr_fnms}, // dc0000000
	{SPU_INSTR_RRR, instr_fnms}, // dc2000000
	{SPU_INSTR_RRR, instr_fnms}, // dc4000000
	{SPU_INSTR_RRR, instr_fnms}, // dc6000000
	{SPU_INSTR_RRR, instr_fnms}, // dc8000000
	{SPU_INSTR_RRR, instr_fnms}, // dca000000
	{SPU_INSTR_RRR, instr_fnms}, // dcc000000
	{SPU_INSTR_RRR, instr_fnms}, // dce000000
	{SPU_INSTR_RRR, instr_fnms}, // dd0000000
	{SPU_INSTR_RRR, instr_fnms}, // dd2000000
	{SPU_INSTR_RRR, instr_fnms}, // dd4000000
	{SPU_INSTR_RRR, instr_fnms}, // dd6000000
	{SPU_INSTR_RRR, instr_fnms}, // dd8000000
	{SPU_INSTR_RRR, instr_fnms}, // dda000000
	{SPU_INSTR_RRR, instr_fnms}, // ddc000000
	{SPU_INSTR_RRR, instr_fnms}, // dde000000
	{SPU_INSTR_RRR, instr_fnms}, // de0000000
	{SPU_INSTR_RRR, instr_fnms}, // de2000000
	{SPU_INSTR_RRR, instr_fnms}, // de4000000
	{SPU_INSTR_RRR, instr_fnms}, // de6000000
	{SPU_INSTR_RRR, instr_fnms}, // de8000000
	{SPU_INSTR_RRR, instr_fnms}, // dea000000
	{SPU_INSTR_RRR, instr_fnms}, // dec000000
	{SPU_INSTR_RRR, instr_fnms}, // dee000000
	{SPU_INSTR_RRR, instr_fnms}, // df0000000
	{SPU_INSTR_RRR, instr_fnms}, // df2000000
	{SPU_INSTR_RRR, instr_fnms}, // df4000000
	{SPU_INSTR_RRR, instr_fnms}, // df6000000
	{SPU_INSTR_RRR, instr_fnms}, // df8000000
	{SPU_INSTR_RRR, instr_fnms}, // dfa000000
	{SPU_INSTR_RRR, instr_fnms}, // dfc000000
	{SPU_INSTR_RRR, instr_fnms}, // dfe000000
	{SPU_INSTR_RRR, instr_fma}, // e00000000
	{SPU_INSTR_RRR, instr_fma}, // e02000000
	{SPU_INSTR_RRR, instr_fma}, // e04000000
	{SPU_INSTR_RRR, instr_fma}, // e06000000
	{SPU_INSTR_RRR, instr_fma}, // e08000000
	{SPU_INSTR_RRR, instr_fma}, // e0a000000
	{SPU_INSTR_RRR, instr_fma}, // e0c000000
	{SPU_INSTR_RRR, instr_fma}, // e0e000000
	{SPU_INSTR_RRR, instr_fma}, // e10000000
	{SPU_INSTR_RRR, instr_fma}, // e12000000
	{SPU_INSTR_RRR, instr_fma}, // e14000000
	{SPU_INSTR_RRR, instr_fma}, // e16000000
	{SPU_INSTR_RRR, instr_fma}, // e18000000
	{SPU_INSTR_RRR, instr_fma}, // e1a000000
	{SPU_INSTR_RRR, instr_fma}, // e1c000000
	{SPU_INSTR_RRR, instr_fma}, // e1e000000
	{SPU_INSTR_RRR, instr_fma}, // e20000000
	{SPU_INSTR_RRR, instr_fma}, // e22000000
	{SPU_INSTR_RRR, instr_fma}, // e24000000
	{SPU_INSTR_RRR, instr_fma}, // e26000000
	{SPU_INSTR_RRR, instr_fma}, // e28000000
	{SPU_INSTR_RRR, instr_fma}, // e2a000000
	{SPU_INSTR_RRR, instr_fma}, // e2c000000
	{SPU_INSTR_RRR, instr_fma}, // e2e000000
	{SPU_INSTR_RRR, instr_fma}, // e30000000
	{SPU_INSTR_RRR, instr_fma}, // e32000000
	{SPU_INSTR_RRR, instr_fma}, // e34000000
	{SPU_INSTR_RRR, instr_fma}, // e36000000
	{SPU_INSTR_RRR, instr_fma}, // e38000000
	{SPU_INSTR_RRR, instr_fma}, // e3a000000
	{SPU_INSTR_RRR, instr_fma}, // e3c000000
	{SPU_INSTR_RRR, instr_fma}, // e3e000000
	{SPU_INSTR_RRR, instr_fma}, // e40000000
	{SPU_INSTR_RRR, instr_fma}, // e42000000
	{SPU_INSTR_RRR, instr_fma}, // e44000000
	{SPU_INSTR_RRR, instr_fma}, // e46000000
	{SPU_INSTR_RRR, instr_fma}, // e48000000
	{SPU_INSTR_RRR, instr_fma}, // e4a000000
	{SPU_INSTR_RRR, instr_fma}, // e4c000000
	{SPU_INSTR_RRR, instr_fma}, // e4e000000
	{SPU_INSTR_RRR, instr_fma}, // e50000000
	{SPU_INSTR_RRR, instr_fma}, // e52000000
	{SPU_INSTR_RRR, instr_fma}, // e54000000
	{SPU_INSTR_RRR, instr_fma}, // e56000000
	{SPU_INSTR_RRR, instr_fma}, // e58000000
	{SPU_INSTR_RRR, instr_fma}, // e5a000000
	{SPU_INSTR_RRR, instr_fma}, // e5c000000
	{SPU_INSTR_RRR, instr_fma}, // e5e000000
	{SPU_INSTR_RRR, instr_fma}, // e60000000
	{SPU_INSTR_RRR, instr_fma}, // e62000000
	{SPU_INSTR_RRR, instr_fma}, // e64000000
	{SPU_INSTR_RRR, instr_fma}, // e66000000
	{SPU_INSTR_RRR, instr_fma}, // e68000000
	{SPU_INSTR_RRR, instr_fma}, // e6a000000
	{SPU_INSTR_RRR, instr_fma}, // e6c000000
	{SPU_INSTR_RRR, instr_fma}, // e6e000000
	{SPU_INSTR_RRR, instr_fma}, // e70000000
	{SPU_INSTR_RRR, instr_fma}, // e72000000
	{SPU_INSTR_RRR, instr_fma}, // e74000000
	{SPU_INSTR_RRR, instr_fma}, // e76000000
	{SPU_INSTR_RRR, instr_fma}, // e78000000
	{SPU_INSTR_RRR, instr_fma}, // e7a000000
	{SPU_INSTR_RRR, instr_fma}, // e7c000000
	{SPU_INSTR_RRR, instr_fma}, // e7e000000
	{SPU_INSTR_RRR, instr_fma}, // e80000000
	{SPU_INSTR_RRR, instr_fma}, // e82000000
	{SPU_INSTR_RRR, instr_fma}, // e84000000
	{SPU_INSTR_RRR, instr_fma}, // e86000000
	{SPU_INSTR_RRR, instr_fma}, // e88000000
	{SPU_INSTR_RRR, instr_fma}, // e8a000000
	{SPU_INSTR_RRR, instr_fma}, // e8c000000
	{SPU_INSTR_RRR, instr_fma}, // e8e000000
	{SPU_INSTR_RRR, instr_fma}, // e90000000
	{SPU_INSTR_RRR, instr_fma}, // e92000000
	{SPU_INSTR_RRR, instr_fma}, // e94000000
	{SPU_INSTR_RRR, instr_fma}, // e96000000
	{SPU_INSTR_RRR, instr_fma}, // e98000000
	{SPU_INSTR_RRR, instr_fma}, // e9a000000
	{SPU_INSTR_RRR, instr_fma}, // e9c000000
	{SPU_INSTR_RRR, instr_fma}, // e9e000000
	{SPU_INSTR_RRR, instr_fma}, // ea0000000
	{SPU_INSTR_RRR, instr_fma}, // ea2000000
	{SPU_INSTR_RRR, instr_fma}, // ea4000000
	{SPU_INSTR_RRR, instr_fma}, // ea6000000
	{SPU_INSTR_RRR, instr_fma}, // ea8000000
	{SPU_INSTR_RRR, instr_fma}, // eaa000000
	{SPU_INSTR_RRR, instr_fma}, // eac000000
	{SPU_INSTR_RRR, instr_fma}, // eae000000
	{SPU_INSTR_RRR, instr_fma}, // eb0000000
	{SPU_INSTR_RRR, instr_fma}, // eb2000000
	{SPU_INSTR_RRR, instr_fma}, // eb4000000
	{SPU_INSTR_RRR, instr_fma}, // eb6000000
	{SPU_INSTR_RRR, instr_fma}, // eb8000000
	{SPU_INSTR_RRR, instr_fma}, // eba000000
	{SPU_INSTR_RRR, instr_fma}, // ebc000000
	{SPU_INSTR_RRR, instr_fma}, // ebe000000
	{SPU_INSTR_RRR, instr_fma}, // ec0000000
	{SPU_INSTR_RRR, instr_fma}, // ec2000000
	{SPU_INSTR_RRR, instr_fma}, // ec4000000
	{SPU_INSTR_RRR, instr_fma}, // ec6000000
	{SPU_INSTR_RRR, instr_fma}, // ec8000000
	{SPU_INSTR_RRR, instr_fma}, // eca000000
	{SPU_INSTR_RRR, instr_fma}, // ecc000000
	{SPU_INSTR_RRR, instr_fma}, // ece000000
	{SPU_INSTR_RRR, instr_fma}, // ed0000000
	{SPU_INSTR_RRR, instr_fma}, // ed2000000
	{SPU_INSTR_RRR, instr_fma}, // ed4000000
	{SPU_INSTR_RRR, instr_fma}, // ed6000000
	{SPU_INSTR_RRR, instr_fma}, // ed8000000
	{SPU_INSTR_RRR, instr_fma}, // eda000000
	{SPU_INSTR_RRR, instr_fma}, // edc000000
	{SPU_INSTR_RRR, instr_fma}, // ede000000
	{SPU_INSTR_RRR, instr_fma}, // ee0000000
	{SPU_INSTR_RRR, instr_fma}, // ee2000000
	{SPU_INSTR_RRR, instr_fma}, // ee4000000
	{SPU_INSTR_RRR, instr_fma}, // ee6000000
	{SPU_INSTR_RRR, instr_fma}, // ee8000000
	{SPU_INSTR_RRR, instr_fma}, // eea000000
	{SPU_INSTR_RRR, instr_fma}, // eec000000
	{SPU_INSTR_RRR, instr_fma}, // eee000000
	{SPU_INSTR_RRR, instr_fma}, // ef0000000
	{SPU_INSTR_RRR, instr_fma}, // ef2000000
	{SPU_INSTR_RRR, instr_fma}, // ef4000000
	{SPU_INSTR_RRR, instr_fma}, // ef6000000
	{SPU_INSTR_RRR, instr_fma}, // ef8000000
	{SPU_INSTR_RRR, instr_fma}, // efa000000
	{SPU_INSTR_RRR, instr_fma}, // efc000000
	{SPU_INSTR_RRR, instr_fma}, // efe000000
	{SPU_INSTR_RRR, instr_fms}, // f00000000
	{SPU_INSTR_RRR, instr_fms}, // f02000000
	{SPU_INSTR_RRR, instr_fms}, // f04000000
	{SPU_INSTR_RRR, instr_fms}, // f06000000
	{SPU_INSTR_RRR, instr_fms}, // f08000000
	{SPU_INSTR_RRR, instr_fms}, // f0a000000
	{SPU_INSTR_RRR, instr_fms}, // f0c000000
	{SPU_INSTR_RRR, instr_fms}, // f0e000000
	{SPU_INSTR_RRR, instr_fms}, // f10000000
	{SPU_INSTR_RRR, instr_fms}, // f12000000
	{SPU_INSTR_RRR, instr_fms}, // f14000000
	{SPU_INSTR_RRR, instr_fms}, // f16000000
	{SPU_INSTR_RRR, instr_fms}, // f18000000
	{SPU_INSTR_RRR, instr_fms}, // f1a000000
	{SPU_INSTR_RRR, instr_fms}, // f1c000000
	{SPU_INSTR_RRR, instr_fms}, // f1e000000
	{SPU_INSTR_RRR, instr_fms}, // f20000000
	{SPU_INSTR_RRR, instr_fms}, // f22000000
	{SPU_INSTR_RRR, instr_fms}, // f24000000
	{SPU_INSTR_RRR, instr_fms}, // f26000000
	{SPU_INSTR_RRR, instr_fms}, // f28000000
	{SPU_INSTR_RRR, instr_fms}, // f2a000000
	{SPU_INSTR_RRR, instr_fms}, // f2c000000
	{SPU_INSTR_RRR, instr_fms}, // f2e000000
	{SPU_INSTR_RRR, instr_fms}, // f30000000
	{SPU_INSTR_RRR, instr_fms}, // f32000000
	{SPU_INSTR_RRR, instr_fms}, // f34000000
	{SPU_INSTR_RRR, instr_fms}, // f36000000
	{SPU_INSTR_RRR, instr_fms}, // f38000000
	{SPU_INSTR_RRR, instr_fms}, // f3a000000
	{SPU_INSTR_RRR, instr_fms}, // f3c000000
	{SPU_INSTR_RRR, instr_fms}, // f3e000000
	{SPU_INSTR_RRR, instr_fms}, // f40000000
	{SPU_INSTR_RRR, instr_fms}, // f42000000
	{SPU_INSTR_RRR, instr_fms}, // f44000000
	{SPU_INSTR_RRR, instr_fms}, // f46000000
	{SPU_INSTR_RRR, instr_fms}, // f48000000
	{SPU_INSTR_RRR, instr_fms}, // f4a000000
	{SPU_INSTR_RRR, instr_fms}, // f4c000000
	{SPU_INSTR_RRR, instr_fms}, // f4e000000
	{SPU_INSTR_RRR, instr_fms}, // f50000000
	{SPU_INSTR_RRR, instr_fms}, // f52000000
	{SPU_INSTR_RRR, instr_fms}, // f54000000
	{SPU_INSTR_RRR, instr_fms}, // f56000000
	{SPU_INSTR_RRR, instr_fms}, // f58000000
	{SPU_INSTR_RRR, instr_fms}, // f5a000000
	{SPU_INSTR_RRR, instr_fms}, // f5c000000
	{SPU_INSTR_RRR, instr_fms}, // f5e000000
	{SPU_INSTR_RRR, instr_fms}, // f60000000
	{SPU_INSTR_RRR, instr_fms}, // f62000000
	{SPU_INSTR_RRR, instr_fms}, // f64000000
	{SPU_INSTR_RRR, instr_fms}, // f66000000
	{SPU_INSTR_RRR, instr_fms}, // f68000000
	{SPU_INSTR_RRR, instr_fms}, // f6a000000
	{SPU_INSTR_RRR, instr_fms}, // f6c000000
	{SPU_INSTR_RRR, instr_fms}, // f6e000000
	{SPU_INSTR_RRR, instr_fms}, // f70000000
	{SPU_INSTR_RRR, instr_fms}, // f72000000
	{SPU_INSTR_RRR, instr_fms}, // f74000000
	{SPU_INSTR_RRR, instr_fms}, // f76000000
	{SPU_INSTR_RRR, instr_fms}, // f78000000
	{SPU_INSTR_RRR, instr_fms}, // f7a000000
	{SPU_INSTR_RRR, instr_fms}, // f7c000000
	{SPU_INSTR_RRR, instr_fms}, // f7e000000
	{SPU_INSTR_RRR, instr_fms}, // f80000000
	{SPU_INSTR_RRR, instr_fms}, // f82000000
	{SPU_INSTR_RRR, instr_fms}, // f84000000
	{SPU_INSTR_RRR, instr_fms}, // f86000000
	{SPU_INSTR_RRR, instr_fms}, // f88000000
	{SPU_INSTR_RRR, instr_fms}, // f8a000000
	{SPU_INSTR_RRR, instr_fms}, // f8c000000
	{SPU_INSTR_RRR, instr_fms}, // f8e000000
	{SPU_INSTR_RRR, instr_fms}, // f90000000
	{SPU_INSTR_RRR, instr_fms}, // f92000000
	{SPU_INSTR_RRR, instr_fms}, // f94000000
	{SPU_INSTR_RRR, instr_fms}, // f96000000
	{SPU_INSTR_RRR, instr_fms}, // f98000000
	{SPU_INSTR_RRR, instr_fms}, // f9a000000
	{SPU_INSTR_RRR, instr_fms}, // f9c000000
	{SPU_INSTR_RRR, instr_fms}, // f9e000000
	{SPU_INSTR_RRR, instr_fms}, // fa0000000
	{SPU_INSTR_RRR, instr_fms}, // fa2000000
	{SPU_INSTR_RRR, instr_fms}, // fa4000000
	{SPU_INSTR_RRR, instr_fms}, // fa6000000
	{SPU_INSTR_RRR, instr_fms}, // fa8000000
	{SPU_INSTR_RRR, instr_fms}, // faa000000
	{SPU_INSTR_RRR, instr_fms}, // fac000000
	{SPU_INSTR_RRR, instr_fms}, // fae000000
	{SPU_INSTR_RRR, instr_fms}, // fb0000000
	{SPU_INSTR_RRR, instr_fms}, // fb2000000
	{SPU_INSTR_RRR, instr_fms}, // fb4000000
	{SPU_INSTR_RRR, instr_fms}, // fb6000000
	{SPU_INSTR_RRR, instr_fms}, // fb8000000
	{SPU_INSTR_RRR, instr_fms}, // fba000000
	{SPU_INSTR_RRR, instr_fms}, // fbc000000
	{SPU_INSTR_RRR, instr_fms}, // fbe000000
	{SPU_INSTR_RRR, instr_fms}, // fc0000000
	{SPU_INSTR_RRR, instr_fms}, // fc2000000
	{SPU_INSTR_RRR, instr_fms}, // fc4000000
	{SPU_INSTR_RRR, instr_fms}, // fc6000000
	{SPU_INSTR_RRR, instr_fms}, // fc8000000
	{SPU_INSTR_RRR, instr_fms}, // fca000000
	{SPU_INSTR_RRR, instr_fms}, // fcc000000
	{SPU_INSTR_RRR, instr_fms}, // fce000000
	{SPU_INSTR_RRR, instr_fms}, // fd0000000
	{SPU_INSTR_RRR, instr_fms}, // fd2000000
	{SPU_INSTR_RRR, instr_fms}, // fd4000000
	{SPU_INSTR_RRR, instr_fms}, // fd6000000
	{SPU_INSTR_RRR, instr_fms}, // fd8000000
	{SPU_INSTR_RRR, instr_fms}, // fda000000
	{SPU_INSTR_RRR, instr_fms}, // fdc000000
	{SPU_INSTR_RRR, instr_fms}, // fde000000
	{SPU_INSTR_RRR, instr_fms}, // fe0000000
	{SPU_INSTR_RRR, instr_fms}, // fe2000000
	{SPU_INSTR_RRR, instr_fms}, // fe4000000
	{SPU_INSTR_RRR, instr_fms}, // fe6000000
	{SPU_INSTR_RRR, instr_fms}, // fe8000000
	{SPU_INSTR_RRR, instr_fms}, // fea000000
	{SPU_INSTR_RRR, instr_fms}, // fec000000
	{SPU_INSTR_RRR, instr_fms}, // fee000000
	{SPU_INSTR_RRR, instr_fms}, // ff0000000
	{SPU_INSTR_RRR, instr_fms}, // ff2000000
	{SPU_INSTR_RRR, instr_fms}, // ff4000000
	{SPU_INSTR_RRR, instr_fms}, // ff6000000
	{SPU_INSTR_RRR, instr_fms}, // ff8000000
	{SPU_INSTR_RRR, instr_fms}, // ffa000000
	{SPU_INSTR_RRR, instr_fms}, // ffc000000
	{SPU_INSTR_RRR, instr_fms}, // ffe000000

};

#endif
