SYM53C810A
PCI-SCSI I/O Processor

Data Manual
Version 2.0

.  INCREASING SCSI RELIABILITY

   TolerANT®
   ACTIVE NEGATION TECHNOLOGY

T07962I
The products described in this publication are product s of Symbios Logic Inc.

SCRIPTS is a trademark and TolerANT is a registered trademark of Symbios Logic
Inc.

It is the policy of Symbios Logic to improve products as new technology,
components, software, and firmware become available. Symbios Logic, therefore,
reserves the right to change specifications without notice.

The products in this manual are not intended for use in life-support appliances,
devices, or systems. Use of these products in such applications without the written
consent of the appropriate Symbios Logic officer is prohibited

Copyright ©1995, 1996
By Symbios Logic Inc.
All Rights Reserved
Printed in U.S.A.

We use comments from our readers to improve Symbios product literature. Please
e-mail any comments regarding technical documentation to pubs@symbios.com.
                        Preface

Preface

SCSI and PCI Reference
Information

This manual assumes some prior knowledge of current and proposed SCSI and PCI standards. For back-
ground information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800)-854-7179 or (303) 792-2181 (outside U.S.)
Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia
Prentice Hall
Englewood Cliffs, NJ 07632
(201) 767-5937
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface
Symbios Logic Electronic Bulletin Board
(719) 573-3562
SCSI Electronic Bulletin Board
(719) 533-7950
Symbios Logic Internet Anonymous FTP Site
ftp.symbios.com (204.131.200.1)
Server:Bastion
Directory: /pub/symchips/scsi
Symbios Logic World-Wide Web Home Page
http://www.symbios.com
PCI Special Interest Group
P.O. Box 10470
Portland, OR 97214
(800) 433-5177; (503) 797-4201 (International); FAX (503) 234-6762

Symbios Logic PCI-SCSI Programming Guide

SYM56C810A Data Manual  i
Document History

Document History

    Page No.      Date          Remarks
                                Rev 1.0
    n/a           6/95          Version 2.0

    1-1,1-3, 1-5, 2-1--2- 7/96
    4, 2-10, 2-11, 2-13,
    3-2, 3-4, 3-6, 3-7, 3-
    9, 3-10, 4-1, 4-4, 4-
    6, 4-7, 5-1, 5-10, 5-
    12, 5-13--5-16, 5-
    21, 5-31, 5-35, 5-50,
    6-23--6-25, 7-1, 7-2,
    7-9, 7-13, 7-24

ii                                           SYM56C810A Data Manual
                                                                                                                                                                 Contents

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
     SCSI and PCI Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i

Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Chapter 1

Introduction

What is Covered in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
SYM53C810A Benefits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

      SCSI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
     PCI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
     Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
     Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
     Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
     Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2

Functional Description

SCSI Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
DMA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SCRIPTS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SDMS: The Total SCSI Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Prefetching SCRIPTS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

     Op Code Fetch Burst Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Load/Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3.3 Volt/5 Volt PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Parity Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
DMA FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

     Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
          Asynchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
          Synchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
          Asynchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
          Synchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

SYM53C810A Data Manual                                                                                                                                           iii
Contents

SCSI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
     Terminator Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
     (Re)Select During (Re)Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
     Determining the Data Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
          SCNTL3 Register, bits 6­4 (SCF2­0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
          SCNTL3 Register, bits 2­0 (CCF2­0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
          SXFER Register, bits 7­5 (TP2­0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
          Achieving Optimal SCSI Send Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
     Polling and Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
     Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
          ISTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
          SIST0 and SIST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
          DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
          SIEN0 and SIEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
          DIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
          DCNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
     Fatal vs. Non-Fatal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
     Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
     Stacked Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
     Halting in an Orderly Fashion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
     Sample Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Chapter 3

PCI Functional Description

PCI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

PCI Bus Commands and Functions Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
     Support for PCI Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
     Selection of Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
     Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
     MMOV Misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
     Memory Write and Invalidate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
          Multiple Cache Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
          Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
          PCI Target Retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
          PCI Target Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
     Memory Read Line Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
     Memory Read Multiple Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
          Burst Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
          Read Multiple with Read Line Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
     Unsupported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

iv  SYM53C810A Data Manual
                                                                                                                                                              Contents

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
     Register 00h
       Vendor ID
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
     Register 02h
       Device ID
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
     Register 04h
       Command
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
     Register 06h
       Status
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
     Register 08h
       Revision ID
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
     Register 09h
       Class Code
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
     Register 0Ch
       Cache Line Size
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
     Register 0Dh
       Latency Timer
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
     Register 0Eh
       Header Type
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 10h
       Base Address Zero (I/O)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 14h
       Base Address One (Memory)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 3Ch
       Interrupt Line
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 3Dh
       Interrupt Pin
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 3Eh
       Min_Gnt
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
     Register 3Fh
       Max_Lat
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

SYM53C810A Data Manual  v
Contents

Chapter 4

Signal Descriptions

Chapter 5

Operating Registers

     Register 00 (80)
       SCSI Control Zero (SCNTL0)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

     Register 01 (81)
       SCSI Control One (SCNTL1)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

     Register 02 (82)
       SCSI Control Two (SCNTL2)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

     Register 03 (83)
       SCSI Control Three (SCNTL3)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

     Register 04 (84)
       SCSI Chip ID (SCID)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

     Register 05 (85)
       SCSI Transfer (SXFER)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

     Register 06 (86)
       SCSI Destination ID (SDID)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

     Register 07 (87)
       General Purpose (GPREG)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

     Register 08 (88)
       SCSI First Byte Received (SFBR)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

     Register 09 (89)
       SCSI Output Control Latch (SOCL)
       Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

     Register 0A (8A)
       SCSI Selector ID (SSID)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

     Register 0B (8B)
       SCSI Bus Control Lines (SBCL)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

     Register 0C (8C)
       DMA Status (DSTAT)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

     Register 0D (8D)
       SCSI Status Zero (SSTAT0)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

     Register 0E (8E)
       SCSI Status One (SSTAT1)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

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Register 0F (8F)
 SCSI Status Two (SSTAT2)
 (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

Registers 10-13 (90-93)
 Data Structure Address (DSA)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

Register 14 (94)
 Interrupt Status (ISTAT)
 (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

Register 18 (98)
 Chip Test Zero (CTEST0)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

Register 19 (99)
 Chip Test One (CTEST1)
 Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

Register 1A (9A)
 Chip Test Two (CTEST2)
 Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

Register 1B (9B)
 Chip Test Three (CTEST3)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

Registers 1C-1F (9C-9F)
 Temporary (TEMP)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

Register 20 (A0)
 DMA FIFO (DFIFO)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

Register 21 (A1)
 Chip Test Four (CTEST4)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

Register 22 (A2)
 Chip Test Five (CTEST5)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

Register 23 (A3)
 Chip Test Six (CTEST6)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Registers 24-26 (A4-A6)
 DMA Byte Counter (DBC)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Register 27 (A7)
 DMA Command (DCMD)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

Registers 28-2B (A8-AB)
 DMA Next Address (DNAD)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

Registers 2C-2F (AC-AF)
 DMA SCRIPTS Pointer (DSP)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

Registers 30-33 (B0-B3)
 DMA SCRIPTS Pointer Save (DSPS)
 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

SYM53C810A Data Manual                                                                                                                             vii
Contents

      Registers 34-37 (B4-B7)
       Scratch Register A (SCRATCH A)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

      Register 38 (B8)
       DMA Mode (DMODE)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

      Register 39 (B9)
       DMA Interrupt Enable (DIEN)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

      Register 3A (BA)
       Scratch Byte Register (SBR)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

      Register 3B (BB)
       DMA Control (DCNTL)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

      Register 3C-3F (BC-BF)
       Adder Sum Output (ADDER)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

      Register 40 (C0)
       SCSI Interrupt Enable Zero (SIEN0)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

      Register 41 (C1)
       SCSI Interrupt Enable One (SIEN1)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

      Register 42 (C2)
       SCSI Interrupt Status Zero (SIST0)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38

      Register 43 (C3)
       SCSI Interrupt Status One (SIST1)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

      Register 44 (C4)
       SCSI Longitudinal Parity (SLPAR)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

      Register 46 (C6)
       Memory Access Control (MACNTL)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41

      Register 47 (C7)
       General Purpose Pin Control (GPCNTL)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41

      Register 48 (C8)
       SCSI Timer Zero (STIME0)
       Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42

      Register 49 (C9)
       SCSI Timer One (STIME1)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43

      Register 4A (CA)
       Response ID (RESPID)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43

      Register 4C (CC)
       SCSI Test Zero (STEST0)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44

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     Register 4D (CD)
       SCSI Test One (STEST1)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45

     Register 4E (CE)
       SCSI Test Two (STEST2)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45

     Register 4F (CF)
       SCSI Test Three (STEST3)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46

     Register 50 (D0)
       SCSI Input Data Latch (SIDL)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

     Registers 54 (D4)
       SCSI Output Data Latch (SODL)
       Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

     Registers 58 (D8)
       SCSI Bus Data Lines (SBDL)
       Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

     Registers 5C-5F (DC-DF)
       Scratch Register B (SCRATCHB)
       (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

Chapter 6

Instruction Set of the I/O Processor

SCSI SCRIPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
     Sample Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Block Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
     Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
     Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
     Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
     Read-Modify-Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
     Move to/from
       SFBR Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Transfer Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
      Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Memory Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
     Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
     Third Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
     Read/Write System Memory from a SCRIPTS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
     First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
     Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

SYM53C810A Data Manual                                                                                                                                    ix
Contents

Chapter 7

Electrical Characteristics

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
PCI Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

          Target Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
          Initiator Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
SCSI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
     Initiator Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
     Initiator Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
     Target Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
     Target Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
     Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27

Appendix A

Register Summary

Appendix B

Mechanical Drawing

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1

x  SYM53C810A Data Manual
                        List of Figures

List of Figures

Figure 1-1: SYM53C810A System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-2: SYM53C810A Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 2-1: DMA FIFO Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-2: SYM Host Interface Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-3: Active or Regulated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-4: Determining the Synchronous Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 3-1: PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-2: Command Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-3: Status Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 4-1: SYM53C810A Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2: Functional Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 5-1: SYM53C810A Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Figure 6-1: SCRIPTS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Figure 6-2: Block Move Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6-3: I/O Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-4: Read/Write Register Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6-5: Transfer Control Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-6: Memory to Memory Move Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-7: Load and Store Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Figure 7-1: Rise and Fall Time Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-2: SCSI Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-3: Hysteresis of SCSI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-4: Input Current as a Function of Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-5: Output Current as a Function of Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-6: Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Figure 7-7: Reset Input Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-8: Interrupt Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-9: PCI Configuration Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-10: PCI Configuration Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Figure 7-11: Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-12: Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

SYM53C810A Data Manual                                                                                                                xi
List of Figures

Figure 7-13: Op Code Fetch, non-burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Figure 7-14: Burst Op Code Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Figure 7-15: Back to Back Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Figure 7-16: Back to Back Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Figure 7-17: Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Figure 7-18: Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Figure 7-19: Initiator Asynchronous Send Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Figure 7-20: Initiator Asynchronous Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Figure 7-21: Target Asynchronous Send Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Figure 7-22: Target Asynchronous Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Figure 7-23: Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27

xii  SYM53C810A Data Manual
                                                                                                                                                         List of Tables

List of Tables

Table 2-1: Bits Used for Parity Control and Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Table 2-2: SCSI Parity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3: SCSI Parity Errors and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 3-1: PCI Bus Commands and Encoding Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 4-1: Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2: System Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-3: Address and Data Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-4: Interface Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-5: Arbitration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-6: Error Reporting Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-7: SCSI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-8: Additional Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Table 5-1: Operating Register Addresses and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table 5-2: Synchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-3: Asynchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1 . . . . . . . . . . . . . 5-12
Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI . . . . . . . . . . . 5-12
Table 5-6: SCSI Synchronous Offset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Table 6-1: Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Table 7-1: Absolute Maximum Stress Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Table 7-2: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/. . . . . . . . . . . 7-3
Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN . . . . . . . . . . . . . . . . . 7-3
Table 7-6: Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-7: Output Signal - MAC/_TESTOUT, REQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-8: Output Signal - IRQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-9: Output Signal - SERR/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-10: Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/,

                  DEVSEL/, STOP/, PERR/, PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

SYM53C810A Data Manual  xiii
List of Tables

Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/ . . . . . . . . . . . . . . . . 7-5
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics. . . . . . . . . . . . . 7-6
Table 7-13: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-14: Reset Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-15: Interrupt Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-16: SYM53C810A PCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Table 7-17: Initiator Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Table 7-18: Initiator Asynchronous Receive Timings (5MB/s) . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Table 7-19: Target Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Table 7-20: Target Asynchronous Receive Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock) . . . . . . . . . . 7-28
Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock) . . . . . . . . . . 7-28

xiv  SYM53C810A Data Manual
                                                                              Introduction
                                                      What is Covered in This Manual

Chapter 1

Introduction

What is Covered in This                               General Description
Manual
                                                      The SYM53C810A PCI-SCSI I/O Processor
This manual provides reference information on the     brings high-performance I/O solutions to host
SYM53C810A PCI- SCSI I/O Processor. It is             adapter, workstation, and general computer
intended for system designers and programmers         designs, making it easy to add SCSI to any PCI
who are using this device to design a SCSI port for   system.
PCI-based personal computers, workstations, or
embedded applications.                                The SYM53C810A is a pin-for-pin replacement
                                                      for the SYM53C810 PCI-SCSI I/O processor. It
This chapter includes general information about       performs Fast SCSI transfers in single-ended
the SYM53C810A and other members of the               mode, and improves performance by optimizing
SYM53C8XX family of PCI-SCSI I/O Processors.          PCI bus utilization. A system diagram showing the
Chapter 2 describes the main functional areas of      connections of the SYM53C810A in a PCI system
the chip in more detail, including the interfaces to  is pictured in Figure 1-1. A block diagram of the
the SCSI bus. Chapter 3 describes the chip's con-     SYM53C810A is pictured in Figure 1-2.
nection to the PCI bus, including the PCI com-
mands and configuration registers supported.          The SYM53C810A integrates a high-perfor-
Chapter 4 contains the pin diagrams and defini-       mance SCSI core, a PCI bus master DMA core,
tions of each signal. Chapter 5 describes each bit    and the Symbios Logic SCSI SCRIPTSTM proces-
in the operating registers, organized by address.     sor to meet the flexibility requirements of SCSI-1,
Chapter 6 defines all of the SCSI SCRIPTS             SCSI-2, and future SCSI standards. It is designed
instructions that are supported by the                to implement multi-threaded I/O algorithms with a
SYM53C810A. Chapter 7 contains the electrical         minimum of processor intervention, solving the
characteristics and AC timings for the chip. The      protocol overhead problems of previous intelligent
appendixes contain a register summary and a           and non-intelligent adapter designs.
mechanical drawing of the SYM53C810A.
                                                      The SYM53C810A is fully supported by the
This data manual assumes the user is familiar with    Symbios Logic SCSI Device Management System
the current and proposed standards for SCSI and       (SDMSTM), a software package that supports the
PCI. For additional background information on         Advanced SCSI Protocol Interface (ASPI). SDMS
these topics, please refer to the list of reference   provides BIOS and driver support for hard disk,
materials provided in the Preface of this docu-       tape, removable media products, and CD-ROM
ment.                                                 under the major PC operating systems.

                                                      The SYM53C810A is packaged in a compact rect-
                                                      angular 100-pin PQFP package to minimize board
                                                      space requirements. It operates the SCSI bus at 5
                                                      MB/s asynchronously or 10 MB/s synchronously,
                                                      and bursts data to the host at full PCI speeds. The

SYM53C810A Data Manual                                1-1
Introduction
TolerANT Technology

SYM53C810A increases SCRIPTS performance            TolerANT Technology
and reduces PCI bus overhead by allowing instruc-
tion prefetches of four or eight dwords.            All Symbios Logic Fast-SCSI devices feature Tol-
                                                    erANT® technology, which includes active nega-
Software development tools are available to devel-  tion on the SCSI drivers and input signal filtering
opers who use the SCSI SCRIPTS language to          on the SCSI receivers. Active negation causes the
create customized SCSI software applications. The   SCSI Request, Acknowledge, Data, and Parity sig-
SYM53C810A allows easy firmware upgrades and        nals to be actively driven high rather than passively
is supported by advanced SCRIPTS commands.          pulled up by terminators. Active negation is
                                                    enabled by setting bit 7 in the STEST3 register in
                                                    the SYM53C8XX family products.

                                                    TolerANT receiver technology improves data
                                                    integrity in unreliable cabling environments, where
                                                    other devices would be subject to data corruption.
                                                    TolerANT receivers filter the SCSI bus signals to
                                                    eliminate unwanted transitions, without the long
                                                    signal delay associated with RC-type input filters.
                                                    This improved driver and receiver technology
                                                    helps eliminate double clocking of data, the single
                                                    biggest reliability issue with SCSI operations.
                                                    TolerANT input signal filtering is a built in feature
                                                    of all Symbios Logic fast SCSI devices. On the
                                                    SYM53C8XX family products, the user may select
                                                    a filtering period of 30 or 60 ns, with bit 1 in the
                                                    STEST2 register.

                                                    The benefits of TolerANT include increased
                                                    immunity to noise when the signal is going high,
                                                    better performance due to balanced duty cycles,
                                                    and improved fast SCSI transfer rates. In addition,
                                                    TolerANT SCSI devices do not cause glitches on
                                                    the SCSI bus at power up or power down, so other
                                                    devices on the bus are also protected from data
                                                    corruption. TolerANT is compatible with both the
                                                    Alternative One and Alternative Two termination
                                                    schemes proposed by the American National Stan-
                                                    dards Institute.

1-2                                                 SYM53C810A Data Manual
                                                                             Introduction
                                                    SYM53C810A Benefits Summary

SYM53C810A Benefits                                 PCI Performance
Summary
                                                    s Bursts 2, 4, 8, or 16 dwords across PCI bus
SCSI Performance                                        with 80-byte DMA FIFO

s Complies with PCI 2.1 specification               s Pre-fetches up to 8 dwords of SCRIPTS
                                                        instructions
s Supports variable block size and scatter/gather
    data transfers                                  s Supports 32-bit word data bursts with variable
                                                        burst lengths.
s Minimizes SCSI I/O start latency
                                                    s Bursts SCRIPTS op code fetches across the
s Performs complex bus sequences without                PCI bus
    interrupts, including restore data pointers
                                                    s Performs zero wait-state bus master data bursts
s Reduces ISR overhead through a unique                 faster than 110 MB/s (@ 33 MHz)
    interrupt status reporting method
                                                    s Supports PCI Cache Line Size Register
s Performs Fast SCSI bus transfers in single-
    ended mode                                      Integration

    s up to 7 MB/s asynchronous                     s 3.3V/5 V PCI Interface
                                                    s Full 32-bit PCI DMA bus master
    s 10 MB/s synchronous                           s DMA controller using Memory to Memory

s New Load and Store SCRIPTS instruction                Move instructions
    increases performance of data transfers to and  s High performance SCSI core
    from the chip registers                         s Integrated SCRIPTS processor
                                                    s Compact 100-pin PQFP packaging
s Support for target to disconnect and later
    reselect with no interrupt to the system        s Ease of Use Direct PCI-to-SCSI connection
    processor
                                                    s Reduced SCSI development effort
s Supports execution of multi-threaded I/O          s Support for the Advanced SCSI Protocol
    algorithms in SCSI SCRIPTS with fast I/O
    context switching                                   Interface (ASPI) software standard via SDMS
                                                        software
                                                    s Compatibility with existing SYM53C7XX and
                                                        53C8XX family SCRIPTS
                                                    s Direct connection to PCI, and SCSI single-
                                                        ended bus
                                                    s Development tools and sample SCSI
                                                        SCRIPTS
                                                    s Maskable and pollable interrupts

SYM53C810A Data Manual                              1-3
Introduction
SYM53C810A Benefits Summary

s Three programmable SCSI timers: Select/         Reliability
    Reselect, Handshake-to-Handshake, and
    General Purpose. The time-out period is       s 2 KV ESD protection on SCSI signals
    programmable from 100 µs to greater than 1.6  s Typical 300 mV SCSI bus hysteresis
    seconds                                       s Average operating supply current of 50 mA
                                                  s Protection against bus reflections due to
s SDMS software for complete PC-based
    operating system support                          impedance mismatches
                                                  s Controlled bus assertion times (reduces RFI,
s Support for relative jump
                                                      improves reliability, and eases FCC
s New SCSI Selected As ID bits for use when           certification)
    responding with multiple IDs                  s Latch-up protection greater than 150 mA
                                                  s Voltage feed through protection (minimum
Flexibility                                           leakage current through SCSI pads)
                                                  s 25% of pins power and ground
s High level programming interface (SCSI          s Power and ground isolation of I/O pads and
    SCRIPTS)                                          internal chip logic
                                                  s Symbios Logic TolerANT technology with:
s Support for execution of tailored SCSI              s Active negation of SCSI Data, Parity,
    sequences from main system RAM
                                                           Request, and Acknowledge signals for
s Flexible programming interface to tune I/O               improved fast SCSI transfer rates.
    performance or to adapt to unique SCSI            s Input signal filtering on SCSI receivers
    devices                                                improves data integrity, even in noisy
                                                           cabling environments.
s Flexibility to accommodate changes in the
    logical I/O interface definition              Testability

s Low level access to all registers and all SCSI  s Access to all SCSI signals through
    bus signals                                       programmed I/O

s Fetch, Master, and Memory Access control        s SCSI loopback diagnostics
    pins                                          s SCSI bus signal continuity checking
                                                  s Single-step mode operation
s Support for indirect fetching of DMA address    s Test mode (AND tree) to check pin continuity
    and byte counts so that SCRIPTS can be
    placed in a PROM                                  to the board

s Separate SCSI and system clocks

s Selectable IRQ pin disable bit

s Ability to route system clock to SCSI clock

1-4                                               SYM53C810A Data Manual
                                                                                                          Introduction
                                                                                 SYM53C810A Benefits Summary

                                        SCSI Connection               SCSI Term Connection

                        Vdd       Vss

PCI                     SYM53C810A                                    SCSI Bus
                                                                                      Peripheral
Bus

                                  SCLK

                        40 MHz Oscillator or                          Bulkhead
                               Optional

                        Internal Connection
                          to PCI Bus Clock

CPU Baseboard

                                    CPU Box
                        Figure 1-1: SYM53C810A System Diagram

                                                 PCI

                                  PCI Master and Slave Control Block

                          Data      SCSI      Operating                Config
                          FIFO    SCRIPTS     Registers               Registers
                        80 Bytes

                               SCSI FIFO and SCSI Control Block
                                                                   TolerANT Technology Drivers and Receivers

                                                               Single-Ended SCSI Bus
                        Figure 1-2: SYM53C810A Chip Block Diagram

SYM53C810A Data Manual                                                                                        1-5
Introduction
SYM53C810A Benefits Summary

1-6                          SYM53C810A Data Manual
                                                      Functional Description
                                                                    SCSI Core

Chapter 2

Functional Description

The SYM53C810A contains three functional              DMA Core
blocks: the SCSI Core, the DMA Core, and the
SCRIPTS Processor. The SYM53C810A is fully            The DMA core is a bus master DMA device that
supported by the SCSI Device Management Sys-          attaches directly to the industry standard PCI Bus.
tem (SDMS), a complete software package that          The DMA core is tightly coupled to the SCSI core
supports the Symbios Logic product line of SCSI       through the SCRIPTS processor, which supports
processors and controllers.                           uninterrupted scatter/gather memory operations.

SCSI Core                                             The SYM53C810A supports 32-bit memory and
                                                      automatically supports misaligned DMA transfers.
The SCSI core supports , synchronous transfer         An 80-byte FIFO allows two, four, eight, or six-
rates up to 10 MB/s, and asynchronous transfer        teen dword bursts across the PCI bus interface to
rates up to 7 MB/s on an 8-bit SCSI bus. The          run efficiently without throttling the bus during
SCSI core can be programmed with SCSI                 PCI bus latency.
SCRIPTS, making it easy to fine tune the system
for specific mass storage devices or advanced SCSI    SCRIPTS Processor
requirements.
                                                      The SCSI SCRIPTS processor allows both DMA
The SCSI core offers low-level register access or a   and SCSI commands to be fetched from host
high-level control interface. Like first generation   memory. Algorithms written in SCSI SCRIPTS
SCSI devices, the SYM53C810A SCSI core can            control the actions of the SCSI and DMA cores
be accessed as a register-oriented device. The abil-  and are executed from 32-bit system RAM. The
ity to sample and/or assert any signal on the SCSI    SCRIPTS processor executes complex SCSI bus
bus can be used in error recovery and diagnostic      sequences independently of the host CPU.
procedures. In support of loopback diagnostics,
the SCSI core can perform a self-selection and        The SCRIPTS processor can begin a SCSI I/O
operate as both an initiator and a target.            operation in approximately 500 ns. This compares
                                                      with 2-8 ms required for traditional intelligent host
The SCSI core is controlled by the integrated         adapters. Algorithms may be designed to tune
SCRIPTS processor through a high-level logical        SCSI bus performance, to adjust to new bus device
interface. Commands controlling the SCSI core         types (such as scanners, communication gateways,
are fetched out of the main host memory or local      etc.), or to incorporate changes in the SCSI-2 or
memory. These commands instruct the SCSI core         SCSI-3 logical bus definitions without sacrificing
to Select, Reselect, Disconnect, Wait for a Discon-   I/O performance. SCSI SCRIPTS are hardware
nect, Transfer Information, Change Bus Phases         independent, so they can be used interchangeably
and, in general, implement all aspects of the SCSI    on any host or CPU system bus.
protocol. The SCRIPTS processor is a special
high-speed processor optimized for SCSI protocol.     A complete set of development tools is available for
                                                      writing custom drivers with SCSI SCRIPTS. For
                                                      more information on SCSI SCRIPTS instructions
                                                      supported by the SYM53C810A, see Chapter 6.

SYM53C810A Data Manual                                2-1
Functional Description
SDMS: The Total SCSI Solution

SDMS: The Total SCSI                                       all recent modifications, the prefetch unit
Solution                                                   flushes its contents and loads the modified
                                                           code every time a MMOV instruction is issued.
For users who do not need to develop custom driv-          To avoid inadvertently flushing the prefetch
ers, Symbios Logic provides a total SCSI solution          unit contents, use the No Flush Memory to
in PC environments with the SCSI Device Man-               Memory Move (NFMMOV) instruction for all
agement System (SDMS). SDMS provides BIOS                  MMOV operations that do not modify code
and driver support for hard disk, tape, and remov-         within the next 4 to 8 dwords. For more
able media peripherals for the major PC-based              information on this instruction, refer to
operating systems.                                         Chapter 6.

SDMS includes a SCSI BIOS to manage all SCSI           2. On every Store instruction. The Store
functions related to the device. It also provides a        instruction may also be used to place modified
series of SCSI device drivers that support most            code directly into memory. To avoid
major operating systems. SDMS supports a multi-            inadvertently flushing the prefetch unit
threaded I/O application programming interface             contents, use the No Flush option for all Store
(API) for user-developed SCSI applications.                operations that do not modify code within the
SDMS supports both the ASPI and CAM SCSI                   next 8 dwords.
software specifications.
                                                       3. On every write to the DSP register.
Prefetching SCRIPTS
Instructions                                           4. On all Transfer Control instructions when the
                                                           transfer conditions are met. This is necessary
When enabled (by setting the Prefetch Enable bit           because the next instruction to be executed is
in the DCNTL register), the prefetch logic in the          not the sequential next instruction in the
SYM53C810A fetches 4 or 8 dwords of instruc-               prefetch unit.
tions. The prefetch logic automatically determines
the maximum burst size that it can perform, based      5. When the Pre-Fetch Flush bit (DCNTL bit 5)
on the burst length as determined by the values in         is set. The unit flushes whenever this bit is set.
the DMODE register and the PCI Cache Line Size             The bit is self-clearing.
register (if cache mode is enabled). If the unit can-
not perform bursts of at least four dwords, it will    Op Code Fetch
disable itself.                                        Burst Capability

The SYM53C810A may flush the contents of the           Setting the Burst Op Code Fetch Enable bit in the
prefetch unit under certain conditions, listed         DMODE register (38h) causes the SYM53C810A
below, to ensure that the chip always operates from    to burst in the first two dwords of all instruction
the most current version of the software.When one      fetches. If the instruction is a memory-to-memory
of these conditions apply, the contents of the         move, the third dword will be accessed in a sepa-
prefetch unit are flushed automatically.               rate ownership. If the instruction is an indirect
                                                       type, the additional dword will be accessed in a
1. On every Memory Move instruction. The               subsequent bus ownership. If the instruction is a
    Memory Move (MMOV) instruction is often            table indirect Block Move, the SYM53C810A will
    used to place modified code directly into          use two accesses to obtain the four dwords
    memory. To make sure that the chip executes        required, in two bursts of two dwords each.

                                                       Note: this feature can only be used if SCRIPTS
                                                                pre-fetching is disabled.

2-2                                                    SYM53C810A Data Manual
                                                                        Functional Description
                                                                              PCI Cache Mode

PCI Cache Mode                                          Parity Options

The SYM53C810A supports the PCI specification           The SYM53C810A implements a flexible parity
for an 8-bit Cache Line Size register located in        scheme that allows control of the parity sense,
PCI configuration space. The Cache Line Size reg-       allows parity checking to be turned on or off, and
ister provides the ability to sense and react to non-   has the ability to deliberately send a byte with bad
aligned addresses corresponding to cache line           parity over the SCSI bus to test parity error recov-
boundaries. In conjunction with the Cache Line          ery procedures. Table 2-1 defines the bits that are
Size register, the PCI commands Read Line, Read         involved in parity control and observation.
Multiple, and Write and Invalidate are each soft-       Table 2-2 describes the parity control function of
ware enabled or disabled to allow the user full flex-   the Enable Parity Checking and Assert SCSI Even
ibility in using these commands. For more               Parity bits in the SCNTL0 register. Table 2-3
information on PCI cache mode operations, refer         describes the options available when a parity error
to Chapter 3.                                           occurs.

Load/Store Instructions

The SYM53C810A supports the Load/Store
instruction type, which simplifies the movement of
data between memory and the internal chip regis-
ters. It also enables the SYM53C810A to transfer
bytes to addresses relative to the DSA register. For
more information on the Load and Store instruc-
tions, refer to Chapter 6.

3.3 Volt/5 Volt PCI Interface

The SYM53C810A can attach directly to a 3.3.
Volt or a 5 Volt PCI interface, due to separate VDD
pins for the PCI bus drivers. This allows the
devices to be used on the universal board recom-
mended by the PCI Special Interest Group.

Loopback Mode

The SYM53C810A loopback mode allows testing
of both initiator and target functions and, in effect,
lets the chip communicate with itself. When the
Loopback Enable bit is set in the STEST1 register,
the SYM53C810A allows control of all SCSI sig-
nals, whether it is operating in initiator or target
mode. For more information on this mode of oper-
ation, refer to the SYM53C8XX Family Program-
ming Guide.

SYM53C810A Data Manual                                                  2-3
Functional Description
Parity Options

                        Table 2-1: Bits Used for Parity Control and Observation

BIt Name                Location       Description

Assert SATN/ on         SCNTL0, Bit 1  Causes the SYM53C810A to automatically assert SATN/ when
Parity Errors                          it detects a parity error while operating on the SCSI bus as an
                        SCNTL0, Bit 3  initiator.
Enable Parity           SCNTL1, Bit 2
Checking                SCNTL1, Bit 5  Enables the SYM53C810A to check for parity errors on the
Assert Even SCSI                       SCSI bus. The SYM53C810A checks for odd parity.
Parity
Disable Halt on                        Determines the SCSI parity sense generated by the
SATN/ or a Parity                      SYM53C810A to the SCSI bus.
Error (Target Mode
Only)                                  Causes the SYM53C810A not to halt operations when a SCSI
Enable Parity Error                    parity error is detected in target mode.
Interrupt
Parity Error            SIEN0, Bit 0   Determines whether the SYM53C810A will generate an inter-
                        SIST0, Bit 0   rupt when it detects a SCSI parity error.
Status of SCSI          SSTAT0, Bit 0  This status bit is set whenever the SYM53C810A has detected a
Parity Signal           SSTAT1, Bit 3  parity error on the SCSI bus.
Latched SCSI Parity     CTEST4, Bit 3  This status bit represents the live SCSI Parity Signal (SDP).
                        DSTAT, Bit 6
Master Parity Error     DIEN, Bit 6    This bit reflects the SCSI odd parity signal corresponding to the
Enable                                 data latched into the SIDL register
Master Data Parity                     Enables PCI parity checking during master data phases.
Error
Master Data Parity                     Set when the SYM53C810A as a PCI master detects that a tar-
Error Interrupt                        get device has signalled a parity error during a data phase.
Enable                                 By clearing this bit, a Master Data Parity Error will not cause
                                       IRQ/ to be asserted, but the status bit will be set in the DSTAT
                                       register.

2-4                                                                              SYM53C810A Data Manual
                                                                                                  Functional Description
                                                                                                           Parity Options

                              Table 2-2: SCSI Parity Control

EPC                     AESP                   Description

0                       0                      Will not check for parity errors. Parity is generated when send-
                                               ing SCSI data. Asserts odd parity when sending SCSI data.
0                       1
                                               Will not check for parity errors. Parity is generated when send-
1                       0                      ing SCSI data. Asserts even parity when sending SCSI data.

1                       1                      Checks for odd parity on SCSI data received. Parity is generated
                                               when sending SCSI data. Asserts odd parity when sending SCSI
                                               data.

                                               Checks for odd parity on SCSI data received. Parity is generated
                                               when sending SCSI data. Asserts even parity when sending
                                               SCSI data.

Key:
EPC = Enable Parity Checking (bit 3 SCNTL0)
ASEP = Assert SCSI Even Parity (bit 2 SCNTL1)

                              Table 2-3: SCSI Parity Errors and Interrupts

DHP                     PAR                    Description

0                       0                      Will halt when a parity error occurs in target or initiator mode

                                               and will NOT generate an interrupt.

0                       1                      Will halt when a parity error occurs in target mode and will gen-

                                               erate an interrupt in target or initiator mode.

1                       0                      Will not halt in target mode when a parity error occurs until the

                                               end of the transfer. An interrupt will not be generated.

1                       1                      Will not halt in target mode when a parity error occurs until the

                                               end of the transfer. An interrupt will be generated.

Key: DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCNTL1) PAR = Parity Error (bit 0 SIEN0)

This table only applies when the Enable Parity Checking bit is set.

SYM53C810A Data Manual                                                                                           2-5
Functional Description
DMA FIFO

DMA FIFO

The DMA FIFO is divided into four sections, each one byte wide and 20 transfers deep. The DMA FIFO
is illustrated in Figure 2-1.

                                                                                                 32 Bits Wide

                             20
                           Bytes
                            Deep

        8 Bits       8 Bits       8 Bits            8 Bits
     Byte Lane 3  Byte Lane 2  Byte Lane 1       Byte Lane 0

                  Figure 2-1: DMA FIFO Sections

2-6                                                           SYM53C810A Data Manual
                                                      Functional Description
                                                                    DMA FIFO

Data Paths                                            Asynchronous SCSI Receive

The data path through the SYM53C810A is               1. Look at the DFIFO and DBC registers and
dependent on whether data is being moved into or          calculate if there are bytes left in the DMA
out of the chip, and whether SCSI data is being           FIFO. To make this calculation, subtract the
transferred asynchronously or synchronously.              seven least significant bits of the DBC register
                                                          from the 7-bit value of the DFIFO register.
Figure 2-2 shows how data is moved to/from the            AND the result with 7Fh for a byte count
SCSI bus in each of the different modes.                  between 0 and 80.

The following steps determine if any bytes remain     2. Read bit 7 in the SSTAT0 register to
in the data path when the chip halts an operation:        determine if any bytes are left in the SIDL
                                                          register. If bit 7 is set in SSTAT0, then the
Asynchronous SCSI Send                                    SIDL register is full.

1. Look at the DFIFO and DBC registers and            Synchronous SCSI Receive
    calculate if there are bytes left in the DMA
    FIFO. To make this calculation, subtract the      1. Subtract the seven least significant bits of the
    seven least significant bits of the DBC register      DBC register from the 7-bit value of the
    from the 7-bit value of the DFIFO register.           DFIFO register. AND the result with 7Fh for a
    AND the result with 7Fh for a byte count              byte count between 0 and 80.
    between zero and 80.
                                                      2. Read the SSTAT1 register and examine bits 7-
2. Read bit 5 in the SSTAT0 register to                   4, the binary representation of the number of
    determine if any bytes are left in the SODL           valid bytes in the SCSI FIFO, to determine if
    register. If bit 5 is set in SSTAT0, then the         any bytes are left in the SCSI FIFO.
    SODL register is full.

Synchronous SCSI Send

1. Look at the DFIFO and DBC registers and
    calculate if there are bytes left in the DMA
    FIFO. To make this calculation, subtract the
    seven least significant bits of the DBC register
    from the 7-bit value of the DFIFO register.
    AND the result with 7Fh for a byte count
    between zero and 80.

2. Read bit 5 in the SSTAT0 register to
    determine if any bytes are left in the SODL
    register. If bit 5 is set in SSTAT0, then the
    SODL register is full.

3. Read bit 6 in the SSTAT0 register to
    determine if any bytes are left in the SODR
    register. If bit 6 is set in SSTAT0, then the
    SODR register is full.

SYM53C810A Data Manual                                2-7
Functional Description
DMA FIFO

                         PCI Interface    PCI Interface   PCI Interface   PCI Interface

                          DMA FIFO        DMA FIFO         DMA FIFO        DMA FIFO
                        (4 bytes x 20)  (4 bytes x 20)   (4 bytes x 20)  (4 bytes x 20)

                        SODL Register   SIDL Register    SODL Register     SCSI FIFO
                        SCSI Interface  SCSI Interface
                                                         SODR Register   SCSI Interface
                        Asynchronous    Asynchronous
                          SCSI Send     SCSI Receive     SCSI Interface  Synchronous
                                                         Synchronous     SCSI Receive
                                                           SCSI Send

                        Figure 2-2: SYM53C810A Host Interface Data Paths

2-8                                                                                      SYM53C810A Data Manual
                                                      Functional Description
                                                         SCSI Bus Interface

SCSI Bus Interface                                    (Re)Select During
                                                      (Re)Selection
The SYM53C810A supports single-ended opera-
tion only. All SCSI signals are active low. The       In multi-threaded SCSI I/O environments, it is not
SYM53C810A contains the single-ended output           uncommon to be selected or reselected while try-
drivers and can be connected directly to the SCSI     ing to perform selection/reselection. This situation
bus. Each output is isolated from the power supply    may occur when a SCSI controller (operating in
to ensure that a powered-down SYM53C810A has          initiator mode) tries to select a target and is rese-
no effect on an active SCSI bus (CMOS "voltage        lected by another. The Select SCRIPTS instruc-
feed-through" phenomena). TolerANT technol-           tion has an alternate address to which the
ogy provides signal filtering at the inputs of SREQ/  SCRIPTS will jump when this situation occurs.
and SACK/ to increase immunity to signal reflec-      The analogous situation for target devices is being
tions.                                                selected while trying to perform a reselection.

Terminator                                            Once a change in operating mode occurs, the initi-
Networks                                              ator SCRIPTS should start with a Set Initiator
                                                      instruction or the target SCRIPTS should start
The terminator networks provide the biasing           with a Set Target instruction. The Selection and
needed to pull signals to an inactive voltage level,  Reselection Enable bits (SCID bits 5 and 6,
and to match the impedance seen at the end of the     respectively) should both be set so that the
cable with the characteristic impedance of the        SYM53C810A may respond as an initiator or as a
cable.Terminators must be installed at the extreme    target. If only selection is enabled, the
ends of the SCSI chain, and only at the ends; no      SYM53C810A cannot be reselected as an initiator.
system should ever have more or less than two ter-    There are also status and interrupt bits in the
minators installed and active. SCSI host adapters     SIST0 and SIEN0 registers, respectively, indicat-
should provide a means of accommodating termi-        ing that the SYM53C810A has been selected (bit
nators. The terminators should be socketed, so        5) or reselected (bit 4).
that if not needed they may be removed, or there
should be a means of disabling them with software.

Single-ended cables can use a 220  pull-up to the
terminator power supply (Term-Power) line and a
330  pull-down to Ground. Symbios recom-
mends active or regulated termination (also known
as Alt-2 or Alternative Two termination) to maxi-
mize the high performance of the SYM53C810A.
Figure 2-3 shows a Unitrode active terminator for
regulated termination. For additional information,
refer to the SCSI-2 Specification. TolerANT active
negation can be used with any ANSI-approved ter-
mination network.

SYM53C810A Data Manual                                2-9
Functional Description
SCSI Bus Interface

                                 UC5601QP

      2.85V                     2               TERML1 20            SD0 (J1.2)
                     C1 C2           REG_OUT    TERML2 21            SD1 (J1.4)
                                                TERML3 22            SD2 (J1.6)
                                19              TERML4 23            SD3 (J1.8)
                                    DISCONNECT  TERML5 24            SD4 (J1.10)
                                                TERML6 25            SD5 (J1.12)
                                                TERML7 26            SD6 (J1.14)
                                                TERML8 27            SD7 (J1.16)
                                                TERML9 28            SD8 (J1.18)
                                                TERML10 3
                                                TERML11 4            ATN (J1.32)
                                                TERML12 5            BSY (J1.36)
                                                TERML13 6            ACK (J1.38)
                                                TERML14 7            RST (J1.40)
                                                TERML15 8            MSG (J1.42)
                                                TERML16 9            SEL (J1.44)
                                                TERML17 10           C/D (J1.46)
                                                TERML18 11           REQ (J1.48)
                                                                     I/O (J1.50)

                            Key

                            C1 10 µF SMT

                            C2 0.1 µF SMT

                            J1   68-pin, high density "P" connector

                                 Figure 2-3: Active or Regulated Termination

2-10                                                                              SYM53C810A Data Manual
                                                          Functional Description
                                                        Synchronous Operation

Synchronous Operation                                   For synchronous send, the output of the SCF
                                                        divider is divided by the transfer period (XFERP)
The SYM53C810A can transfer synchronous                 bits in the SCSI Transfer (SXFER) register. For
SCSI data in both initiator and target modes. The       valid combinations of the SCF and the XFERP,
SXFER register controls both the synchronous off-       see Table 5-4 and Table 5-5, under the description
set and the transfer period. It may be loaded by the    of the XFERP bits 7-5 in the SXFER register.
CPU before SCRIPTS execution begins, from
within SCRIPTS via a Table Indirect I/O instruc-        SCNTL3 Register, bits 2­0 (CCF2­0)
tion, or with a Read-Modify-Write instruction.
                                                        The CCF2-0 bits select the frequency of the
The SYM53C810A can receive data from the                SCLK for asynchronous SCSI operations. To meet
SCSI bus at a synchronous transfer period as short      the SCSI timings as defined by the ANSI specifica-
as 80 ns or 160 ns (with a 50 MHz clock), regard-       tion, these bits need to be set properly.
less of the transfer period used to send data. The
SYM53C810A can receive data at one-fourth of            SXFER Register, bits 7­5 (TP2­0)
the divided SCLK frequency. Depending on the
SCLK frequency, the negotiated transfer period,         The TP2-0 divider (XFERP) bits determine the
and the synchronous clock divider, the                  SCSI synchronous send rate in either initiator or
SYM53C810A can send synchronous data at                 target mode. This value further divides the output
intervals as short as 100 ns for fast SCSI-2 and        from the SCF divider.
200 ns for SCSI-1.
                                                        Achieving Optimal SCSI Send Rates
Determining the
Data Transfer Rate                                      To achieve optimal synchronous SCSI send tim-
                                                        ings, the SCF divisor value should be set high, to
Synchronous data transfer rates are controlled by       divide the clock as much as possible before pre-
bits in two different registers of the                  senting the clock to the TP divider bits in the
SYM53C810A. A brief description of the bits is          SXFER register. The TP2-0 divider value should
provided below. Figure 2-4 illustrates the clock        be as low as possible. For example, with 40 MHz
division factors used in each register, and the role    clock to achieve a 5 MB/s send rate, the SCF bits
of the register bits in determining the transfer rate.  can be set to divide by 1 and the TP bits to divide
                                                        by 8; or the SCF bits can be set to divide by 2 and
SCNTL3 Register, bits 6­4 (SCF2­0)                      the TP bits set to divide by 4. Use the second
                                                        option to achieve optimal SCSI timings.
The SCF2-0 bits select the factor by which the fre-
quency of SCLK is divided before being presented
to the synchronous SCSI control logic. The output
from this divider controls the rate at which data
can be received; this rate must not exceed 50
MHz. The receive rate is 1/4 of the divider output.
For example, if SCLK is 40MHz and the SCF
value is set to divide by one, then the maximum
rate at which data can be received is 10 MB/s (40/
(1*4) = 10).

SYM53C810A Data Manual                                  2-11
Functional Description
Synchronous Operation

      SCF2  SCF1        SCF0  SCF                           TP2  TP1             TP0  XFERP
                              Divisor                                                 Divisor
      0     0           1     1                             0    0               0
      0     1           0     1.5                                                     4
      0     1           1     2                             0    0               1    5
      1     0           0     3                                                       6
      0     0           0     3                             0    1               0    7
                                                                                      8
                                       SCF                  0    1               1    9
                                      Divider                                         10
                                                            1    0               0    11
                                       CCF
                                      Divider               1    0               1         Receive
                                                                                           Clock
                                                            1    1               0
                                                                                       Send Clock
                                                            1    1               1    (to SCSI bus)

            SCLK                               This point-          Divide by 4
                                               must not
                                                                 Synchronous
                                               exceed 50              Divider
                                               MHz
                                                                 Asynchronous
                                                                   SCSI Logic

      CCF2  CCF1        CCF0  SCSI Clock   Example:
                              (MHz)
      0     0           0                  SCLK= 40 MHz, SCF=1(/1), XFERP=0(/4),
      0     0           1     50.1-66.00   CCF=3(37.51-50.00 MHz)
      0     1           0     16.67-25.00  Synchronous send rate=(SCLK/SCF)/XFERP=
      0     1           1     25.01-37.50  (40/1)/4= 10 MB/s
      1     0           0     37.51-50.00  Synchronous receive rate=(SCLK/SCF) / 4=(40/1)/4= 10 MB/s
                              50.01-66.00

                        Figure 2-4: Determining the Synchronous Transfer Rate

2-12                                                                                  SYM53C810A Data Manual
                                                         Functional Description
                                                             Interrupt Handling

Interrupt Handling                                       ISTAT register is set, then a SCSI-type interrupt
                                                         has occurred and the SIST0 and SIST1 registers
The SCRIPTS processor in the SYM53C810A                  should be read. If the DIP bit in the ISTAT regis-
performs most functions independently of the host        ter is set, then a DMA-type interrupt has occurred
microprocessor. However, certain interrupt situa-        and the DSTAT register should be read. SCSI-
tions must be handled by the external micropro-          type and DMA-type interrupts may occur simulta-
cessor. This section explains all aspects of             neously, so in some cases both SIP and DIP may
interrupts as they apply to the SYM53C810A.              be set.

Polling and                                              SIST0 and SIST1
Hardware Interrupts
                                                         The SIST0 and SIST1 registers contain the SCSI-
The external microprocessor is informed of an            type interrupt bits. Reading these registers will
interrupt condition by polling or hardware inter-        determine which condition or conditions caused
rupts. Polling means that the microprocessor must        the SCSI-type interrupt, and will clear that SCSI
continually loop and read a register until it detects    interrupt condition. If the SYM53C810A is receiv-
a bit set that indicates an interrupt. This method is    ing data from the SCSI bus and a fatal interrupt
the fastest, but it wastes CPU time that could be        condition occurs, the SYM53C810A will attempt
used for other system tasks. The preferred method        to send the contents of the DMA FIFO to memory
of detecting interrupts in most systems is hardware      before generating the interrupt. If the
interrupts. In this case, the SYM53C810A will            SYM53C810A is sending data to the SCSI bus
assert the Interrupt Request (IRQ/) line that will       and a fatal SCSI interrupt condition occurs, data
interrupt the microprocessor, causing the micro-         could be left in the DMA FIFO. Because of this
processor to execute an interrupt service routine. A     the DMA FIFO Empty (DFE) bit in DSTAT
hybrid approach would use hardware interrupts for        should be checked. If this bit is clear, set the CLF
long waits, and use polling for short waits.             (Clear DMA FIFO) and CSF (Clear SCSI FIFO)
                                                         bits before continuing. The CLF bit is bit 2 in
                                                         CTEST3. The CSF bit is bit 1 in STEST3.

Registers                                                DSTAT

The registers in the SYM53C810A that are used            The DSTAT register contains the DMA-type
for detecting or defining interrupts are the ISTAT,      interrupt bits. Reading this register will determine
SIST0, SIST1, DSTAT, SIEN0, SIEN1,                       which condition or conditions caused the DMA-
DCNTL, and DIEN.                                         type interrupt, and will clear that DMA interrupt
                                                         condition. The DFE bit, bit 7 in DSTAT, is purely
ISTAT                                                    a status bit; it will not generate an interrupt under
                                                         any circumstances and will not be cleared when
The ISTAT is the only register that can be               read. DMA interrupts will flush neither the DMA
accessed as a slave during SCRIPTS operation,            nor SCSI FIFOs before generating the interrupt,
therefore it is the register that is polled when         so the DFE bit in the DSTAT register should be
polled interrupts are used. It is also the first regis-  checked after any DMA interrupt. If the DFE bit
ter that should be read when the IRQ/ pin has been       is clear, then the FIFOs must be cleared by setting
asserted in association with a hardware interrupt.       the CLF (Clear DMA FIFO) and CSF (Clear
The INTF (Interrupt on the Fly) bit should be the        SCSI FIFO) bits, or flushed by setting the FLF
first interrupt serviced. It must be written to one to   (Flush DMA FIFO) bit.
be cleared. This interrupt must be cleared before
servicing any other interrupts. If the SIP bit in the

SYM53C810A Data Manual                                   2-13
Functional Description
Interrupt Handling

SIEN0 and SIEN1                                        configure the chip's behavior when the SATN/
                                                       interrupt is enabled during target role operation.
The SIEN0 and SIEN1 registers are the interrupt        The Interrupt on the Fly interrupt is also non-
enable registers for the SCSI interrupts in SIST0      fatal, since SCRIPTS can continue when it occurs.
and SIST1.
                                                       The reason for non-fatal interrupts is to prevent
DIEN                                                   SCRIPTS from stopping when an interrupt occurs
                                                       that does not require service from the CPU. This
The DIEN register is the interrupt enable register     prevents an interrupt when arbitration is complete
for DMA interrupts in DSTAT.                           (CMP set), when the SYM53C810A has been
                                                       selected or reselected (SEL or RSL set), when the
DCNTL                                                  initiator has asserted ATN (target mode: SATN/
                                                       active), or when the General Purpose or Hand-
When bit 1 in this register is set, the IRQ/ pin will  shake to Handshake timers expire. These inter-
not be asserted when an interrupt condition            rupts do not require CPU intervention during
occurs. The interrupt is not lost or ignored, but      high-level SCRIPTS operation.
merely masked at the pin. Clearing this bit when
an interrupt is pending will immediately cause the     Masking
IRQ/ pin to assert. As with any register other than
ISTAT, this register cannot be accessed except by a    Masking an interrupt means disabling or ignoring
SCRIPTS instruction during SCRIPTS execution.          that interrupt. Interrupts can be masked by clear-
                                                       ing bits in the SIEN0 and SIEN1 (for SCSI inter-
Fatal vs. Non-Fatal                                    rupts) registers or the DIEN (for DMA interrupts)
Interrupts                                             register. How the chip will respond to masked
                                                       interrupts depends on: whether polling or hard-
A fatal interrupt, as the name implies, always         ware interrupts are being used; whether the inter-
causes SCRIPTS to stop running. All non-fatal          rupt is fatal or non-fatal; and whether the chip is
interrupts become fatal when they are enabled by       operating in initiator or target role.
setting the appropriate interrupt enable bit. For
more information on interrupt masking, see the         If a non-fatal interrupt is masked and that condi-
discussion on masking later in this section. All       tion occurs, SCRIPTS will not stop, the appropri-
DMA interrupts (indicated by the DIP bit in            ate bit in the SIST0 or SIST1 will still be set, the
ISTAT and one or more bits in DSTAT being set)         SIP bit in the ISTAT will not be set, and the IRQ/
are fatal.                                             pin will not be asserted. See the section on non-
                                                       fatal vs. fatal interrupts for a list of the non-fatal
Some SCSI interrupts (indicated by the SIP bit in      interrupts.
the ISTAT and one or more bits in SIST0 or
SIST1 being set) are non-fatal. When the               If a fatal interrupt is masked and that condition
SYM53C810A is operating in initiator role, only        occurs, then SCRIPTS will still stop, the appropri-
the Function Complete (CMP), Selected (SEL),           ate bit in the DSTAT, SIST0, or SIST1 register
Reselected (RSL), General Purpose Timer Expired        will be set, and the SIP or DIP bits in the ISTAT
(GEN), and Handshake to Handshake Timer                will be set, but the IRQ/ pin will not be asserted.
Expired (HTH) interrupts are non-fatal. When
operating in target role CMP, SEL, RSL, Target         When the chip is initialized, enable all fatal inter-
mode: SATN/ active (M/A), GEN, and HTH are             rupts if you are using hardware interrupts. If a fatal
non-fatal. Refer to the description for the Disable    interrupt is disabled and that interrupt condition
Halt on a Parity Error or SATN/ active (Target
Mode Only) (DHP) bit in the SCNTL1 register to

2-14                                                   SYM53C810A Data Manual
                                                         Functional Description
                                                             Interrupt Handling

occurs, SCRIPTS will halt and the system will            set, there is a small timing window in which multi-
never know it unless it times out and checks the         ple interrupts can occur but will not be stacked.
ISTAT after a certain period of inactivity.              These could be multiple SCSI interrupts (SIP set),
                                                         multiple DMA interrupts (DIP set), or multiple
If you are polling the ISTAT instead of using hard-      SCSI and multiple DMA interrupts (both SIP and
ware interrupts, then masking a fatal interrupt will     DIP set).
make no difference since the SIP and DIP bits in
the ISTAT inform the system of interrupts, not the       As previously mentioned, DMA interrupts will not
IRQ/ pin.                                                attempt to flush the FIFOs before generating the
                                                         interrupt. It is important to set the Clear DMA
Masking an interrupt after IRQ/ is asserted will not     FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a
cause IRQ/ to be deasserted.                             DMA interrupt occurs and the DMA FIFO Empty
                                                         (DFE) bit is not set. This is because any future
Stacked Interrupts                                       SCSI interrupts will not be posted until the DMA
                                                         FIFO is clear of data. These `locked out' SCSI
The SYM53C810A stacks interrupts if they occur           interrupts will be posted as soon as the DMA
one after another. If the SIP or DIP bits in the         FIFO is empty.
ISTAT register are set (first level), then there is
already at least one pending interrupt, and any          Halting in an
future interrupts will be stacked in extra registers     Orderly Fashion
behind the SIST0, SIST1, and DSTAT registers
(second level). When two interrupts have occurred        When an interrupt occurs, the SYM53C810A will
and the two levels of the stack are full, any further    attempt to halt in an orderly fashion.
interrupts will set additional bits in the extra regis-
ters behind SIST0, SIST1, and DSTAT. When the            s If the interrupt occurs in the middle of an
first level of interrupts are cleared, all the inter-        instruction fetch, the fetch will be completed,
rupts that came in afterward will move into the              except in the case of a Bus Fault. Execution
SIST0, SIST1, and DSTAT. After the first inter-              will not begin, but the DSP will point to the
rupt is cleared by reading the appropriate register,         next instruction since it is updated when the
the IRQ/ pin will be deasserted for a minimum of             current instruction is fetched.
three CLKs; the stacked interrupt(s) will move
into the SIST0, SIST1, or DSTAT; and the IRQ/            s If the DMA direction is a write to memory and
pin will be asserted once again.                             a SCSI interrupt occurs, the SYM53C810A
                                                             will attempt to flush the DMA FIFO to
Since a masked non-fatal interrupt will not set the          memory before halting. Under any other
SIP or DIP bits, interrupt stacking will not occur.          circumstances only the current cycle will be
A masked, non-fatal interrupt will still post the            completed before halting, so the DFE bit in
interrupt in SIST0, but will not assert the IRQ/             DSTAT should be checked to see if any data
pin. Since no interrupt is generated, future inter-          remains in the DMA FIFO.
rupts will move right into the SIST0 or SIST1
instead of being stacked behind another interrupt.       s SCSI SREQ/SACK handshakes that have
When another condition occurs that generates an              begun will be completed before halting.
interrupt, the bit corresponding to the earlier
masked non-fatal interrupt will still be set.            s The SYM53C810A will attempt to clean up
                                                             any outstanding synchronous offset before
A related situation to interrupt stacking is when            halting.
two interrupts occur simultaneously. Since stack-
ing does not occur until the SIP or DIP bits are         s In the case of Transfer Control Instructions,
                                                             once instruction execution begins it will
                                                             continue to completion before halting.

SYM53C810A Data Manual                                   2-15
Functional Description
Interrupt Handling

s If the instruction is a JUMP/CALL WHEN/IF          6. When using polled interrupts, go back to step
    <phase>, the DSP will be updated to the              1 before leaving the interrupt service routine,
    transfer address before halting.                     in case any stacked interrupts moved in when
                                                         the first interrupt was cleared. When using
s All other instructions may halt before                 hardware interrupts, the IRQ/ pin will be
    completion.                                          asserted again if there are any stacked
                                                         interrupts. This should cause the system to re-
Sample Interrupt                                         enter the interrupt service routine.
Service Routine

The following is a sample of an interrupt service
routine for the SYM53C810A. It can be repeated
if polling is used, or should be called when the
IRQ/ pin is asserted if hardware interrupts are
used.

1. Read ISTAT.

2. If the INTF bit is set, it must be written to a
    one to clear this status.

3. If only the SIP bit is set, read SIST0 and
    SIST1 to clear the SCSI interrupt condition
    and get the SCSI interrupt status. The bits in
    the SIST0 and SIST1 tell which SCSI
    interrupt(s) occurred and determine what
    action is required to service the interrupt(s).

4. If only the DIP bit is set, read the DSTAT to
    clear the interrupt condition and get the DMA
    interrupt status. The bits in the DSTAT will
    tell which DMA interrupt(s) occurred and
    determine what action is required to service
    the interrupt(s).

5. If both the SIP and DIP bits are set, read
    SIST0, SIST1, and DSTAT to clear the SCSI
    and DMA interrupt condition and get the
    interrupt status. If using 8-bit reads of the
    SIST0, SIST1, and DSTAT registers to clear
    interrupts, insert a 12 CLK delay between the
    consecutive reads to ensure that the interrupts
    clear properly. Both the SCSI and DMA
    interrupt conditions should be handled before
    leaving the ISR. It is recommended that the
    DMA interrupt be serviced before the SCSI
    interrupt, because a serious DMA interrupt
    condition could influence how the SCSI
    interrupt is acted upon.

2-16                                                 SYM53C810A Data Manual
                                                       PCI Functional Description
                                                                   PCI Addressing

Chapter 3

PCI Functional Description

PCI Addressing                                         SYM53C810A compares its assigned base
                                                       addresses with the value on the Address/Data bus
There are three types of PCI-defined address           during the PCI address phase. If there is a match
space:                                                 of the upper 24 bits, the access is for the
                                                       SYM53C810A and the low order eight bits define
s Configuration space                                  the register to be accessed. A decode of C_BE/ (3-
                                                       0) determines which registers and what type of
s Memory space                                         access is to be performed.

s I/O space                                            PCI defines memory space as a contiguous 32-bit
                                                       memory address that is shared by all system
Configuration space is a contiguous 256-byte set of    resources, including the SYM53C810A. Base
addresses dedicated to each "slot" or "stub" on the    Address Register One determines which 256-byte
bus. Decoding C_BE/(3-0) determines if a PCI           memory area this device will occupy.
cycle is intended to access configuration register
space. The IDSEL bus signal is a chip select that      PCI defines I/O space as a contiguous 32-bit I/O
allows access to the configuration register space      address that is shared by all system resources,
only. Any attempt to access configuration space        including the SYM53C810A. Base Address Regis-
will be ignored unless IDSEL is asserted.The eight     ter Zero determines which 256-byte I/O area this
lower order address lines and byte enables are used    device will occupy.
to select a specific 8-bit register. The host proces-
sor uses this configuration space to initialize the    PCI Bus Commands and
SYM53C810A. Figure 3-1 contains a list of the          Functions Supported
PCI configuration registers supported in the
SYM53C810A.                                            Bus commands indicate to the target the type of
                                                       transaction the master is requesting. Bus com-
The lower 128 bytes of the SYM53C810A config-          mands are encoded on the C_BE/(3-0) lines dur-
uration space hold system parameters while the         ing the address phase. PCI bus command
upper 128 bytes map into the SYM53C810A                encoding and types appear in Table 3-1.
operating registers. For all PCI cycles except con-
figuration cycles, the SYM53C810A registers are        The I/O Read command is used to read data from
located on the 256-byte block boundary defined by      an agent mapped in I/O address space. All 32
the base address assigned through the configured       address bits are decoded.
register.The SYM53C810A operating registers are
available in both the upper and lower 128-byte         The I/O Write command is used to write data to an
portions of the 256-byte space selected.               agent when mapped in I/O address space. All 32
                                                       address bits are decoded.
At initialization time, each PCI device is assigned a
base address (in the case of the SYM53C810A, the
upper 24 bits of the address are used) for memory
accesses and I/O accesses. On every access, the

SYM53C810A Data Manual                                 3-1
PCI Functional Description
PCI Cache Mode

The Memory Read, Memory Read Multiple, and             Note: the SYM53C810A will not automatically
Memory Read Line commands are used to read                      use the value in the PCI Cache Line Size
data from an agent mapped in memory address                     register as the cache line size value. The
space. All 32 address bits are decoded.                         chip scales the value of the Cache Line Size
                                                                register down to the nearest binary burst
The Memory Write and Memory Write and Invali-                   size allowed by the chip (2, 4, 8 or 16),
date commands are used to write data to an agent                compares this value to the DMODE burst
when mapped in memory address space. All 32                     size, then selects the smallest as the value
address bits are decoded.                                       for the cache line size. The SYM53C810A
                                                                will use this value for all burst data
PCI Cache Mode                                                  transfers.

The SYM53C810A supports the PCI specification          Alignment
for an 8-bit Cache Line Size register located in
PCI configuration space. The Cache Line Size reg-      The SYM53C810A uses the calculated burst size
ister provides the ability to sense and react to non-  value to monitor the current address for alignment
aligned addresses corresponding to cache line          to the cache line size. When it is not aligned the
boundaries. In conjunction with the Cache Line         chip disables bursting, allowing only single dword
Size register, the PCI commands Read Line, Read        transfers until a cache line boundary is reached.
Multiple, and Write and Invalidate are each soft-      When the chip is aligned, bursting is re-enabled it
ware enabled or disabled to allow the user full flex-  will burst in increments specified by the Cache
ibility in using these commands.                       Line Size register as explained above. If the Cache
                                                       Line Size register is not set (default = 00h), the
Support for PCI                                        DMODE burst size is automatically used as the
Cache Line Size Register                               cache line size.

The SYM3C810A supports the PCI specification           MMOV
for an 8-bit Cache Line Size register in PCI config-   Misalignment
uration space; it can sense and react to non-aligned
addresses corresponding to cache line boundaries.      The SYM53C810A will not operate in a cache
                                                       alignment mode when a MMOV instruction is
Selection of Cache                                     issued and the read and write addresses are differ-
Line Size                                              ent distances from the nearest cache line bound-
                                                       ary. For example, if the read address is 0x21F and
The cache logic will select a cache line size based    the write address is 0x42F, and the cache line size
on the values for the burst size in the DMODE          is eight (8), the addresses are byte aligned, but they
register and the PCI Cache Line Size register.         are not the same distance from the nearest cache
                                                       boundary. The read address is 1 byte from the
                                                       cache boundary 0x220 and the write address is 17
                                                       bytes from the cache boundary 0x440. In this situ-
                                                       ation, the chip will not align to cache boundaries
                                                       and will operate as an SYM53C810.

3-2                                                    SYM53C810A Data Manual
                                                       PCI Functional Description
                                                                  PCI Cache Mode

Memory Write                                           Multiple Cache Transfers
and Invalidate Command
                                                           When multiple cache lines of data have been
The Memory Write and Invalidate command is                 read in during a MMOV instruction (See the
identical to the Memory Write command, except              description for the Read Multiple command),
that it additionally guarantees a minimum transfer         the SYM53C810A will issue a Write and Inval-
of one complete cache line; i.e., the master intends       idate command using the burst size necessary
to write all bytes within the addressed cache line in      to transfer all the data in one transfer. For
a single PCI transaction unless interrupted by the         example, if the cache line size is 4, and the chip
target. This command requires implementation of            read in 16 dwords of data using a Read Multi-
the PCI Cache Line Size register at address 0Ch in         ple command, the chip will switch the burst
PCI configuration space. The SYM53C810A                    size to 16, and issue a Write and Invalidate to
enables Memory Write and Invalidate cycles when            transfer all 16 dwords in one bus ownership.
bit 0 in the CTEST3 register (WRIE) and bit 4 in
the PCI Command register are set. This will cause      Latency
Memory Write and Invalidate commands to be
issued when the following conditions are met:          In accordance with the PCI specification, the
                                                       chip's latency timer will be ignored when issuing a
1. The CLSE bit, WRIE bit, and PCI Config              Write and Invalidate command such that when a
    Command register, bit 4 must be set.               latency time-out has occurred, the SYM53C810A
                                                       will continue to transfer up until a cache line
2. The cache line size register must contain a         boundary. At that point, the chip will relinquish
    legal burst size (2, 4, 8 or 16) value AND that    the bus, and finish the transfer at a later time using
    value must be less than or equal to the            another bus ownership. If the chip is transferring
    DMODE burst size.                                  multiple cache lines it will continue to transfer
                                                       until the next cache boundary is reached.
3. The chip must have enough bytes in the DMA
    FIFO to complete at least one full cache line      PCI Target Retries
    burst.
                                                       During a Write and Invalidate transfer, if the target
4. The chip must be aligned to a cache line            device issues a retry (STOP with no TRDY, indi-
    boundary.                                          cating that no data was transferred), the
                                                       SYM53C810A will relinquish the bus and imme-
When these conditions have been met, the               diately try to finish the transfer on another bus
SYM53C810A will issue a Write and Invalidate           ownership. The chip will issue another Write and
command instead of a Memory Write command              Invalidate command on the next ownership, in
during all PCI write cycles.                           accordance with the PCI specification.

                                                       PCI Target Disconnect

                                                       During a Write and Invalidate transfer, if the target
                                                       device issues a disconnect the SYM53C810A will
                                                       relinquish the bus and immediately try to finish the
                                                       transfer on another bus ownership. The chip will
                                                       not issue another Write and Invalidate command
                                                       on the next ownership.

SYM53C810A Data Manual                                 3-3
PCI Functional Description
PCI Cache Mode

Memory Read                                           4. The chip must be aligned to a cache line
Line Command                                              boundary.

This command is identical to the Memory Read          When these conditions have been met, the chip
command, except that it additionally indicates that   will issue a Read Line command instead of a
the master intends to fetch a complete cache line.    Memory Read during all PCI read cycles. Other-
This command is intended to be used with bulk         wise, it will issue a normal Memory Read com-
sequential data transfers where the memory system     mand.
and the requesting master might gain some perfor-
mance advantage by reading up to a cache line         Memory Read
boundary rather than a single memory cycle.The        Multiple Command
Read Line Mode function that exists in the previ-
ous SYM53C8XX chips has been modified in the          This command is identical to the Memory read
SYM53C810A to reflect the PCI cache line size         command except that it additionally indicates that
register specifications. The functionality of the     the master may intend to fetch more than one
Enable Read Line bit (bit 3 in DMODE) has been        cache line before disconnecting. The
modified to more resemble the Write and Invali-       SYM53C810A supports PCI Read Multiple func-
date mode in terms of conditions that must be met     tionality and will issue Read Multiple commands
before a Read Line command will be issued. How-       on the PCI bus when the Read Multiple Mode is
ever, the Read Line option will operate exactly like  enabled. This mode is enabled by setting bit 2 of
the previous SYM53C8XX chips when cache               the DMODE register (ERMP).The command will
mode has been disabled by a CLSE bit reset or         be issued when certain conditions have been met.
when certain conditions exist in the chip
(explained below).                                    If cache mode has been enabled, a Read Multiple
                                                      command will be issued on all read cycles, except
The Read Line mode is enabled by setting bit 3 in     op code fetches, when the following conditions
the DMODE register. If cache mode is disabled,        have been met:
Read Line commands will be issued on every read
data transfer, except op code fetches, as in previ-   1. The CLSE and ERMP bits must be set.
ous SYM53C8XX chips.
                                                      2. The Cache Line Size register must contain a
If cache mode has been enabled, a Read Line com-          legal burst size value (2, 4, 8 or 16) AND that
mand will be issued on all read cycles, except op         value must be less than or equal to the
code fetches, when the following conditions have          DMODE burst size.
been met:
                                                      3. The number of bytes to be transferred at the
1. The CLSE and Enable Read Line bits must be             time a cache boundary has been reached must
    set.                                                  be equal to or greater than the DMODE burst
                                                          size.
2. The Cache Line Size register must contain a
    legal burst size value (2, 4, 8 or 16) AND that   4. The chip must be aligned to a cache line
    value must be less than or equal to the               boundary.
    DMODE burst size.
                                                      When these conditions have been met, the chip
3. The number of bytes to be transferred at the       will issue a Read Multiple command instead of a
    time a cache boundary has been reached must       Memory Read during all PCI read cycles.
    be equal to or greater than a full cache line
    size.

3-4                                                   SYM53C810A Data Manual
                                                                            PCI Functional Description
                                                                                       PCI Cache Mode

Burst Size Selection                                   met. Instead, a Read Multiple command will be
                                                       issued, even though the conditions for Read Line
The Read Multiple command reads in multiple            have been met.
cache lines of data in a single bus ownership. The
number of cache lines to be read is determined by      If the Read Multiple mode is enabled and the Read
the DMODE burst size bits. In other words, the         Line mode has been disabled, Read Multiple com-
chip will switch its normal operating burst size to    mands will still be issued if the Read Multiple con-
reflect the DMODE burst size settings for the          ditions are met.
Read Multiple command. For example, if the
cache line size is 4, and the DMODE burst size is      Unsupported PCI
16, the chip will switch the current burst size from   Commands
4 to 16, and issue a Read Multiple. After the trans-
fer, the chip will then switch the burst size back to  The SYM53C810A does not respond to reserved
the normal operating burst size of 4.                  commands, special cycle, dual address cycle, or
                                                       interrupt acknowledge commands as a slave. It will
Read Multiple with Read Line Enabled                   never generate these commands as a master.

When both the Read Multiple and Read Line
modes have been enabled, the Read Line com-
mand will not be issued if the above conditions are

                            Table 3-1: PCI Bus Commands and Encoding Types

C_BE(3-0)  Command Type           Supported as Master                       Supported as Slave
                                                                            No
0000       Interrupt Acknowledge  No                                        No
0001                                                                        Yes
0010       Special Cycle          No                                        Yes
0011
0100       I/O Read Cycle         Yes                                       Yes
0101                                                                        Yes
0110       I/O Write Cycle        Yes
0111                                                                        Yes
1000       Reserved                                    n/a                  Yes
1001                                                                        No (defaults to 0110)
1010       Reserved                                    n/a                  No
1011                                                                        No (defaults to 0110)
1100       Memory Read            Yes                                       No (defaults to 0111)
1101
1110       Memory Write           Yes
1111
           Reserved                                    n/a

           Reserved                                    n/a

           Configuration Read     No

           Configuration Write    No

           Memory Read Multiple   Yes

           Dual Address Cycle     No

           Memory Read Line       Yes

           Memory Write and Invalidate Yes

SYM53C810A Data Manual                                                                             3-5
PCI Functional Description
Configuration Registers

Configuration Registers                                For detailed information, refer to the PCI Specifi-
                                                       cation.
The Configuration registers are accessible only by
system BIOS during PCI configuration cycles, and       Figure 3-1 shows the PCI configuration registers
are not available to the user at any time. No other    implemented by the SYM53C810A. Addresses
cycles, including SCRIPTS operations, can access       40h through 7Fh are not defined.
these registers.
                                                       All PCI-compliant devices, such as the
The lower 128 bytes hold configuration data while      SYM53C810A, must support the Vendor ID,
the upper 128 bytes hold the SYM53C810A oper-          Device ID, Command, and Status Registers. Sup-
ating registers, which are described in Chapter        port of other PCI-compliant registers is optional.
Five, "Operating Registers." The operating regis-      In the SYM53C810A, registers that are not sup-
ters can be accessed by SCRIPTS or the host pro-       ported are not writable and return all zeroes when
cessor.                                                read. Only those registers and bits that are cur-
                                                       rently supported by the SYM53C810A are
Note: the configuration register descriptions are      described in this chapter. For more detailed infor-
         provided for general information only, to     mation on PCI registers, please see the PCI Speci-
         indicate which PCI configuration addresses    fication.
         are supported in the SYM53C810A.

     31                                      16 15                           0

         Device ID = 0001h                             Vendor ID = 1000h        00h

                            Status                            Command           04h

                            Class Code = 010000h                 Rev ID=01h     08h

     Not Supported Header Type Latency Timer Cache Line Size 0Ch

                                    Base Address Zero (I/O)*                    10h

                                    Base Address One (Memory)**                 14h

                                    Not Supported                               18h

                                    Not Supported                               1Ch

                                    Not Supported                               20h

                                    Not Supported                               24h

                                             Reserved                           28h

                                             Reserved                           2Ch

                                             Reserved                           30h

                                             Reserved                           34h

                                             Reserved                           38h

         Max_Lat                    Min_Gnt          Interrupt Pin Interrupt Line 3Ch

                                           Figure 3-1: PCI Configuration Register Map
*I/O Base is supported
**Memory Base is supported
Note: Addresses 40h to 7Fh are not defined. All unsupported registers are not writable and will return all zeroes when read. Reserved
registers will also return zeroes when read.

3-6                                                                             SYM53C810A Data Manual
                                                        PCI Functional Description
                                                          Configuration Registers

Register 00h                                                more information on these conditions, refer to
Vendor ID                                                   the section "Memory Write and Invalidate
Read Only                                                   Command" To enable Write and Invalidate
                                                            Mode, bit 0 in the CTEST3 register (Operat-
This field identifies the manufacturer of the device.       ing registers) must also be set.
Symbios Logic Vendor ID is 1000h.
                                                        Bit 2 Enable Bus Mastering
Register 02h
Device ID                                                   This bit controls the SYM53C810A's ability to
Read Only                                                   act as a master on the PCI bus. A value of zero
                                                            disables the device from generating PCI bus
This field identifies the particular device. The            master accesses. A value of one allows the
SYM53C810A device ID is 0001h.                              SYM53C810A to behave as a bus master.
                                                            The SYM53C810A must be a bus master in
Register 04h                                                order to fetch SCRIPTS instructions and
Command                                                     transfer data.
Read/Write
                                                        Bit 1 Enable Memory Space
The Command Register, illustrated in Figure 3-2,
provides coarse control over a device's ability to          This bit controls the SYM53C810A's response
generate and respond to PCI cycles.When a zero is           to memory space accesses. A value of zero dis-
written to this register, the SYM53C810A is logi-           ables the device response. A value of one allows
cally disconnected from the PCI bus for all                 the SYM53C810A to respond to memory
accesses except configuration accesses.                     space accesses at the address specified by Base
                                                            Address One .
In the SYM53C810A, bits 3, 5, 7, and 9 are not
implemented. Bits 10 through 15 are reserved.           Bit 0 Enable I/O Space

Bits 15-10 Reserved                                         This bit controls the SYM53C810A's response
Bit 8 SERR/ Enable                                          to I/O space accesses. A value of zero disables
                                                            the response. A value of one allows the
    This bit enables the SERR/ driver. SERR/ is             SYM53C810A to respond to I/O space
    disabled when this bit is clear. The default            accesses at the address specified in Base
    value of this bit is zero. This bit and bit 6 must      Address Zero.
    be set to report address parity errors.

Bit 6 Enable Parity Error Response
    This bit allows the SYM53C810A to detect
    parity errors on the PCI bus and report these
    errors to the system. Only data parity checking
    is enabled. The SYM53C810A always gener-
    ates parity for the PCI bus.

Bit 4 Write and Invalidate Mode
    This bit, when set, will cause Memory Write
    and Invalidate cycles to be issued on the PCI
    bus after certain conditions have been met. For

SYM53C810A Data Manual                                  3-7
PCI Functional Description
Configuration Registers

                                                   15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0

                                               Reserved
                                              Reserved
                                             Reserved
                                            Reserved
                                           Reserved
                                          Reserved
                               Not Implemented
                                    SERR/ Enable
                              Not Implemented
                    Enable Parity Response
                         Not Implemented
          Write and Invalidate Mode
                  Not Implemented

        Enable Bus Mastering
     Enable Memory Space

        Enable I/O Space

                            Figure 3-2: Command Register Layout

Register 06h                                           Bit 14 Signaled System Error
Status
Read/Write                                                 This bit is set whenever a device asserts the
                                                           SERR/ signal.
The Status Register, illustrated in Figure 3-3, is
used to record status information for PCI bus-         Bit 13 Master Abort (from Master)
related events.
                                                           This bit should be set by a master device when-
In the SYM53C810A, bits 0 through 4 are                    ever its transaction (except for Special Cycle) is
reserved and bits 5, 6, 7, and 11 are not imple-           terminated with master-abort. All master
mented by the SYM53C810A.                                  devices should implement this bit.

Reads to this register behave normally. Writes are     Bit 12 Received Target Abort (from
slightly different in that bits can be reset, but not      Master)
set. A bit is reset whenever the register is written,
and the data in the corresponding bit location is a        This bit should be set by a master device when-
one. For instance, to clear bit 15 and not affect any      ever its transaction is terminated with a target
other bits, write the value 8000h to the register.         abort. All master devices should implement
                                                           this bit.
Bit 15 Detected Parity Error (from Slave)

    This bit will be set by the SYM53C810A
    whenever it detects a data parity error, even if
    parity error handling is disabled.

3-8                                                              SYM53C810A Data Manual
                                                    PCI Functional Description
                                                      Configuration Registers

Bits 10-9 DEVSEL/ Timing                            Bit 8 Data Parity Reported

    These bits encode the timing of DEVSEL/.            This bit is set when the following three condi-
    These are encoded as 00b for fast, 01b for          tions are met: 1) The bus agent asserted
    medium, 10b for slow, and 11b reserved.             PERR/ itself or observed PERR/ asserted; 2)
    These bits are read only and should indicate        The agent setting this bit acted as the bus mas-
    the slowest time that a device asserts DEVSEL/      ter for the operation in which the error
    for any bus command except Configuration            occurred; and 3) The Parity Error Response bit
    Read and Configuration Write. The                   in the Command register is set.
    SYM53C810A supports 01b.
                                                    Bits 7-6 Not Implemented

                                                    Bits 5-0 Reserved

                                                15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0

       Detected Parity Error (from Slave)
                      Signaled System Error

Received Master Abort (from Master)
Received Target Abort (from Master)

                          Not Implemented

                         DEVSEL timing

          00 = fast, 01 = medium, 10 = slow

                   Data Parity Reported
                      Not Implemented

                    Not Implemented
                Not Implemented

                       Reserved
                   Reserved
             Reserved
          Reserved
       Reserved

                                     Figure 3-3: Status Register Layout

SYM53C810A Data Manual                                                                3-9
PCI Functional Description
Configuration Registers

Register 08h                                            Register 0Dh
Revision ID                                             Latency Timer
Read Only                                               Read/Write

This register specifies device and revision identifi-   The Latency Timer register specifies, in units of
ers. In the SYM53C810A, the upper nibble is             PCI bus clocks, the value of the Latency Timer for
0001b. The lower nibble represents the current          this PCI bus master. The SYM53C810A supports
revision level of the device. It should have the same   this timer. All eight bits are writable, allowing
value as the Chip Revision Level bits in the            latency values of 0-255 PCI clocks. Use the follow-
CTEST3 register.                                        ing equation to calculate an optimum latency value
                                                        for the SYM53C810A:
Register 09h
Class Code                                              Latency = 2 + (Burst Size * (typical wait states +1)).
Read Only
                                                        Values greater than optimum are also acceptable.
This register is used to identify the generic func-
tion of the device. The upper byte of this register is
a base class code, the middle byte is a subclass
code, and the lower byte identifies a specific regis-
ter-level programming interface. The value of this
register is 010000h, which indicates a SCSI con-
troller.

Register 0Ch
Cache Line Size
Read/Write

This register specifies the system cache line size in
units of 32-bit words. Cache mode is enabled and
disabled by the Cache Line Size Enable (CLSE)
bit, bit 7 in the DCNTL register. Setting this bit
causes the SYM53C810A to align to cache line
boundaries before allowing any bursting, except
during MMOVs in which the read and write
addresses are Burst Size boundary misaligned. For
more information, see "Support for PCI Cache
Line Size Register" on page 3-2.

3-10                                                    SYM53C810A Data Manual
                                                        PCI Functional Description
                                                          Configuration Registers

Register 0Eh                                            Register 3Dh
Header Type                                             Interrupt Pin
Read Only                                               Read Only

This register identifies the layout of bytes 10h        This register tells which interrupt pin the device
through 3Fh in configuration space and also             uses. Its value is set to 01h, for the INTA/ signal.
whether or not the device contains multiple func-
tions. The value of this register is 00h.               Register 3Eh
                                                        Min_Gnt
Register 10h                                            Read Only
Base Address Zero (I/O)
Read/Write                                              Register 3Fh
                                                        Max_Lat
This 32-bit register has bit zero hardwired to one.     Read Only
Bit 1 is reserved and must return a zero on all
reads, and the other bits are used to map the           These registers are used to specify the desired set-
device into I/O space.                                  tings for Latency Timer values. Min_Gnt is used to
                                                        specify how long a burst period the device needs.
Register 14h                                            Max_Lat is used to specify how often the device
Base Address One (Memory)                               needs to gain access to the PCI bus. The value
Read/Write                                              specified in these registers is in units of 0.25
                                                        microseconds. Values of zero indicate that the
This register has bit 0 hardwired to zero. For          device has no major requirements for the settings
detailed information on the operation of this regis-    of Latency Timers. The SYM53C810A sets the
ter, refer to the PCI Specification.                    Min_Gnt register to 11h and the Max_Lat register
                                                        to 40h.
Register 3Ch
Interrupt Line
Read/Write

This register is used to communicate interrupt line
routing information. POST software will write the
routing information into this register as it initiates
and configures the system. The value in this regis-
ter tells which input of the system interrupt con-
troller(s) has been connected to the device's
interrupt pin.Values in this register are specified by
system architecture.

SYM53C810A Data Manual                                  3-11
PCI Functional Description
Configuration Registers

3-12                        SYM53C810A Data Manual
                                                                                                                                Signal Descriptions

Chapter 4

Signal Descriptions

This chapter presents the SYM53C810A pin configuration and signal definitions using tables and
illustrations. Figure 4-1 is the pin diagram and Figure 4-2 is a functional signal grouping. The pin def-
initions are presented in Table 4-1 through Table 4-8. The SYM53C810A is pin-for-pin compatible
with the SYM53C810.

                                      AD22
                                         Vss-I
                                            AD23
                                               IDSEL
                                                  C_BE3/
                                                      AD24
                                                         AD25
                                                            Vss-I
                                                               AD26
                                                                   AD27
                                                                      V DD-I
                                                                         AD28
                                                                            AD29
                                                                                Vss-I
                                                                                   AD30
                                                                                      AD31
                                                                                         VDD -C
                                                                                             REQ/
                                                                                                GNT/
                                                                                                   Vss-C

                            AD21 1    99 97 95 93 91 89 87 85 83 81                                            80 CLK
                            AD20 2
                            VDD-I 3            SYM53C810A                                                      79 RST/
                            AD19 4              100-Pin QFP
                           VSS-I 5                                                                             78 SERR/
                            AD18 6
                            AD17 7                                                                             77 V DD -S
                            AD16 8
                            Vss-I 9                                                                            76 SD0/
                         C_BE2/ 10
                         FRAME/ 11                                                                             75 SD1/
                           IRDY/ 12
                            Vss-I 13                                                                           74 SD2/
                           TRDY/ 14                                                                            73 Vss-S
                        DEVSEL/ 15                                                                             72 SD3/
                          VDD-I 16                                                                             71 SD4/
                           STOP/ 17                                                                            70 SD5/
                                                                                                               69 SD6/
                            VSS-I 18                                                                           68 Vss-S
                                                                                                               67 SD7/
                           PERR/ 19                                                                            66 SDP/
                                                                                                               65 SATN/
                             PAR 20                                                                            64 SBSY/
                         C_BE1/ 21                                                                             63 Vss-S
                                                                                                               62 SACK/
                            VSS-I 22                                                                           61 SRST/
                            AD15 23                                                                            60 SMSG/
                            AD14 24                                                                            59 SSEL/
                            AD13 25                                                                            58 Vss-S
                            VSS-I 26                                                                           57 SCD/
                            AD12 27                                                                            56 SREQ/
                            VDD-I 28                                                                           55 SIO/
                            AD11 29                                                                            54 V DD -S
                            AD10 30                                                                            53 MAC/_TESTOUT
                                                                                                               52 TESTIN
                                                                                                               51 SCLK

                                      32 34 36 38 40 42 44 46 48 50

                                      AD9
                                         Vss-I
                                            AD8
                                               C_BE0/
                                                  AD7
                                                      AD6
                                                         Vss-I
                                                            AD5
                                                               AD4
                                                                   VDD-I
                                                                      AD3
                                                                         AD2
                                                                            Vss-I
                                                                                AD1
                                                                                   AD0
                                                                                      VDD -C
                                                                                         IRQ/
                                                                                             GPIO0_FETCH/
                                                                                                GPIO1_MASTER/
                                                                                                   VSS -C

                                               Figure 4-1: SYM53C810A Pin Diagram

The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capac-
itor values between 0.01 and 0.1µF should provide adequate noise isolation. Because of the number of high current drivers on the
SYM53C810A, a multi-layer PC board with power and ground planes is required.

SYM53C810A Data Manual                                                                                                                4-1
Signal Descriptions

The PCI/SCSI pin definitions are organized into
the following functional groups: Power and
Ground, System, Address/Data, Interface Control,
Arbitration, Error Reporting, SCSI, and Optional
Interface. A slash (/) at the end of the signal name
indicates that the active state occurs when the sig-
nal is at a low voltage. When the slash is absent, the
signal is active at a high voltage.

There are four signal type definitions:

I          Input, a standard input-only signal

O          Totem Pole Output, a standard out-

           put driver

T/S        Tri-State, a bi-directional, tri-state

           input/output pin

S/T/S      Sustained Tri-state, an active low
           tri-state signal owned and driven by
           one and only one agent at a time

                                     Table 4-1: Power and Ground Pins

   Symbol            Pin No.             Description

   VSS-I             5, 9, 13, 18, 22, 26, Power supplies to the PCI I/O pins
                     32, 37, 43, 87, 93, 99

   VDD-I*            3, 16, 28, 40, 90   Power supplies to the PCI I/O pins

   VSS-S             58, 63, 68, 73      Power supplies to the SCSI bus I/O pins

   VDD-S             54, 77              Power supplies to the SCSI bus I/O pins

   VSS-C             50, 81              Power supplies to the internal logic core

   VDD-C             46, 84              Power supplies to the internal logic core

   *These pins can accept a VDD source of 3.3 or 5 Volts. All other VDD pins must be supplied 5 Volts.

4-2                                                                                                     SYM53C810A Data Manual
                                                                Signal Descriptions

          System        CLK         SCLK                        SCSI
Address and Data        RST        SD7-0                        Additional Interface
                        AD31-0
 Interface Control                   SDP
       Arbitration
                                  SCTRL/
  Error Reporting
                        C_BE/3-0

                        PAR

                        FRAME/
                        TRDY/

                        IRDY/       GPIO0_FETCH/
                        STOP/
                                  GPIO1_MASTER/
                        DEVSEL/    MAC/_TESTOUT
                        IDSEL
                        REQ/                    IRQ/
                        GNT/                TESTIN/

                        SERR/
                        PERR/

                        Figure 4-2: Functional Signal Grouping

SYM53C810A Data Manual                                                                4-3
Signal Descriptions

Symbol    Pin No.    Type   Table 4-2: System Pins

CLK       80         I            Description

RST/      79         I            Clock. Clock provides timing for all transactions on the PCI bus
                                  and is an input to every PCI device. All other PCI signals are
                                  sampled on the rising edge of CLK, and other timing parame-
                                  ters are defined with respect to this edge. This clock can option-
                                  ally be used as the SCSI core clock; however, the
                                  SYM53C810A will not achieve fast SCSI transfer rates.

                                  Reset. Reset forces the PCI sequencer of each device to a known
                                  state. All t/s and s/t/s signals are forced to a high impedance
                                  state, and all internal logic is reset. The RST/ input is synchro-
                                  nized internally to the rising edge of CLK.The CLK input must
                                  be active while RST/ is active to properly reset the device.

Symbol    Pin No.    Type   Table 4-3: Address and Data Pins

AD(31-0)  85, 86, 88, T/S               Description
          89, 91, 92,
          94, 95, 98,                   Address/Data. Physical dword address and data are multiplexed
          100, 1, 2, 4,                 on the same PCI pins. During the first clock of a transaction,
          6, 7, 8, 23,                  AD(31-0) contain a physical byte address. During subsequent
          24, 25, 27,                   clocks, AD(31-0) contain data. A bus transaction consists of an
          29, 30, 31,                   address phase, followed by one or more data phases. PCI sup-
          33, 35, 36,                   ports both read and write bursts. AD(7-0) define the least sig-
          38, 39, 41,                   nificant byte, and AD(31-24) define the most significant byte.
          42, 44, 45
                                        Command/Byte Enable. Bus command and byte enables are mul-
C_BE/(3-0) 96, 10, 21, T/S              tiplexed on the same PCI pins. During the address phase of a
                    34                  transaction, C_BE(3-0)/ define the bus command. During the
                                        data phase, C_BE(3-0)/ are used as byte enables. The byte
PAR       20         T/S                enables determine which byte lanes carry meaningful data.
                                        C_BE/(0) applies to byte lane 0, and C_BE/(3) to byte lane 3.
                                        Parity. Parity is the even parity bit that protects the AD(31-0)
                                        and C_BE/(3-0) lines. During address phase, both the address
                                        and command bits are covered. During data phase, both data
                                        and byte enables are covered.

4-4                         SYM53C810A Data Manual
                               Signal Descriptions

Symbol  Pin No.         Type   Table 4-4: Interface Control Pins
FRAME/  11              S/T/S
                        S/T/S         Description
TRDY/   14
                        S/T/S         Cycle Frame. Cycle Frame is driven by the current master to indi-
IRDY/   12                            cate the beginning and duration of an access. FRAME/ is asserted
                        S/T/S         to indicate a bus transaction is beginning. While FRAME/ is
STOP/   17              S/T/S         asserted, data transfers continue. When FRAME/ is deasserted, the
                        I             transaction is in the final data phase or the bus is idle.
DEVSEL/ 15
                                      Target Ready.Target Ready indicates the target agent's (selected
IDSEL   97                            device's) ability to complete the current data phase of the transac-
                                      tion. TRDY/ is used with IRDY/. A data phase is completed on any
                                      clock when both TRDY/ and IRDY/ are sampled asserted. During a
                                      read, TRDY/ indicates that valid data is present on AD(31-0). Dur-
                                      ing a write, it indicates the target is prepared to accept data. Wait
                                      cycles are inserted until both IRDY/ and TRDY/ are asserted
                                      together.

                                      Initiator Ready. Initiator Ready indicates the initiating agent's (bus
                                      master's) ability to complete the current data phase of the transac-
                                      tion. This signal is used with TRDY/. A data phase is completed on
                                      any clock when both IRDY/ and TRDY/ are sampled asserted. Dur-
                                      ing a write, IRDY/ indicates that valid data is present on AD(31-0).
                                      During a read, it indicates the master is prepared to accept data.
                                      Wait cycles are inserted until both IRDY/ and TRDY/ are asserted
                                      together.

                                      Stop. Stop indicates that the selected target is requesting the master
                                      to stop the current transaction.

                                      Device Select. Device Select indicates that the driving device has
                                      decoded its address as the target of the current access. As an input,
                                      it indicates to a master whether any device on the bus has been
                                      selected.

                                      Initialization Device Select. Initialization Device Select is used as a
                                      chip select in place of the upper 24 address lines during configura-
                                      tion read and write transactions.

Symbol  Pin No.         Type   Table 4-5: Arbitration Pins

REQ/    83              O          Description

GNT/    82              I          Request. Request indicates to the arbiter that this agent desires to
                                   use the PCI bus.This is a point-to-point signal. Every master has its
                                   own REQ/.
                                   Grant. Grant indicates to the agent that access to the PCI bus has
                                   been granted. This is a point-to-point signal. Every master has its
                                   own GNT/.

SYM53C810A Data Manual         4-5
Signal Descriptions

Symbol    Pin No.             Type          Table 4-6: Error Reporting Pins
PERR/     19                  S/T/S
                                                   Description
SERR/     78                  O
                                                   Parity Error. Parity Error may be pulsed active by an agent that
                                                   detects a parity error. PERR/ can be used by any agent to signal
                                                   data corruptions. However, on detection of a PERR/ pulse, the cen-
                                                   tral resource may generate a non-maskable interrupt to the host
                                                   CPU, which often implies the system will be unable to continue
                                                   operation once error processing is complete.

                                                   System Error.This open drain output pin is used to report address
                                                   parity errors.

                                              Table 4-7: SCSI Pins

Symbol               Pin No.             Type Description
SCLK
                     51                  I    SCSI Clock. SCLK is used to derive all SCSI-related timings. The
SD(7-0),                                      speed of this clock is determined by the application's requirements;
SDP                                           in some applications SCLK may be sourced internally from the
SCTRL/                                        PCI bus clock (CLK). If SCLK is internally sourced, then the
                                              SCLK pin should be tied low.

                     67, 69, 70,71,72, I/O    SCSI Data. SCSI Data includes the following data lines and parity
                     74, 75, 76, 66           signals: SD(7-0) (8-bit SCSI data bus), and SDP (SCSI data par-
                                              ity bit).

                     57, 55, 60, 56,     I/O  SCSI Control. SCSI Control includes the following signals:

                     62, 64, 65, 61, 59       SCD/ SCSI phase line, command/data

                                              SIO/         SCSI phase line, input/output

                                              SMSG/ SCSI phase line, message

                                              SREQ/ Data handshake signal from target device

                                              SACK/ Data handshake signal from initiator device

                                              SBSY/ SCSI bus arbitration signal, busy

                                              SATN/ SCSI Attention, the initiator is requesting a message

                                                           out phase

                                              SRST/ SCSI bus reset

                                              SSEL/ SCSI bus arbitration signal, select device

4-6                                                                                       SYM53C810A Data Manual
                                                              Signal Descriptions

                        Table 4-8: Additional Interface Pins

Symbol   Pin No.        Type Description
TESTIN/  52
                        I  Test In.When this pin is driven low, the SYM53C810A connects all

                           inputs and outputs to an "AND tree." The SCSI control signals

                           and data lines are not connected to the "AND tree." The output of

                           the "AND tree" is connected to the Test Out pin. This allows man-

                           ufacturers to verify chip connectivity and determine exactly which

                           pins are not properly attached. When the TESTIN pin is driven

                           low, internal pull-ups are enabled on all input, output, and bidirec-

                           tional pins, all outputs and bidirectional signals will be tri-stated,

                           and the MAC/_TESTOUT pin will be enabled. Connectivity can

                           be tested by driving one of the SYM53C810A pins low. The MAC/

                           _TESTOUT pin should respond by also driving low.

GPIO0_   48             I/O General Purpose I/O pin. Optionally, when driven low, indicates that
                                  the next bus request will be for an op code fetch. This pin powers
FETCH/                            up as a general purpose input.

                           This pin has two specific purposes in the Symbios Logic SDMS
                           software. SDMS uses it to toggle SCSI device LEDs, turning on
                           the LED whenever the SYM53C810A is on the SCSI bus. SDMS
                           drives this pin low to turn on the LED, or drives it high to turn off
                           the LED. This signal can also be used as data I/O for serial
                           EEPROM access. In this case it is used with the GPIO0 pin, which
                           serves as a clock.The pin can be controlled from PCI configuration
                           register 35h or observed from the GPREG operating register, at
                           address 07h.

GPIO1_   49             I/O General Purpose I/O pin. Optionally, when driven low, indicates that
                                  the SYM53C810A is bus master. This pin powers up as a general
MASTER/                           purpose input.

                           Symbios Logic SDMS software supports use of this signal in serial
                           EPROM applications, when enabled, in combination with the
                           GPIO0 pin. When this signal is used as a clock for serial EEPROM
                           access, the GPIO1 pin serves as data, and the pin is controlled
                           from PCI configuration register 35h.

MAC_     53             T/S Memory Access Control/Test Out. This pin can be programmed to
                                  indicate local or system memory accesses (non-PCI applications).
TESTOUT                           It is also used to test the connectivity of the SYM53C810A signals
                                  using an "AND tree" scheme. The MAC/_TESTOUT pin is only
                                  driven as the Test Out function when the TESTIN/ pin is driven
                                  low.

IRQ/     47             O Interrupt. This signal, when asserted low, indicates that an inter-
                                  rupting condition has occurred and that service is required from
                                  the host CPU. The output drive of this pin is programmed as either
                                  open drain with an internal weak pull-up or, optionally, as a totem
                                  pole driver. Refer to the description of DCNTL Register, bit 3, for
                                  additional information.

SYM53C810A Data Manual                                                                             4-7
Signal Descriptions

4-8                  SYM53C810A Data Manual
                                                                                  Operating Registers

Chapter 5

Operating Registers

This section contains descriptions of all               Note: the only register that the host CPU can
SYM53C810A operating registers. Table 5-1 sum-                   access while the SYM53C810A is
marizes the SYM53C810A operating register set.                   executing SCRIPTS is the ISTAT register;
Figure 5-1, the register map, lists registers by oper-           attempts to access other registers will
ating and configuration addresses. The terms "set"               interfere with the operation of the chip.
and "assert" are used to refer to bits that are pro-             However, all operating registers are
grammed to a binary one. Similarly, the terms                    accessible with SCRIPTS. All read data is
"deassert," "clear" and "reset" are used to refer to             synchronized and stable when presented to
bits that are programmed to a binary zero. Any bits              the PCI bus.
marked as reserved should always be written to ze-
ro; mask all information read from them. Reserved       Note: the SYM53C810A cannot fetch SCRIPTS
bit functions may be changed at any time. Unless                 instructions from the operating register
otherwise indicated, all bits in registers are active            space. Instructions must be fetched from
high, that is, the feature is enabled by setting the             system memory.
bit. The bottom row of every register diagram
shows the default register values, which are enabled
after the chip is powered on or reset.

                        Table 5-1: Operating Register Addresses and Descriptions

Memory   PCI                       Label                Description
or I/O   Configuration Read/Write
Address  Address
Offset
         80             R/W        SCNTL0               SCSI Control 0
00                                                      SCSI Control 1
01       81             R/W        SCNTL1               SCSI Control 2
02                                                      SCSI Control 3
03       82             R/W        SCNTL2               SCSI Chip ID
04                                                      SCSI Transfer
05       83             R/W        SCNTL3               SCSI Destination ID
06                                                      General Purpose Bits
07       84             R/W        SCID                 SCSI First Byte Received
08                                                      SCSI Output Control Latch
09       85             R/W        SXFER                SCSI Selector ID
0A
         86             R/W        SDID

         87             R/W        GPREG

         88             R/W        SFBR

         89             R/W        SOCL

         8A             R          SSID

SYM53C810A Data Manual                                                             5-1
Operating Registers

         Table 5-1: Operating Register Addresses and Descriptions (Continued)

Memory   PCI                       Label     Description
or I/O   Configuration Read/Write
Address  Address                   SBCL      SCSI Bus Control Lines
Offset                             DSTAT     DMA Status
         8B          R/W           SSTAT0    SCSI Status 0
0B       8C          R             SSTAT1    SCSI Status 1
0C       8D          R             SSTAT2    SCSI Status 2
0D       8E          R             DSA       Data Structure Address
0E       8F          R             ISTAT     Interrupt Status
0F       90-93       R/W           Reserved
10-13    94          R/W           CTEST0    Reserved
14       95-97                     CTEST1    Chip Test 1
15-17    98          R/W           CTEST2    Chip Test 2
18       99          R/W           CTEST3    Chip Test 3
19       9A          R             TEMP      Temporary Stack
1A       9B          R             DFIFO     DMA FIFO
1B       9C-9F       R/W           CTEST4    Chip Test 4
1C-1F    A0          R/W           CTEST5    Chip Text 5
20       A1          R/W           CTEST6    Chip Test 6
21       A2          R/W           DBC       DMA Byte Counter
22       A3          R/W           DCMD      DMA Command
23       A4-A6       R/W           DNAD      DMA Next Address for Data
24-26    A7          R/W           DSP       DMA SCRIPTS Pointer
27       A8-AB       R/W           DSPS      DMA SCRIPTS Pointer Save
28-2B    AC-AF       R/W           SCRATCHA  General Purpose Scratch Pad A
2C-2F    B0-B3       R/W           DMODE     DMA Mode
30-33    B4-B7       R/W           DIEN      DMA Interrupt Enable
34-37    B8          R/W           SBR       Scratch Byte Register
38       B9          R/W           DCNTL     DMA Control
39       BA          R/W           ADDER     Sum output of internal adder
3A       BB          R/W           SIEN0     SCSI Interrupt Enable 0
3B       BC-BF       R             SIEN1     SCSI Interrupt Enable 1
3C-3F    C0          R/W           SIST0     SCSI Interrupt Status 0
40       C1          R/W           SIST1     SCSI Interrupt Status 1
41       C2          R             SLPAR     SCSI Longitudinal Parity
42       C3          R
43       C4          R/W
44

5-2                                          SYM53C810A Data Manual
                                                                               Operating Registers

         Table 5-1: Operating Register Addresses and Descriptions (Continued)

Memory   PCI                       Label     Description
or I/O   Configuration Read/Write
Address  Address                   Reserved  Memory Access Control
Offset                             MACNTL    General Purpose Control
         C5             R/W        GPCNTL    SCSI Timer 0
45       C6             R/W        STIME0    SCSI Timer 1
46       C7             R/W        STIME1    Response ID
47       C8             R/W        RESPID
48       C9             R/W        Reserved  SCSI Test 0
49       CA                        STEST0    SCSI Test 1
4A       CB             R          STEST1    SCSI Test 2
4B       CC             R          STEST2    SCSI Test 3
4C       CD             R/W        STEST3    SCSI Input Data Latch
4D       CE             R/W        SIDL
4E       CF             R          Reserved  SCSI Output Data Latch
4F       D0                        SODL
50       D1-D3          R/W        Reserved  SCSI Bus Data Lines
51-53    D4                        SBDL
54       D5-D7          R          Reserved  General Purpose Scratch Pad B
55-57    D8                        SCRATCHB
58       D9-DB          R/W
59-5B    DC-DF
5C-5F

SYM53C810A Data Manual                                                         5-3
Operating Registers

       SCNTL3        SCNTL2           SCNTL1         SCNTL0       Mem I/O  Config
       GPREG                                            SCID
         SBCL        SDID             SXFER             SFBR         00      80
       SSTAT2                                                        04      84
                     SSID              SOCL           DSTAT          08      88
       CTEST3                                                        0C     8C
       CTEST6        SSTAT1           SSTAT0           ISTAT         10      90
        DCMD                                       RESERVED          14      94
                               DSA                                   18      98
       DCNTL                                          DFIFO          1C     9C
         SIST1       RESERVED                                        20     A0
                                                     DMODE           24     A4
      GPCNTL         CTEST2           CTEST1                         28     A8
     RESERVED                                          SIEN0         2C     AC
                               TEMP                   SLPAR          30     B0
       STEST3                                        STIME0          34     B4
                     CTEST5           CTEST4         STEST0          38     B8
                                               SIDL                  3C     BC
                                       DBC     SODL                  40     C0
                                               SBDL                  44     C4
                               DNAD                                  48     C8
                                                                     4C     CC
                               DSP                                   50     D0
                                                                     54     D4
                               DSPS                                  58     D8
                                                                     5C     DC
                            SCRATCH A

                     SBR               DIEN

                               ADDER

                     SIST0             SIEN1

                     MACNTL          RESERVED

                     RESPID           STIME1

                     STEST2           STEST1

                     RESERVED

                     RESERVED

                     RESERVED

                            SCRATCH B

                     Figure 5-1: SYM53C810A Register Address Map

5-4                                                               SYM53C810A Data Manual
                                                       Operating Registers

Register 00 (80)                                       Full Arbitration, Selection/Reselection
SCSI Control Zero (SCNTL0)
Read/Write                                                 1. The SYM53C810A waits for a bus free
                                                                condition.
ARB1 ARB0 START WATN EPC      RES  AAP  TRG
                                                           2. It asserts SBSY/ and its SCSI ID (stored in
7     6     5           4  3  2    1    0                       the SCID register) onto the SCSI bus.

Default>>>                                                 3. If the SSEL/ signal is asserted by another
                                                                SCSI device or if the SYM53C810A
1     1     0           0  0  X    0    0                       detects a higher priority ID, the
                                                                SYM53C810A will deassert BSY, deassert
Bit 7 ARB1 (Arbitration mode bit 1)                             its ID, and wait until the next bus free state
                                                                to try arbitration again.
Bit 6 ARB0 (Arbitration mode bit 0)
                                                           4. The SYM53C810A repeats arbitration
ARB1  ARB0  Arbitration Mode                                    until it wins control of the SCSI bus. When
0     0     Simple arbitration                                  it has won, the Won Arbitration bit is set in
0     1     Reserved                                            the SSTAT0 register, bit 2.
1     0     Reserved
1     1     Full arbitration, selection/reselection        5. The SYM53C810A performs selection by
                                                                asserting the following onto the SCSI bus:
Simple Arbitration                                              SSEL/, the target's ID (stored in the SDID
                                                                register), and the SYM53C810A's ID
    1. The SYM53C810A waits for a bus free                      (stored in the SCID register).
         condition to occur.
                                                           6. After a selection is complete, the Function
    2. It asserts SBSY/ and its SCSI ID                         Complete bit is set in the SIST0 register,
         (contained in the SCID register) onto the              bit 6.
         SCSI bus. If the SSEL/ signal is asserted by
         another SCSI device, the SYM53C810A               7. If a selection time-out occurs, the Selection
         will deassert SBSY/, deassert its ID and set           Time-Out bit is set in the SIST1 register,
         the Lost Arbitration bit (bit 3) in the                bit 2.
         SSTAT0 register.
                                                       Bit 5 START (Start sequence)
    3. After an arbitration delay, the CPU should          When this bit is set, the SYM53C810A will
         read the SBDL register to check if a higher       start the arbitration sequence indicated by the
         priority SCSI ID is present. If no higher         Arbitration Mode bits. The Start Sequence bit
         priority ID bit is set, and the Lost              is accessed directly in low-level mode; during
         Arbitration bit is not set, the                   SCSI SCRIPTS operations, this bit is con-
         SYM53C810A has won arbitration.                   trolled by the SCRIPTS processor. An arbitra-
                                                           tion sequence should not be started if the
    4. Once the SYM53C810A has won                         connected (CON) bit in the SCNTL1 register,
         arbitration, SSEL/ must be asserted via the       bit 4, indicates that the SYM53C810A is
         SOCL for a bus clear plus a bus settle delay      already connected to the SCSI bus. This bit is
         (1.2 µs) before a low level selection can be      automatically cleared when the arbitration
         performed.                                        sequence is complete. If a sequence is aborted,
                                                           bit 4 in the SCNTL1 register should be
                                                           checked to verify that the SYM53C810A did
                                                           not connect to the SCSI bus.

SYM53C810A Data Manual                                 5-5
Operating Registers

Bit 4 WATN (Select with SATN/ on a start                   If the Assert SATN/ on Parity Error bit is
             sequence)                                     cleared or the Enable Parity Checking bit is
                                                           cleared, SATN/ will not be automatically
    When this bit is set and the SYM53C810A is             asserted on the SCSI bus when a parity error is
    in initiator mode, the SATN/ signal will be            received.
    asserted during SYM53C810A selection of a
    SCSI target device. This is to inform the target   Bit 0 TRG (Target role)
    that the SYM53C810A has a message to send.             This bit determines the default operating role
    If a selection time-out occurs while attempting        of the SYM53C810A. The user must manually
    to select a target device, SATN/ will be deas-         set target or initiator role. This can be done
    serted at the same time SSEL/ is deasserted.           using the SCRIPTS language (SET TARGET
    When this bit is clear, the SATN/ signal will          or CLEAR TARGET). When this bit is set, the
    not be asserted during selection. When execut-         chip is a target device by default. When this bit
    ing SCSI SCRIPTS, this bit is controlled by            is cleared, the SYM53C810A is an initiator
    the SCRIPTS processor, but it may be set               device by default.
    manually in low level mode.
                                                                                CAUTION:
Bit 3 EPC (Enable parity checking)
    When this bit is set, the SCSI data bus is         Writing this bit while not connected may cause the
    checked for odd parity when data is received       loss of a selection or reselection due to the chang-
    from the SCSI bus in either initiator or target    ing of target or initiator roles.
    mode. If a parity error is detected, bit 0 of the
    SIST0 register is set and an interrupt may be
    generated.

    If the SYM53C810A is operating in initiator
    mode and a parity error is detected, SATN/
    can optionally be asserted, but the transfer
    continues until the target changes phase. When
    this bit is cleared, parity errors are not
    reported.

Bit 2 Reserved

Bit 1 AAP (Assert SATN/ on parity error)
    When this bit is set, the SYM53C810A auto-
    matically asserts the SATN/ signal upon detec-
    tion of a parity error. SATN/ is only asserted in
    initiator mode. The SATN/ signal is asserted
    before deasserting SACK/ during the byte
    transfer with the parity error. The Enable Par-
    ity Checking bit must also be set for the
    SYM53C810A to assert SATN/ in this man-
    ner. A parity error is detected on data received
    from the SCSI bus.

5-6                                                    SYM53C810A Data Manual
                                                       Operating Registers

Register 01 (81)                                           between internal core cells. During synchro-
SCSI Control One (SCNTL1)                                  nous operation, the SYM53C810A transfers
Read/Write                                                 data until there are no outstanding synchro-
                                                           nous offsets. If the SYM53C810A is receiving
EXC  ADB    DHP         CON  RST AESP IARB  SST            data, any data residing in the DMA FIFO is
                                                           sent to memory before halting.
7    6      5           4    3  2  1        0
                                                           When this bit is set, the SYM53C810A does
Default>>>                                                 not halt the SCSI transfer when SATN/ or a
                                                           parity error is received.
0    0      0           0    0  0  0        0
                                                       Bit 4 CON (Connected)
Bit 7 EXC (Extra clock cycle of data                       This bit is automatically set any time the
             setup)                                        SYM53C810A is connected to the SCSI bus
                                                           as an initiator or as a target. It is set after the
    When this bit is set, an extra clock period of         SYM53C810A successfully completes arbitra-
    data setup is added to each SCSI data send             tion or when it has responded to a bus initiated
    transfer. The extra data setup time can provide        selection or reselection. This bit is also set after
    additional system design margin, though it will        the chip wins simple arbitration when operat-
    affect the SCSI transfer rates. Clearing this bit      ing in low level mode. When this bit is clear,
    disables the extra clock cycle of data setup           the SYM53C810A is not connected to the
    time. Setting this bit only affects SCSI send          SCSI bus.
    operations.
                                                           The CPU can force a connected or discon-
Bit 6 ADB (Assert SCSI data bus)                           nected condition by setting or clearing this bit.
    When this bit is set, the SYM53C810A drives            This feature would be used primarily during
    the contents of the SCSI Output Data Latch             loopback mode.
    Register (SODL) onto the SCSI data bus.
    When the SYM53C810A is an initiator, the           Bit 3 RST (Assert SCSI RST/ signal)
    SCSI I/O signal must be inactive to assert the         Setting this bit asserts the SRST/ signal. The
    SODL contents onto the SCSI bus. When the              SRST/ output remains asserted until this bit is
    SYM53C810A is a target, the SCSI I/O signal            cleared. The 25 µs minimum assertion time
    must be active for the SODL contents to be             defined in the SCSI specification must be
    asserted onto the SCSI bus. The contents of            timed out by the controlling microprocessor or
    the SODL register can be asserted at any time,         a SCRIPTS loop.
    even before the SYM53C810A is connected to
    the SCSI bus. This bit should be cleared when      Bit 2 AESP (Assert even SCSI parity
    executing SCSI SCRIPTS. It is normally used                     (force bad parity))
    only for diagnostics testing or operation in low
    level mode.                                            When this bit is set, the SYM53C810A asserts
                                                           even parity. It forces a SCSI parity error on
Bit 5 DHP (Disable Halt on Parity Error                    each byte sent to the SCSI bus from the
             or ATN) (Target Only)                         SYM53C810A. If parity checking is enabled,
                                                           then the SYM53C810A checks data received
    The DHP bit is only defined for target role.           for odd parity. This bit is used for diagnostic
    When this bit is cleared, the SYM53C810A               testing and should be clear for normal opera-
    halts the SCSI data transfer when a parity error       tion. It can be used to generate parity errors to
    is detected or when the SATN/ signal is                test error handling functions.
    asserted. If SATN/ or a parity error is received
    in the middle of a data transfer, the
    SYM53C810A may transfer up to three addi-
    tional bytes before halting to synchronize

SYM53C810A Data Manual                                 5-7
Operating Registers

Bit 1 IARB (Immediate Arbitration)                      Bit 0 SST (Start SCSI Transfer)
    Setting this bit causes the SCSI core to imme-          This bit is automatically set during SCRIPTS
    diately begin arbitration once a Bus Free phase         execution, and should not be used. It causes
    is detected following an expected SCSI discon-          the SCSI core to begin a SCSI transfer, includ-
    nect. This bit is useful for multi-threaded appli-      ing SREQ/SACK handshaking. The determi-
    cations. The ARB1-0 bits in SCNTL0 should               nation of whether the transfer is a send or
    be set for full arbitration and selection before        receive is made according to the value written
    setting this bit.                                       to the I/O bit in SOCL. This bit is self-reset-
                                                            ting. It should not be set for low level opera-
    Arbitration will be re-tried until won. At that         tion.
    point, the SYM53C810A will hold BSY and
    SEL asserted, and wait for a select or reselect                              CAUTION:
    sequence to be requested. The Immediate
    Arbitration bit will be reset automatically when    Writing to this register while not connected may
    the selection or reselection sequence is com-       cause the loss of a selection/reselection by resetting
    pleted, or times out. Interrupts will not occur     the Connected bit.
    until after this bit is reset.

    An unexpected disconnect condition will clear
    IARB without attempting arbitration. See the
    SCSI Disconnect Unexpected bit (SCNTL2,
    bit 7) for more information on expected versus
    unexpected disconnects.

    An immediate arbitration sequence can be
    aborted. First, the Abort bit in the ISTAT reg-
    ister should be set. Then one of two things will
    eventually happen:

    1. The Won Arbitration bit (SSTAT0 bit 2)
         will be set. In this case, the Immediate
         Arbitration bit needs to be reset. This will
         complete the abort sequence and
         disconnect the SYM53C810A from the
         SCSI bus. If it is not acceptable to go to
         Bus Free phase immediately following the
         arbitration phase, a low level selection may
         be performed instead.

    2. The abort will complete because the
         SYM53C810A loses arbitration. This can
         be detected by the Immediate Arbitration
         bit being cleared. The Lost Arbitration bit
         (SSTAT0 bit 3) should not be used to
         detect this condition. No further action
         needs to be taken in this case.

5-8                                                     SYM53C810A Data Manual
                                                                          Operating Registers

Register 02 (82)                                     Register 03 (83)
SCSI Control Two (SCNTL2)                            SCSI Control Three (SCNTL3)
Read/Write                                           Read/Write

SDU  RES    RES         RES  RES  RES  RES  RES      RES SCF2 SCF1 SCF0 RES CCF2 CCF1 CCF0

7    6      5           4    3    2    1    0        7  6        5  4  3  2       1  0

Default>>>                                           Default>>>

0    X      X           X    X    X    X    X        X  0        0  0  X  0       0  0

Bit 7 SDU (SCSI Disconnect Unexpected)               Bit 7 Reserved
    This bit is valid in initiator mode only. When
    this bit is set, the SCSI core is not expecting  Bits 6-4 SCF2-0 (Synchronous Clock
    the SCSI bus to enter the Bus Free phase. If it               Conversion Factor)
    does, an unexpected disconnect error will be
    generated (see the Unexpected Disconnect bit         These bits select the factor by which the fre-
    in the SIST0 register, bit 2). During normal         quency of SCLK is divided before being pre-
    SCRIPTS mode operation, this bit is set auto-        sented to the synchronous SCSI control logic.
    matically whenever the SCSI core is reselected,      The bits are encoded as per Table 5-2, "Syn-
    or successfully selects another SCSI device.         chronous Clock Conversion Factor," on
    The SDU bit should be reset with a register          page 5-10. For synchronous receive, the output
    write (MOVE 0X7f & SCNTL2 TO SCNTL2)                 of this divider is always divided by 4 and that
    before the SCSI core expects a disconnect to         value determines the transfer rate. For exam-
    occur, normally prior to sending an Abort,           ple, if SCLK is 40 MHz and the SCF value is
    Abort Tag, Bus Device Reset, Clear Queue or          set to divide by one, then the maximum syn-
    Release Recovery message, or before deassert-        chronous receive rate is 10 Mb/s
    ing SACK/ after receiving a Disconnect com-           (  40 / 1 ) / 4 = 10 .
    mand or Command Complete message.
                                                         For synchronous send, the output of this
Bits 6-0 Reserved                                        divider gets divided by the transfer period
                                                         (XFERP) bits in the SCSI Transfer (SXFER)
                                                         register, and that value determines the transfer

SYM53C810A Data Manual                                                               5-9
Operating Registers

      rate. For valid combinations of the SCF and  Table 5-3: Asynchronous Clock Conversion
      XFERP, see Table 5-4 and Table 5-5.                                     Factor

Table 5-2: Synchronous Clock Conversion            CCF2  CCF1  CCF0  SCSI Clock (MHz)
                          Factor                   0     0     0     50.01-66.00
                                                   0     0     1     16.67-25.00
SCF2  SCF1           SCF0  Factor Frequency        0     1     0     25.01-37.50
0     0              0     SCLK/3                  0     1     1     37.51-50.00
0     0              1     SCLK/1                  1     0     0     50.01-66.00
0     1              0     SCLK/1.5                1     0     1     Reserved
0     1              1     SCLK/2                  1     1     0     Reserved
1     0              0     SCLK/3                  1     1     1     Reserved
1     0              1     Reserved
1     1              0     Reserved
1     1              1     Reserved

Note: for additional information on how the
         synchronous transfer rate is determined,
         see "Synchronous Operation" on page 2-
         11.

Bit 3 Reserved

Bits 2-0 CCF2-0 (Clock Conversion Factor
    These bits select the frequency of the SCLK
    for asynchronous SCSI operations.The bits are
    encoded as per the following table. All other
    combinations are reserved and should never be
    used.

5-10                                                                 SYM53C810A Data Manual
                                                                                           Operating Registers

Register 04 (84)                                         Register 05 (85)
SCSI Chip ID (SCID)                                      SCSI Transfer (SXFER)
Read/Write                                               Read/Write

RES  RRE    SRE         RES  RES ENC2 ENC1 ENC0          TP2  TP1       TP0     RES  MO3   MO2  MO1    MO0

7    6      5           4    3  2       1  0             7    6         5       4    3     2    1      0

Default>>>                                               Default>>>

X    0      0           X    X  0       0  0             0    0         0       X    0     0    0      0

Bit 7 Reserved                                           Note: when using Table Indirect I/O commands,
                                                                  bits 7-0 of this register will be loaded from
Bit 6 RRE (Enable Response to                                     the I/O data structure.
             Reselection)
                                                         Note: for additional information on how the
    When this bit is set, the SYM53C810A is                       synchronous transfer rate is determined,
    enabled to respond to bus-initiated reselection               refer to Chapter 2, "Functional
    at the chip ID in the RESPID register. Note                   Description."
    that the SYM53C810A will not automatically
    reconfigure itself to initiator mode as a result of  Bits 7-5 TP2-0 (SCSI Synchronous Transfer
    being reselected.                                                 Period)

Bit 5 SRE (Enable Response to Selection)                     These bits determine the SCSI synchronous
    When this bit is set, the SYM53C810A is able             transfer period (XFERP) used by the
    to respond to bus-initiated selection at the chip        SYM53C810A when sending synchronous
    ID in the RESPID register. Note that the                 SCSI data in either initiator or target mode.
    SYM53C810A will not automatically reconfig-              These bits control the programmable dividers
    ure itself to target mode as a result of being           in the chip.
    selected.

Bit 4-3 Reserved                                              TP2            TP1     TP0        XFERP

                                                                     0       0          0       4

Bits 2-0 Encoded SYM53C810A Chip SCSI                                0       0          1       5
             ID, bits 2-0
                                                                     0       1          0       6
    These bits are used to store the SYM53C810A
    encoded SCSI ID. This is the ID which the                        0       1          1       7
    chip will assert when arbitrating for the SCSI
    bus. The IDs that the SYM53C810A will                            1       0          0       8
    respond to when being selected or reselected
    are configured in the RESPID register. The                       1       0          1       9
    priority of the 8 possible IDs, in descending
    order is:                                                        1       1          0       10

                                                                     1       1          1       11

            Highest             Lowest                      Use the following formula to calculate the syn-
                                                            chronous send and receive rates. Table 5-4 and
            76543210                                        Table 5-5 show examples of possible bit com-
                                                            binations.

SYM53C810A Data Manual                                                                                 5-11
Operating Registers

     Synchronous Send Rate = (SCLK/SCF)/XFERP
     Synchronous Receive Rate = (SCLK/SCF) / 4
Key:
SCLK = SCLK
SCF = Synchronous Clock Conversion Factor, SCNTL3 bits
6-4
XFERP = Transfer period, SXFER register bits 7-5

            Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1

SCLK (MHz)           SCF (SCNTL3 XFERP (SXFER Sync Send  Sync Send    Sync Receive    Synch
                                                         Period (ns)  Rate (MB/s)     Receive
66.67                bits 6-4)  bits 7-5)  Rate (MB/s)                                Period (ns)
66.67                                                    180          5.55
50                   ÷3         4          5.55          225          5.55            180
50                                                       160          6.25            180
40                   ÷3         5          4.44          200          6.25            160
37.50                                                    200          5               160
33.33                ÷2         4          6.25          160          6.25            200
25                                                       180          5.55            160
20                   ÷2         5          5             160          6.25            180
16.67                                                    200          5               160
                     ÷2         4          5             240          4.17            200
                                                                                      240
                     ÷ 1.5      4          6.25

                     ÷ 1.5      4          5.55

                     ÷1         4          6.25

                     ÷1         4          5

                     ÷1         4          4.17

            Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI

SCLK (MHz)           SCF (SCNTL3 XFERP (SXFER Sync Send  Sync Send    Sync Receive    Synch
                                                         Period (ns)  Rate (MB/s)     Receive
66.67                bits 6-4)  bits 7-5)  Rate (MB/s)                                Period (ns)
66.67                                                    90           11.11
50                   ÷ 1.5      4          11.11         112.5        11.11           90
50                                         8.88          80           12.5            90
40                   ÷1         5          12.5          100          12.5            80
37.50                                      10            100          10              80
33.33                ÷1         4          10            106.67       9.375           100
25                                         9.375         120          8.33            106.67
20                   ÷1         5          8.33          160          6.25            120
16.67                                      6.25          200          5               160
                     ÷1         4          5             240          4.17            200
                                           4.17                                       240
                     ÷1         4

                     ÷1         4

                     ÷1         4

                     ÷1         4

                     ÷1         4

5-12                                                                  SYM53C810A Data Manual
                                                                                   Operating Registers

Bit 4 Reserved                                        Register 06 (86)
                                                      SCSI Destination ID (SDID)
Bits 3-0 MO4-MO0 (Max SCSI Synchronous                Read/Write
             Offset)
                                                      RES  RES    RES      RES  RES ENC2 ENC1 ENC0
    These bits describe the maximum SCSI syn-
    chronous offset used by the SYM53C810A            7    6      5        4    3  2       1  0
    when transferring synchronous SCSI data in
    either initiator or target mode. The following    Default>>>
    table describes the possible combinations and
    their relationship to the synchronous data off-   X    X      X        X    X  0       0  0
    set used by the SYM53C810A. These bits
    determine the SYM53C810A's method of              Bits 7-3 Reserved
    transfer for Data In and Data Out phases only;
    all other information transfers will occur asyn-  Bits 2-0 Encoded destination SCSI ID
    chronously.                                           Writing these bits sets the SCSI ID of the
                                                          intended initiator or target during SCSI rese-
Table 5-6: SCSI Synchronous Offset Values                 lection or selection phases, respectively. When
                                                          executing SCRIPTS, the SCRIPTS processor
MO3  MO2  MO1           MO0  Synchronous                  writes the destination SCSI ID to this register.
                             Offset                       The SCSI ID is defined by the user in a
                                                          SCRIPTS SELECT or RESELECT instruc-
0 0 0 0 0-Asynchronous                                    tion. The value written should be the binary-
00011                                                     encoded ID value. The priority of the 8 possi-
00102                                                     ble IDs, in descending order, is:
00113
01004                                                             Highest          Lowest
01015
01106                                                             76543210
01117
10008
1 X X 1 Reserved
1 X 1 X Reserved
1 1 X X Reserved

SYM53C810A Data Manual                                                                        5-13
Operating Registers

Register 07 (87)                                      Register 08 (88)
General Purpose (GPREG)                               SCSI First Byte Received (SFBR)
Read/Write                                            Read/Write

RES   RES   RES      RES  RES  RES  GPIO1  GPIO0      1B7  1B6    1B5  1B4  1B3  1B2  1B1  1B0
                                       1      0
7     6     5        4    3    2                      7    6      5    4    3    2     1   0

Default>>>                                            Default>>>

X     X     X        X    X    X    0      0          0    0      0    0    0    0     0   0

Bits 7-2 Reserved                                     This register contains the first byte received in any
                                                      asynchronous information transfer phase. For ex-
Bits 1-0 GPIO1-GPIO0 (General Purpose)                ample, when the SYM53C810A is operating in ini-
    These bits can be programmed through the          tiator role, this register contains the first byte
    GPCNTL Register to become inputs, outputs,        received in Message In, Status Phase, Reserved In
    or, special functions. These signals can also be  and Data In.
    programmed as live inputs and sensed through
    a SCRIPTS Register to Register Move Instruc-      When a Block Move instruction is executed for a
    tion. GPIO(1-0) default as inputs. When con-      particular phase, the first byte received is stored in
    figured as inputs, an internal pull-up is         this register--even if the present phase is the same
    enabled.                                          as the last phase. The first byte-received value for a
                                                      particular input phase is not valid until after a
    The Symbios Logic SDMS software uses the          MOVE instruction is executed.
    GPIO 0 pin to toggle SCSI device LEDs, turn-
    ing on the LED whenever the SYM53C810A            This register is also the accumulator for register
    is connected to the SCSI bus. SDMS drives         read-modify-writes with the SFBR as the destina-
    this pin low to turn on the LED, or drives it     tion. This allows bit testing after an operation.
    high to turn off the LED.
                                                      The SFBR can not be written to via the CPU, and
    The GPIO 1-0 pins are used in SDMS to             therefore not by a Memory Move. Additionally, the
    access serial NVRAM. When used for access-        Load instruction cannot be used to write to this reg-
    ing serial NVRAM, GPIO 1 is used as a clock       ister. However, the SFBR can be loaded via
    with the GPIO 0 pin serving as data.              SCRIPTS Read/Write operations. To load the
                                                      SFBR with a byte stored in system memory, the
                                                      byte must first be moved to an intermediate
                                                      SYM53C810A register (such as the SCRATCH
                                                      register), and then to the SFBR.

                                                      This register will also contain the state of the lower
                                                      eight bits of the SCSI data bus during the selection
                                                      phase if the COM bit in the DCNTL register is
                                                      clear.

5-14                                                                             SYM53C810A Data Manual
                                                                                 Operating Registers

Register 09 (89)                                        Register 0A (8A)
SCSI Output Control Latch (SOCL)                        SCSI Selector ID (SSID)
Read /Write                                             Read Only

REQ  ACK    BSY         SEL  ATN MSG  C/D  I/O          VAL  RES    RES  RES  RES ENID2 ENID1 ENID0

7    6      5           4    3  2     1    0            7    6      5    4    3  2  1  0

Default>>>                                              Default>>>

0    0      0           0    0  0     0    0            0    X      X    X    X  0  0  0

Bit 7 REQ(Assert SCSI REQ/ signal)                      Bit 7 VAL (SCSI Valid Bit)
                                                            If VAL is asserted, the two SCSI IDs were
Bit 6 ACK(Assert SCSI ACK/ signal)                          detected on the bus during a bus-initiated
                                                            selection or reselection, and the encoded desti-
Bit 5 BSY(Assert SCSI BSY/ signal)                          nation SCSI ID bits below are valid. If VAL is
                                                            deasserted, only one ID was present and the
Bit 4 SEL(Assert SCSI SEL/ signal)                          contents of the encoded destination ID are
                                                            meaningless.
Bit 3 ATN(Assert SCSI ATN/ signal)
                                                        Bits 6-3 Reserved
Bit 2 MSG(Assert SCSI MSG/ signal)
                                                        Bits 2-0 Encoded Destination SCSI ID
Bit 1 C/D(Assert SCSI C_D/ signal)                          Reading the SSID register immediately after
                                                            the SYM53C810A has been selected or rese-
Bit 0 I/O(Assert SCSI I_O/ signal)                          lected returns the binary-encoded SCSI ID of
This register is used primarily for diagnostic testing      the device that performed the operation.These
or programmed I/O operation. It is controlled by            bits are invalid for targets that are selected
the SCRIPTS processor when executing SCSI                   under the single initiator option of the SCSI-1
SCRIPTS. SOCL should only be used when trans-               specification. This condition can be detected
ferring data via programmed I/O. Some bits are set          by examining the VAL bit above.
(1) or reset (0) when executing SCSI SCRIPTS.
Do not write to the register once the
SYM53C810A starts executing normal SCSI
SCRIPTS.

SYM53C810A Data Manual                                                                 5-15
Operating Registers

Register 0B (8B)                                        Register 0C (8C)
SCSI Bus Control Lines (SBCL)                           DMA Status (DSTAT)
Read Only                                               Read Only

REQ   ACK   BSY      SEL  ATN MSG  C/D  I/O             DFE MDPE    BF  ABRT SSI  SIR  RES  IID

7     6     5        4    3  2     1    0               7  6        5   4   3     2    1    0

Default>>>                                              Default>>>

X     X     X        X    X  X     X    X               1  0        0   0   0     0    X    0

Bit 7 REQ (SREQ/ status)                                Reading this register will clear any bits that are set
                                                        at the time the register is read, but will not neces-
Bit 6 ACK (SACK/ status)                                sarily clear the register because additional inter-
                                                        rupts may be pending (the SYM53C810A stacks
Bit 5 BSY (SBSY/ status)                                interrupts). The DIP bit in the ISTAT register will
                                                        also be cleared. DMA interrupt conditions may be
                                                        individually masked through the DIEN register.

Bit 4 SEL (SSEL/ status)                                When performing consecutive 8-bit reads of the
                                                        DSTAT, SIST0 and SIST1 registers (in any or-
Bit 3 ATN SATN/ status)                                 der), insert a delay equivalent to 12 CLK periods
                                                        between the reads to ensure that the interrupts clear
Bit 2 MSG (SMSG/ status)                                properly. See Chapter 2, "Functional Description,"
                                                        for more information on interrupts.
Bit 1 C/D (SC_D/ status)

Bit 0 I/O (SI_O/ status)                                Bit 7 DFE (DMA FIFO empty)
When read, this register returns the SCSI control           This status bit is set when the DMA FIFO is
line status. A bit will be set when the corresponding       empty. It may be used to determine if any data
SCSI control line is asserted. These bits are not           resides in the FIFO when an error occurs and
latched; they are a true representation of what is on       an interrupt is generated. This bit is a pure sta-
the SCSI bus at the time the register is read. The re-      tus bit and will not cause an interrupt.
sulting read data is synchronized before being pre-
sented to the PCI bus to prevent parity errors from     Bit 6 MDPE (Master Data Parity Error)
being passed to the system. This register can be            This bit is set when the SYM53C810A as a
used for diagnostics testing or operation in low level      master detects a data parity error, or a target
mode.                                                       device signals a parity error during a data
                                                            phase. This bit is completely disabled by the
                                                            Master Parity Error Enable bit (bit 3 of
                                                            CTEST4).

                                                        Bit 5 BF (Bus fault)
                                                            This bit is set when a PCI bus fault condition
                                                            is detected. A PCI bus fault can only occur
                                                            when the SYM53C810A is bus master. A PCI
                                                            bus fault occurs when a cycle ends with a Bad
                                                            Address or Target Abort Condition.

5-16                                                                              SYM53C810A Data Manual
                                                                                  Operating Registers

Bit 4 ABRT (Aborted)                                     Register 0D (8D)
    This bit is set when an abort condition occurs.      SCSI Status Zero (SSTAT0)
    An abort condition occurs when a software            Read Only
    abort command is issued by setting bit 7 of the
    ISTAT register.                                      ILF  ORF    OLF  AIP  LOA WOA  RST SDP0/

Bit 3 SSI (Single step interrupt)                        7    6      5    4    3    2   1  0
    If the Single-Step Mode bit in the DCNTL
    register is set, this bit will be set and an inter-  Default>>>
    rupt generated after successful execution of
    each SCRIPTS instruction.                            0    0      0    0    0    0   0  0

Bit 2 SIR (SCRIPTS interrupt                             Bit 7 ILF (SIDL full)
             instruction received)                           This bit is set when the SCSI Input Data Latch
                                                             register (SIDL) contains data. Data is trans-
    This status bit is set whenever an Interrupt             ferred from the SCSI bus to the SCSI Input
    instruction is evaluated as true.                        Data Latch register before being sent to the
                                                             DMA FIFO and then to the host bus. The
Bit 1 Reserved                                               SIDL register contains SCSI data received
                                                             asynchronously. Synchronous data received
                                                             does not flow through this register.

Bit 0 IID (Illegal instruction detected)                 Bit 6 ORF (SODR full)
    This status bit is set any time an illegal instruc-      This bit is set when the SCSI Output Data
    tion is detected, whether the SYM53C810A is              Register (SODR, a hidden buffer register
    operating in single-step mode or automatically           which is not accessible) contains data. The
    executing SCSI SCRIPTS. This bit will also be            SODR register is used by the SCSI logic as a
    set if one of the following conditions occurs:           second storage register when sending data syn-
                                                             chronously. It cannot be read or written by the
    1. If the SYM53C810A is executing a Wait                 user. This bit can be used to determine how
         Disconnect instruction and the SCSI REQ             many bytes reside in the chip when an error
         line is asserted without a disconnect               occurs.
         occurring.
                                                         Bit 5 OLF (SODL full)
    2. If a Move, Chained Move, or Memory                    This bit is set when SCSI Output Data Latch
         Move command with a byte count of zero              (SODL) contains data. The SODL register is
         is fetched.                                         the interface between the DMA logic and the
                                                             SCSI bus. In synchronous mode, data is trans-
    3. If a Load/Store memory address maps back              ferred from the host bus to the SODL register,
         into chip register space.                           and then to the SCSI Output Data Register
                                                             (SODR, a hidden buffer register which is not
                                                             accessible) before being sent to the SCSI bus.
                                                             In asynchronous mode, data is transferred
                                                             from the host bus to the SODL register, and
                                                             then to the SCSI bus. The SODR buffer regis-
                                                             ter is not used for asynchronous transfers. This
                                                             bit can be used to determine how many bytes
                                                             reside in the chip when an error occurs.

SYM53C810A Data Manual                                                                     5-17
Operating Registers

Bit 4 AIP (Arbitration in progress)                    Register 0E (8E)
    Arbitration in Progress (AIP = 1) indicates that   SCSI Status One (SSTAT1)
    the SYM53C810A has detected a Bus Free             Read Only
    condition, asserted BSY, and asserted its SCSI
    ID onto the SCSI bus.                              FF3   FF2        FF1  FF0 SDP0L MSG  C/D  I/O

Bit 3 LOA (Lost arbitration)                           7     6          5       4  3     2  1    0
    When set, LOA indicates that the
    SYM53C810A has detected a bus free condi-          Default>>>
    tion, arbitrated for the SCSI bus, and lost arbi-
    tration due to another SCSI device asserting       0     0          0       0  X     X  X    X
    the SEL/ signal.
                                                       Bits 7-4 FF3-FF0 (FIFO flags)
Bit 2 WOA (Won arbitration)
    When set, WOA indicates that the                   FF3         FF2       FF1   FF0      Bytes in the
    SYM53C810A has detected a Bus Free condi-                                                SCSI FIFO
    tion, arbitrated for the SCSI bus and won arbi-       0        0         0        0
    tration. The arbitration mode selected in the                                                 0
    SCNTL0 register must be full arbitration and          0        0         0        1           1
    selection for this bit to be set.                                                             2
                                                          0        0         1        0           3
Bit 1 RST/ (SCSI RST/ signal)                                                                     4
    This bit reports the current status of the SCSI       0        0         1        1           5
    RST/ signal, and the SRST bit (bit 6) in the                                                  6
    ISTAT register.                                       0        1         0        0           7
                                                                                                  8
Bit 0 SDP/ (SCSI SDP/ parity signal)                      0        1         0        1           9
    This bit represents the active high current sta-
    tus of the SCSI SDP/ parity signal.                   0        1         1        0

                                                          0        1         1        1

                                                          1        0         0        0

                                                          1        0         0        1

                                                          These four bits define the number of bytes that
                                                          currently reside in the SYM53C810A's SCSI
                                                          synchronous data FIFO. These bits are not
                                                          latched and they will change as data moves
                                                          through the FIFO. Because the FIFO can only
                                                          hold nine bytes, values over nine will not occur.

                                                       Bit 3 SDPL (Latched SCSI parity)
                                                           This bit reflects the SCSI parity signal
                                                           (SDP/), corresponding to the data latched in
                                                           the SCSI Input Data Latch register (SIDL). It
                                                           changes when a new byte is latched into the
                                                           SIDL register. This bit is active high, in other
                                                           words, it is set when the parity signal is active.

5-18                                                                                  SYM53C810A Data Manual
                                                                                  Operating Registers

Bit 2 MSG (SCSI MSG/ signal)                         Register 0F (8F)

Bit 1 C/D (SCSI C_D/ signal)                         SCSI Status Two (SSTAT2)
                                                     (Read Only)

Bit 0 I/O (SCSI I_O/ signal)                         RES  RES    RES    RES  RES  RES LDSC RES
These SCSI phase status bits are latched on the as-
serting edge of SREQ/ when operating in either ini-  7    6      5      4    3    2  1  0
tiator or target mode. These bits are set when the
                                                     Default>>>

                                                     X    X      X      X    X    X  1  X

corresponding signal is active. They are useful      Bits 7-2 Reserved
when operating in low level mode.

                                                     Bit 1 LDSC (Last Disconnect)
                                                         This bit is used in conjunction with the Con-
                                                         nected (CON) bit in SCNTL1. It allows the
                                                         user to detect the case in which a target device
                                                         disconnects, and then some SCSI device
                                                         selects or reselects the SYM53C810A. If the
                                                         Connected bit is asserted and the LDSC bit is
                                                         asserted, a disconnect has occurred. This bit is
                                                         set when the Connected bit in SCNTL1 is
                                                         clear. This bit is cleared when a Block Move
                                                         instruction executes while the Connected bit in
                                                         SCNTL1 is on.

                                                     Bit 0 Reserved

SYM53C810A Data Manual                                                                  5-19
Operating Registers

Registers 10-13 (90-93)                                Register 14 (94)
Data Structure Address (DSA)                           Interrupt Status (ISTAT)
Read/Write                                             (Read/Write)

This 32-bit register contains the base address used    ABRT SRST SIGP SEM CON INTF  SIP  DIP
for all table indirect calculations. The DSA register
is usually loaded prior to starting an I/O, but it is  7  6        5  4  3       2  1    0
possible for a SCRIPTS Memory Move to load the
DSA during the I/O.                                    Default>>>

During any Memory-to-Memory Move operation,            0  0        0  0  0       0  0    0
the contents of this register are preserved. The
power-up value of this register is indeterminate.      This is the only register that can be accessed by the
                                                       host CPU while the SYM53C810A is executing
                                                       SCRIPTS (without interfering in the operation of
                                                       the SYM53C810A). It may be used to poll for in-
                                                       terrupts if hardware interrupts are disabled. There
                                                       may be stacked interrupts pending; read this regis-
                                                       ter after servicing an interrupt to check for stacked
                                                       interrupts. For more information on interrupt han-
                                                       dling refer to Chapter 2, "Functional Description."

                                                       Bit 7 ABRT (Abort operation)
                                                           Setting this bit aborts the current operation
                                                           being executed by the SYM53C810A. If this
                                                           bit is set and an interrupt is received, reset this
                                                           bit before reading the DSTAT register to pre-
                                                           vent further aborted interrupts from being gen-
                                                           erated. The sequence to abort any operation is:

                                                           1. Set this bit.

                                                           2. Wait for an interrupt.

                                                           3. Read the ISTAT register.

                                                           4. If the SCSI Interrupt Pending bit is set,
                                                                then read the SIST0 or SIST1 register to
                                                                determine the cause of the SCSI Interrupt
                                                                and go back to Step 2.

                                                           5. If the SCSI Interrupt Pending bit is clear,
                                                                and the DMA Interrupt Pending bit is set,
                                                                then write 00h value to this register.

                                                           6. Read the DSTAT register to verify the
                                                                aborted interrupt and to see if any other
                                                                interrupting conditions have occurred.

                                                       Bit 6 SRST (Software reset)
                                                           Setting this bit resets the SYM53C810A. All
                                                           operating registers are cleared to their default
                                                           values and all SCSI signals are deasserted. Set-

5-20                                                                             SYM53C810A Data Manual
                                                       Operating Registers

    ting this bit does not cause the SCSI RST/ sig-    Bit 3 CON (Connected)
    nal to be asserted. This reset will not clear the      This bit is automatically set any time the
    53C700 compatibility bit or any of the PCI             SYM53C810A is connected to the SCSI bus
    configuration registers. This bit is not self-         as an initiator or as a target. It will be set after
    clearing; it must be cleared to clear the reset        successfully completing selection or when the
    condition (a hardware reset will also clear this       SYM53C810A has responded to a bus-initi-
    bit).                                                  ated selection or reselection. It will also be set
                                                           after the SYM53C810A wins arbitration when
Bit 5 SIGP (Signal process)                                operating in low level mode. When this bit is
    SIGP is a R/W bit that can be written at any           clear, the SYM53C810A is not connected to
    time, and polled and reset via CTEST2. The             the SCSI bus.
    SIGP bit can be used in various ways to pass a
    flag to or from a running SCRIPTS instruc-         Bit 2 INTF (Interrupt on the Fly)
    tion.                                                  This bit is asserted by an INTFLY instruction
                                                           during SCRIPTS execution. SCRIPTS pro-
    The only SCRIPTS instruction directly                  grams will not halt when the interrupt occurs.
    affected by the SIGP bit is Wait For Selection/        This bit can be used to notify a service routine,
    Reselection. Setting this bit causes that              running on the main processor while the
    instruction to jump to the alternate address           SCRIPTS processor is still executing a
    immediately. The instructions at the alternate         SCRIPTS program. If this bit is set, when the
    jump address should check the status of SIGP           ISTAT register is read it will not automatically
    to determine the cause of the jump. The SIGP           be cleared. To clear this bit, it must be written
    bit may be used at any time and is not                 to a one. The reset operation is self-clearing.
    restricted to the wait for selection/ reselection
    condition.                                         Note: if the INTF bit is set but SIP or DIP is not
                                                                set, do not attempt to read the other chip
Bit 4 SEM (Semaphore)                                           status registers. An interrupt-on-the-fly
    This bit can be set by the SCRIPTS processor                interrupt must be cleared before servicing
    using a SCRIPTS register write instruction.                 any other interrupts indicated by SIP or
    The bit may also be set by an external proces-              DIP.
    sor while the SYM53C810A is executing a
    SCRIPTS operation. This bit enables the            Note: this bit must be written to one in order to
    SYM53C810A to notify an external processor                  clear it after it has been set.
    of a predefined condition while SCRIPTS are
    running. The external processor may also
    notify the SYM53C810A of a predefined con-
    dition and the SCRIPTS processor may take
    action while SCRIPTS are executing.

SYM53C810A Data Manual                                 5-21
Operating Registers

Bit 1 SIP (SCSI interrupt pending)                   Register 18 (98)
    This status bit is set when an interrupt condi-  Chip Test Zero (CTEST0)
    tion is detected in the SCSI portion of the      Read/Write
    SYM53C810A. The following conditions will
    cause a SCSI interrupt.                          This was a general purpose read/write register in
                                                     previous SYM53C8XX family chips. Although it is
    s A phase mismatch occurs (initiator mode)       still a read/write register, Symbios reserves the right
         or SATN/ becomes active (target mode)       to use these bits for future 53C8XX family en-
                                                     hancements.
    s An arbitration sequence completes

    s A selection or reselection time-out occurs

    s The SYM53C810A was selected

    s The SYM53C810A was reselected

    s A SCSI gross error occurs

    s An unexpected disconnect occurs

    s A SCSI reset occurs

    s A parity error is detected

    s The handshake-to-handshake timer is
         expired

    s The general purpose timer is expired

     To determine exactly which condition(s)
    caused the interrupt, read the SIST0 and
    SIST1 registers.

Bit 0 DIP (DMA interrupt pending)
    This status bit is set when an interrupt condi-
    tion is detected in the DMA portion of the
    SYM53C810A. The following conditions will
    cause a DMA interrupt.

    s A PCI parity error is detected

    s A bus fault is detected

    s An abort condition is detected

    s A SCRIPTS instruction is executed in
         single-step mode

    s A SCRIPTS interrupt instruction is
         executed

    s An illegal instruction is detected

    To determine exactly which condition(s)
    caused the interrupt, read the DSTAT register.

5-22                                                 SYM53C810A Data Manual
                                                                               Operating Registers

Register 19 (99)                                       Register 1A (9A)
Chip Test One (CTEST1)                                 Chip Test Two (CTEST2)
Read Only                                              Read Only

FMT3 FMT2 FMT1 FMT0 FFL3 FFL2 FFL1 FFL0                DDIR SIGP   CIO  CM  RES TEOP DREQ DACK

7  6        5           4  3  2  1  0                  7  6        5    4   3  2  1  0

Default>>>                                             Default>>>

1  1        1           1  0  0  0  0                  0  0        X    X   0  0  0  1

Bits 7-4 FMT3-0 (Byte empty in DMA FIFO)               Bit 7 DDIR (Data transfer direction)
    These bits identify the bottom bytes in the            This status bit indicates which direction data is
    DMA FIFO that are empty. Each bit corre-               being transferred. When this bit is set, the data
    sponds to a byte lane in the DMA FIFO. For             will be transferred from the SCSI bus to the
    example, if byte lane three is empty, then             host bus. When this bit is clear, the data will be
    FMT3 will be set. Since the FMT flags indi-            transferred from the host bus to the SCSI bus.
    cate the status of bytes at the bottom of the
    FIFO, if all FMT bits are set, the DMA FIFO        Bit 6 SIGP (Signal process)
    is empty.                                              This bit is a copy of the SIGP bit in the ISTAT
                                                           register (bit 5).The SIGP bit is used to signal a
Bits 3-0 FFL3-0 (Byte full in DMA FIFO)                    running SCRIPTS instruction. When this reg-
    These status bits identify the top bytes in the        ister is read, the SIGP bit in the ISTAT register
    DMA FIFO that are full. Each bit corresponds           is cleared.
    to a byte lane in the DMA FIFO. For example,
    if byte lane three is full then FFL3 will be set.  Bit 5 CIO (Configured as I/O)
    Since the FFL flags indicate the status of bytes       This bit is defined as the Configuration I/O
    at the top of the FIFO, if all FFL bits are set,       Enable Status bit. This read-only bit indicates
    the DMA FIFO is full.                                  if the chip is currently enabled as I/O space.

                                                       Note: both bits 4 and 5 may be set if the chip is
                                                                dual-mapped.

                                                       Bit 4 CM (Configured as memory)
                                                           This bit is defined as the configuration mem-
                                                           ory enable status bit. This read-only bit indi-
                                                           cates if the chip is currently enabled as
                                                           memory space.

                                                       Note: both bits 4 and 5 may be set if the chip is
                                                                dual-mapped.

                                                       Bit 3 Reserved

SYM53C810A Data Manual                                                               5-23
Operating Registers

Bit 2 TEOP (SCSI true end of process)                  Register 1B (9B)
    This bit indicates the status of the               Chip Test Three (CTEST3)
    SYM53C810A's internal TEOP signal. The             Read/Write
    TEOP signal acknowledges the completion of
    a transfer through the SCSI portion of the         V3  V2      V1  V0  FLF   CLF  FM  WRIE
    SYM53C810A. When this bit is set, TEOP is
    active. When this bit is clear, TEOP is inactive.  7   6       5   4   3     2    1   0

Bit 1 DREQ (Data request status)                       Default>>>
    This bit indicates the status of the
    SYM53C810A's internal Data Request signal          X   X       X   X   0     0    0   0
    (DREQ). When this bit is set, DREQ is active.
    When this bit is clear, DREQ is inactive.          Bits 7-4 V3-V0 (Chip revision level)
                                                           These bits identify the chip revision level for
Bit 0 DACK (Data acknowledge status)                       software purposes.
    This bit indicates the status of the
    SYM53C810A's internal Data Acknowledge             Bit 3 FLF (Flush DMA FIFO)
    signal (DACK/). When this bit is set, DACK/ is         When this bit is set, data residing in the DMA
    inactive. When this bit is clear, DACK/ is             FIFO is transferred to memory, starting at the
    active.                                                address in the DNAD register. The internal
                                                           DMAWR signal, controlled by the CTEST5
                                                           register, determines the direction of the trans-
                                                           fer. This bit is not self clearing; once the
                                                           SYM53C810A has successfully transferred
                                                           the data, this bit should be reset.

                                                       Note: polling of FIFO flags is allowed during
                                                                flush operations.

                                                       Bit 2 CLF (Clear DMA FIFO)
                                                           When this bit is set, all data pointers for the
                                                           DMA FIFO are cleared. Any data in the FIFO
                                                           is lost. This bit automatically resets after the
                                                           SYM53C810A has successfully cleared the
                                                           appropriate FIFO pointers and registers.

                                                       Note: this bit does not clear the data visible at the
                                                                bottom of the FIFO.

                                                       Bit 1 FM (Fetch pin mode)
                                                           When set, this bit causes the FETCH/ pin to
                                                           deassert during indirect and table indirect read
                                                           operations. FETCH/ will only be active during
                                                           the op code portion of an instruction fetch.
                                                           This allows SCRIPTS to be stored in a PROM
                                                           while data tables are stored in RAM.

                                                           If this bit is not set, FETCH/ will be asserted
                                                           for all bus cycles during instruction fetches.

5-24                                                                            SYM53C810A Data Manual
                                                   Operating Registers

Bit 0 WRIE (Write and Invalidate Enable)           Registers 1C-1F (9C-9F)
    This bit, when set, causes Memory Write and    Temporary (TEMP)
    Invalidate commands to be issued on the PCI    Read/Write
    bus after certain conditions have been met.
    These conditions are described in more detail  This 32-bit register stores the Return instruction
    in Chapter 3.                                  address pointer from the Call instruction. The ad-
                                                   dress pointer stored in this register is loaded into
                                                   the DSP register when a Return instruction is exe-
                                                   cuted. This address points to the next instruction to
                                                   be executed. Do not write to this register while the
                                                   SYM53C810A is executing SCRIPTS.

                                                   During any Memory-to-Memory Move operation,
                                                   the contents of this register are preserved. The
                                                   power-up value of this register is indeterminate.

SYM53C810A Data Manual                             5-25
Operating Registers

Register 20 (A0)                                       Register 21 (A1)
DMA FIFO (DFIFO)                                       Chip Test Four (CTEST4)
Read/Write                                             Read/Write

RES   BO6   BO5      BO4  Bo3  BO2  BO1  BO0           BDIS ZMOD ZSD SRTM MPEE FBL2 FBL1 FBL0

7     6     5        4    3    2    1    0             7  6        5  4  3      2  1  0

Default>>>                                             Default>>>

X     0     0        0    0    0    0    0             0  0        0  0  0      0  0  0

Bit 7 Reserved                                         Bit 7 BDIS (Burst Disable)
                                                           When set, this bit will cause the
Bits 6-0 BO6-BO0 (Byte offset counter)                     SYM53C810A to perform back to back cycles
    These bits indicate the amount of data trans-          for all transfers. When reset, the
    ferred between the SCSI core and the DMA               SYM53C810A performs back to back transfers
    core. It may be used to determine the number           for op code fetches and burst transfers for data
    of bytes in the DMA FIFO when an interrupt             moves.The handling of op code fetches is
    occurs. These bits are unstable while data is          dependent on the setting of the Burst Op Code
    being transferred between the two cores; once          Fetch bit in the DMODE register.
    the chip has stopped transferring data, these
    bits are stable.                                   Bit 6 ZMOD (High impedance mode)
                                                           Setting this bit causes the SYM53C810A to
    Since the DFIFO register counts the number             place all output and bidirectional pins into a
    of bytes transferred between the DMA core              high-impedance state. In order to read data out
    and the SCSI core, and the DBC register                of the SYM53C810A, this bit must be cleared.
    counts the number of bytes transferred across          This bit is intended for board-level testing only.
    the host bus, the difference between these two         Do not set this bit during normal system oper-
    counters represents the number of bytes                ation.
    remaining in the DMA FIFO.
                                                       Bit 5 ZSD (SCSI Data High Impedance)
     The following steps will determine how many           Setting this bit causes the SYM53C810A to
    bytes are left in the DMA FIFO when an error           place the SCSI data bus SD(7-0) and the par-
    occurs, regardless of the direction of the trans-      ity line (SDP) in a high-impedance state. In
    fer:                                                   order to transfer data on the SCSI bus, this bit
                                                           must be cleared.
    1. Subtract the seven least significant bits of
         the DBC register from the 7-bit value of      Bit 4 SRTM (Shadow Register Test Mode)
         the DFIFO register.                               Setting this bit allows access to the shadow reg-
                                                           isters used by Memory-to-Memory Move
    2. AND the result with 7Fh for a byte count            operations. When this bit is set, register
         between zero and 64.                              accesses to the TEMP and DSA registers are
                                                           directed to the shadow copies STEMP
Note: to calculate the total number of bytes in            (Shadow TEMP) and SDSA (Shadow DSA).
         both the DMA FIFO and SCSI logic, see             The registers are shadowed to prevent them
         the section on Data Paths in Chapter Two,         from being overwritten during a Memory-to-
         "Functional Description."                         Memory Move operation. The DSA and
                                                           TEMP registers contain the base address used

5-26                                                                        SYM53C810A Data Manual
                                                                                Operating Registers

    for table indirect calculations, and the address   Register 22 (A2)
    pointer for a call or return instruction, respec-  Chip Test Five (CTEST5)
    tively. This bit is intended for manufacturing     Read/Write
    diagnostics only and should not be set during
    normal operations.                                 ADCK BBCK RES MASR DDIR RES  RES  RES

Bit 3 MPEE (Master Parity Error Enable)                7  6        5      4  3  2   1    0
    Setting this bit enables parity checking during
    master data phases. A parity error during a bus    Default>>>
    master read is detected by the SYM53C810A.
    A parity error during a bus master write is        0  0        X      0  0  X   X    X
    detected by the target, and the SYM53C810A
    is informed of the error by the PERR/ pin          Bit 7 ADCK (Clock address incrementor)
    being asserted by the target. When this bit is         Setting this bit increments the address pointer
    reset, the SYM53C810A will not interrupt if a          contained in the DNAD register. The DNAD
    master parity error occurs. This bit is reset at       register is incremented based on the DNAD
    power up.                                              contents and the current DBC value. This bit
                                                           automatically clears itself after incrementing
Bits 2-0 FBL2-FBL0 (FIFO byte control)                     the DNAD register.

FBL2  FBL1  FBL0        DMA FIFO   Pins                Bit 6 BBCK (Clock byte counter)
                        Byte lane                          Setting this bit decrements the byte count con-
0     X     X                      n/a                     tained in the 24-bit DBC register. It is decre-
1     0     0           Disabled   D(7-0)                  mented based on the DBC contents and the
1     0     1           0          D(15-8)                 current DNAD value. This bit automatically
1     1     0           1          D(23-16)                clears itself after decrementing the DBC regis-
1     1     1           2          D(31-24)                ter.
                        3
                                                       Bit 5 Reserved

These bits steer the contents of the CTEST6            Bit 4 MASR (Master control for set or
register to the appropriate byte lane of the 32-                    reset pulses)
bit DMA FIFO. If the FBL2 bit is set, then
FBL1 and FBL0 determine which of four byte                 This bit controls the operation of bit 3. When
lanes can be read or written. When cleared, the            this bit is set, bit 3 asserts the corresponding
byte lane read or written is determined by the             signals. When this bit is reset, bit 3 deasserts
current contents of the DNAD and DBC regis-                the corresponding signals. This bit and bit 3
ters. Each of the four bytes that make up the              should not be changed in the same write cycle.
32-bit DMA FIFO can be accessed by writing
these bits to the proper value. For normal             Bit 3 DDIR (DMA direction)
operation, FBL2 must equal zero.                           Setting this bit either asserts or deasserts the
                                                           internal DMA Write (DMAWR) direction sig-
                                                           nal depending on the current status of the
                                                           MASR bit in this register. Asserting the
                                                           DMAWR signal indicates that data will be
                                                           transferred from the SCSI bus to the host bus.
                                                           Deasserting the DMAWR signal transfers data
                                                           from the host bus to the SCSI bus.

                                                       Bits 2-0 Reserved

SYM53C810A Data Manual                                                                   5-27
Operating Registers

Register 23 (A3)                                      Registers 24-26 (A4-A6)
Chip Test Six (CTEST6)                                DMA Byte Counter (DBC)
Read/Write                                            Read/Write

DF7   DF6   DF5      DF4  DF3  DF2  DF1  DF0          This 24-bit register determines the number of bytes
                                                      to be transferred in a Block Move instruction.
7     6     5        4    3    2    1    0            While sending data to the SCSI bus, the counter is
                                                      decremented as data is moved into the DMA FIFO
Default>>>                                            from memory. While receiving data from the SCSI
                                                      bus, the counter is decremented as data is written
0     0     0        0    0    0    0    0            to memory from the SYM53C810A. The DBC
                                                      counter is decremented each time that data is trans-
Bits 7-0 DF7-DF0 (DMA FIFO)                           ferred on the PCI bus. It is decremented by an
    Writing to this register writes data to the       amount equal to the number of bytes that were
    appropriate byte lane of the DMA FIFO as          transferred.
    determined by the FBL bits in the CTEST4
    register. Reading this register unloads data      The maximum number of bytes that can be trans-
    from the appropriate byte lane of the DMA         ferred in any one Block Move command is
    FIFO as determined by the FBL bits in the         16,777,215 bytes. The maximum value that can be
    CTEST4 register. Data written to the FIFO is      loaded into the DBC register is FFFFFFh. If the
    loaded into the top of the FIFO. Data read out    instruction is a Block Move and a value of 000000h
    of the FIFO is taken from the bottom. To pre-     is loaded into the DBC register, an illegal instruc-
    vent DMA data from being corrupted, this reg-     tion interrupt will occur if the SYM53C810A is not
    ister should not be accessed before starting or   in target role, Command phase.
    restarting SCRIPTS operation. This register
    should only be written when testing the DMA       The DBC register is also used to hold the least sig-
    FIFO using the CTEST4 register. Writes to         nificant 24 bits of the first dword of a SCRIPTS
    this register while the test mode is not enabled  fetch, and to hold the offset value during table indi-
    will have unexpected results.                     rect I/O SCRIPTS. For a complete description, see
                                                      Chapter Six, "Instruction Set of the I/O Proces-
                                                      sor." The power-up value of this register is indeter-
                                                      minate.

5-28                                                  SYM53C810A Data Manual
                                                      Operating Registers

Register 27 (A7)                                      Registers 28-2B (A8-AB)
DMA Command (DCMD)                                    DMA Next Address (DNAD)
Read/Write                                            Read/Write

This 8-bit register determines the instruction for    This 32-bit register contains the general purpose
the SYM53C810A to execute. This register has a        address pointer. At the start of some SCRIPTS op-
different format for each instruction. For a com-     erations, its value is copied from the DSPS register.
plete description, see Chapter Six, "Instruction Set  Its value may not be valid except in certain abort
of the I/O Processor."                                conditions. The default value of this register is zero.

SYM53C810A Data Manual                                5-29
Operating Registers

Registers 2C-2F (AC-AF)                                 Registers 30-33 (B0-B3)
DMA SCRIPTS Pointer (DSP)                               DMA SCRIPTS Pointer Save (DSPS)
Read/Write                                              Read/Write

The CPU writes the address of the first SCRIPTS         This register contains the second dword of a
instruction to this register to begin SCSI SCRIPTS      SCRIPTS instruction. It is overwritten each time a
operation. In normal SCRIPTS operation, once the        SCRIPTS instruction is fetched. When a
starting address of the first SCRIPTS instruction is    SCRIPTS interrupt instruction is executed, this
written to this register, SCRIPTS instructions are      register holds the interrupt vector. The power-up
automatically fetched and executed until an inter-      value of this register is indeterminate.
rupt condition occurs.

In single-step mode, there is a single step interrupt
after each instruction is executed. The DSP register
does not need to be written with the next address,
but the Start DMA bit (bit 2, DCNTL register)
must be set each time the step interrupt occurs to
fetch and execute the next SCRIPTS command.
When writing this register eight bits at a time, writ-
ing the upper eight bits begins execution of the
SCSI SCRIPTS. The default value of this register
is zero.

5-30                                                    SYM53C810A Data Manual
                                                                               Operating Registers

Registers 34-37 (B4-B7)                             Register 38 (B8)
Scratch Register A (SCRATCH A)                      DMA Mode (DMODE)
Read/Write                                          Read/Write

This is a general purpose, user-definable scratch   BL1  BL0    SIOM DIOM ERL ERMP BOF   MAN
pad register. Apart from CPU access, only Register
Read/Write and Memory Moves into the                7       6   5  4  3        2      1  0
SCRATCH register will alter its contents. The
power-up value of this register is indeterminate.   Default>>>

The SYM53C810A cannot fetch SCRIPTS in-             0       0   0  0  0        0      0  0
structions from this location.
                                                    Bit 7-6 BL1-BL0 (Burst length)

                                                         BL1 BL0 Burst Length

                                                         0      0  2- transfer burst

                                                         0      1  4- transfer burst

                                                         1      0  8-transfer burst

                                                         1      1  16-transfer burst

                                                       These bits control the maximum number of
                                                       transfers performed per bus ownership, regard-
                                                       less of whether the transfers are back-to-back,
                                                       burst, or a combination of both. The
                                                       SYM53C810A asserts the Bus Request (REQ/
                                                       ) output when the DMA FIFO can accommo-
                                                       date a transfer of at least one burst size of data.
                                                       Bus Request (REQ/) is also asserted during
                                                       start-of-transfer and end-of-transfer cleanup
                                                       and alignment, even though less than a full
                                                       burst of transfers may be performed. The
                                                       SYM53C810A inserts a "fairness delay" of
                                                       four CLKs between burst-length transfers (as
                                                       set in BL1-0) during normal operation. The
                                                       fairness delay is not inserted during PCI retry
                                                       cycles. This gives the CPU and other bus mas-
                                                       ter devices the opportunity to access the PCI
                                                       bus between bursts.

                                                    Bit 5 SIOM (Source I/O-Memory Enable)
                                                        This bit is defined as an I/O Memory Enable
                                                        bit for the source address of a Memory Move
                                                        or Block Move Command. If this bit is set,
                                                        then the source address is in I/O space; and if
                                                        reset, then the source address is in memory
                                                        space.

SYM53C810A Data Manual                                                                   5-31
Operating Registers

      This function is useful for register-to-memory    accessed in a subsequent bus ownership. If the
      operations using the Memory Move instruc-         instruction is a table indirect block move type,
      tion when the SYM53C810A is I/O mapped.           the chip will access the remaining two dwords
      Bits 4 and 5 of the CTEST2 register can be        in a subsequent bus ownership, thereby fetch-
      used to determine the configuration status of     ing the four dwords required in two bursts of
      the SYM53C810A.                                   two dwords each.

Bit 4 DIOM (Destination I/O-Memory                      Bit 0 MAN (Manual Start Mode)
             Enable)                                        Setting this bit prevents the SYM53C810A
                                                            from automatically fetching and executing
    This bit is defined as an I/O Memory Enable             SCSI SCRIPTS when the DSP register is writ-
    bit for the destination address of a Memory             ten. When this bit is set, the Start DMA bit in
    Move or Block Move Command. If this bit is              the DCNTL register must be set to begin
    set, then the destination address is in I/O             SCRIPTS execution. Clearing this bit causes
    space; and if reset, then the destination address       the SYM53C810A to automatically begin
    is in memory space.                                     fetching and executing SCSI SCRIPTS when
                                                            the DSP register is written. This bit is not nor-
    This function is useful for memory­to­register          mally used for SCSI SCRIPTS operations.
    operations using the Memory Move instruc-
    tion when the SYM53C810A is I/O mapped.
    Bits 4 and 5 of the CTEST2 register can be
    used to determine the configuration status of
    the SYM53C810A.

Bit 3 ERL (Enable Read Line)
    This bit enables a PCI Read Line command. If
    PCI cache mode is enabled by setting bits in
    the PCI Cache Line Size register, the chip
    issues a Read Line command on all read cycles
    if other conditions are met. For more informa-
    tion on these conditions, refer to Chapter 3.

ERMP (Enable Read Multiple)
    This bit, when set, will cause Read Multiple
    commands to be issued on the PCI bus after
    certain conditions have been met. These condi-
    tions are described in Chapter 3.

Bit 1 BOF (Burst Op Code Fetch Enable)
    Setting this bit causes the SYM53C810A to
    fetch instructions in burst mode, if the Burst
    Disable bit (CTEST4, bit7) is cleared. Specifi-
    cally, the chip will burst in the first two dwords
    of all instructions using a single bus ownership.
    If the instruction is a memory-to-memory
    move type, the third dword will be accessed in
    a subsequent bus ownership. If the instruction
    is an indirect type, the additional dword will be

5-32                                                    SYM53C810A Data Manual
                                                        Operating Registers

Register 39 (B9)                                        Register 3A (BA)
DMA Interrupt Enable (DIEN)                             Scratch Byte Register (SBR)
Read/Write                                              Read/Write

RES MDPE    BF          ABRT SSI  SIR  RES  IID         This is a general purpose register. Apart from CPU
                                                        access, only Register Read/Write and Memory
7      6    5           4  3      2    1    0           Moves into this register will alter its contents. The
                                                        default value of this register is zero. This register
Default>>>                                              was called the DMA Watchdog Timer on previous
                                                        SYM53C8XX family products.
X      0    0           0  0      0    X    0

This register contains the interrupt mask bits corre-
sponding to the interrupting conditions described
in the DSTAT register. An interrupt is masked by
clearing the appropriate mask bit. Masking an in-
terrupt prevents IRQ/ from being asserted for the
corresponding interrupt, but the status bit will still
be set in the DSTAT register. Masking an interrupt
will not prevent the ISTAT DIP from being set. All
DMA interrupts are considered fatal, therefore
SCRIPTS will stop running when a DMA interrupt
occurs, whether or not the interrupt is masked. Set-
ting a mask bit enables the assertion of IRQ/ for the
corresponding interrupt. (A masked non-fatal in-
terrupt will not prevent un-masked or fatal inter-
rupts from getting through; interrupt stacking
begins when either the ISTAT SIP or DIP bit is
set.)

The SYM53C810A IRQ/ output is latched; once
asserted, it will remain asserted until the interrupt
is cleared by reading the appropriate status register.
Masking an interrupt after the IRQ/ output is as-
serted will not cause IRQ/ to be deasserted.

For more information on interrupts, see Chapter
Two, "Functional Description."

Bit 7 Reserved

Bit 6 MDPE (Master Data Parity Error)

Bit 5 BF (Bus fault)

Bit 4 ABRT (Aborted)

Bit 3 SSI (Single step interrupt)

Bit 2       SIR (SCRIPTS interrupt
            instruction received

Bit 1 Reserved

Bit 0 IID (Illegal instruction detected)

SYM53C810A Data Manual                                  5-33
Operating Registers

Register 3B (BB)                                        Bit 3 IRQM (IRQ Mode)
DMA Control (DCNTL)                                         When set, this bit enables a totem pole driver
Read/Write                                                  for the IRQ pin. When reset, this bit enables an
                                                            open drain driver for the IRQ pin with a inter-
CLSE PFF    PFEN SSM IRQM STD  IRQD COM                     nal weak pull-up. This bit is reset at power up.

7     6     5        4  3  2   1  0                     Bit 2 STD (Start DMA operation)
                                                            The SYM53C810A fetches a SCSI SCRIPTS
Default>>>                                                  instruction from the address contained in the
                                                            DSP register when this bit is set. This bit is
0     0     0        0  0  0   0  0                         required if the SYM53C810A is in one of the
                                                            following modes:
Bit 7 CLSE (Cache Line Size Enable)
    Setting this bit enables the SYM53C810A to              1. Manual start mode ­ Bit 0 in the DMODE
    sense and react to cache line boundaries set up              register is set
    by the DMODE or PCI Cache Line Size regis-
    ter, whichever contains the smaller value.              2. Single-step mode ­ Bit 4 in the DCNTL
    Clearing this bit disables the cache line size               register is set
    logic and the SYM53C810A monitors the
    cache line size via the DMODE register.                 When the SYM53C810A is executing
                                                            SCRIPTS in manual start mode, the Start
Bit 6 PFF (Pre-Fetch Flush)                                 DMA bit needs to be set to start instruction
    Setting this bit will cause the pre-fetch unit to       fetches. This bit will remain set until an inter-
    flush its contents. The bit will reset after the        rupt occurs. When the SYM53C810A is in sin-
    flush is complete.                                      gle-step mode, the Start DMA bit needs to be
                                                            set to restart execution of SCRIPTS after a sin-
Bit 5 PFEN (Pre-fetch Enable)                               gle-step interrupt.
    Setting this bit enables the pre-fetch unit if the
    burst size is equal to or greater than four. For    Bit 1 IRQD (IRQ Disable)
    more information on SCRIPTS instruction                 Setting this bit tristates the IRQ pin; clearing
    prefetching, see Chapter 2.                             the bit enables normal operation.When bit 1 in
                                                            this register is set, the IRQ/ pin will not be
Bit 4 SSM (Single-step mode)                                asserted when an interrupt condition occurs.
    Setting this bit causes the SYM53C810A to               The interrupt is not lost or ignored, but merely
    stop after executing each SCRIPTS instruc-              masked at the pin. Clearing this bit when an
    tion, and generate a single step interrupt.             interrupt is pending will immediately cause the
    When this bit is clear the SYM53C810A will              IRQ/ pin to assert. As with any register other
    not stop after each instruction; instead it con-        than ISTAT, this register cannot be accessed
    tinues fetching and executing instructions until        except by a SCRIPTS instruction during
    an interrupt condition occurs. This bit should          SCRIPTS execution.
    be clear for normal SCSI SCRIPTS operation.
    To restart the SYM53C810A after it generates
    a SCRIPTS Step interrupt, read the ISTAT
    and DSTAT registers to recognize and clear
    the interrupt; then set the START DMA bit in
    this register.

5-34                                                    SYM53C810A Data Manual
                                                      Operating Registers

Bit 0 COM (53C700 compatibility)                      Register 3C-3F (BC-BF)
    When this bit is clear, the SYM53C810A will       Adder Sum Output (ADDER)
    behave in a manner compatible with the            Read Only
    SYM53C700; selection/reselection IDs will be
    stored in both the SSID and SFBR registers.       This register contains the output of the internal
                                                      adder, and is used primarily for test purposes. The
    When this bit is set, the ID will be stored only  power-up value for this register is indeterminate.
    in the SSID register, protecting the SFBR from
    being overwritten if a selection/reselection
    occurs during a DMA register-to-register oper-
    ation.

    This bit is not affected by a software reset.

SYM53C810A Data Manual                                5-35
Operating Registers

Register 40 (C0)                                     Bit 4 RSL (Reselected)
SCSI Interrupt Enable Zero (SIEN0)                       This bit controls whether an interrupt occurs
Read/Write                                               when the SYM53C810A has been reselected
                                                         by a SCSI initiator device. The Enable
M/A   CMP   SEL      RSL  SGE  UDC  RST  PAR             Response to Reselection bit in the SCID regis-
                                                         ter must be set for this to occur.
7     6     5        4    3    2    1    0
                                                     Bit 3 SGE (SCSI Gross Error)
Default>>>                                               This bit controls whether an interrupt occurs
                                                         when the SYM53C810A detects a SCSI Gross
0     0     0        0    0    0    0    0               Error. The following conditions are considered
                                                         SCSI Gross Errors:
This register contains the interrupt mask bits that
correspond to the interrupting conditions described      1. Data underflow - the SCSI FIFO was read
in the SIST0 register. An interrupt is masked by              when no data was present.
clearing the appropriate mask bit. For more infor-
mation on interrupts, see Chapter 2.                     2. Data overflow - the SCSI FIFO was
                                                              written to while full.
Bit 7 M/A (SCSI Phase Mismatch -
             Initiator Mode; SCSI ATN                    3. Offset underflow - in target mode, a
             Condition - Target Mode)                         SACK/ pulse was received before the
                                                              corresponding SREQ/ was sent.
    In initiator mode, this bit controls whether an
    interrupt occurs when the SCSI phase asserted        4. Offset overflow - in initiator mode, an
    by the target and sampled during SREQ/ does               SREQ/ pulse was received which caused
    not match the expected phase in the SOCL                  the maximum offset (Defined by the
    register. This expected phase is automatically            MO3-0 bits in the SXFER register) to be
    written by the SCSI SCRIPTS program. In                   exceeded.
    target mode, this bit is set when the initiator
    has asserted SATN/. See the Disable Halt on          5. In initiator mode, a phase change occurred
    Parity Error or SATN/ Condition bit in the                with an outstanding SREQ/SACK offset.
    SCNTL1 register for more information on
    when this status is actually raised.                 6. Residual data in SCSI FIFO - a transfer
                                                              other than synchronous data receive was
Bit 6 CMP (Function Complete)                                 started with data left in the SCSI
    This bit controls whether an interrupt occurs             synchronous receive FIFO.
    when full arbitration and selection sequence
    has completed.                                   Bit 2 UDC (Unexpected Disconnect)
                                                         This bit controls whether an interrupt occurs
Bit 5 SEL (Selected)                                     in the case of an unexpected disconnect. This
    This bit controls whether an interrupt occurs        condition only occurs in initiator mode. It hap-
    when the SYM53C810A has been selected by             pens when the target to which the
    a SCSI target device. The Enable Response to         SYM53C810A is connected disconnects from
    Selection bit in the SCID register must be set       the SCSI bus unexpectedly. See the SCSI Dis-
    for this to occur.                                   connect Unexpected bit in the SCNTL2 regis-
                                                         ter for more information on expected versus
                                                         unexpected disconnects. Any disconnect in low
                                                         level mode causes this condition.

5-36                                                 SYM53C810A Data Manual
                                                                                 Operating Registers

Bit 1 RST (SCSI Reset Condition)                    Register 41 (C1)
    This bit controls whether an interrupt occurs   SCSI Interrupt Enable One (SIEN1)
    when the SRST/ signal has been asserted by      Read/Write
    the SYM53C810A or any other SCSI device.
    Note that this condition is edge-triggered, so  RES  RES    RES    RES  RES  STO  GEN  HTH
    that multiple interrupts cannot occur because
    of a single SRST/ pulse.                        7    6      5      4    3    2    1    0

Bit 0 PAR (SCSI Parity Error)                       Default>>>
    This bit controls whether an interrupt occurs
    when the SYM53C810A detects a parity error      X    X      X      X    X    0    0    0
    while receiving or sending SCSI data. See the
    Disable Halt on Parity Error or SATN/ Condi-    This register contains the interrupt mask bits corre-
    tion bits in the SCNTL1 register for more       sponding to the interrupting conditions described
    information on when this condition will actu-   in the SIST1 register. An interrupt is masked by
    ally be raised.                                 clearing the appropriate mask bit. For more infor-
                                                    mation on interrupts, refer to Chapter 2, "Func-
                                                    tional Description."

                                                    Bits 7-3 Reserved

                                                    Bit 2 STO (Selection or Reselection Time-
                                                                 out)

                                                        This bit controls whether an interrupt occurs
                                                        when the SCSI device which the
                                                        SYM53C810A was attempting to select or
                                                        reselect did not respond within the pro-
                                                        grammed time-out period. See the description
                                                        of the STIME0 register bits 3-0 for more infor-
                                                        mation on the time-out timer.

                                                    Bit 1 GEN (General Purpose Timer
                                                                 Expired)

                                                        This bit controls whether an interrupt occurs
                                                        when the general purpose timer has expired.
                                                        The time measured is the time between
                                                        enabling and disabling of the timer. See the
                                                        description of the STIME1 register, bits 3-0,
                                                        for more information on the general purpose
                                                        timer.

SYM53C810A Data Manual                                                                     5-37
Operating Registers

Bit 0 HTH (Handshake to Handshake                  Register 42 (C2)
             timer Expired)                        SCSI Interrupt Status Zero (SIST0)
                                                   Read Only
    This bit controls whether an interrupt occurs
    when the handshake-to-handshake timer has      M/A  CMP    SEL  RSL  SGE  UDC  RST  PAR
    expired. The time measured is the SCSI
    Request to Request (target) or Acknowledge to  7    6      5    4    3    2    1    0
    Acknowledge (initiator) period. See the
    description of the STIME0 register, bits 7-4,  Default>>>
    for more information on the handshake-to-
    handshake timer.                               0    0      0    0    0    0    0    0

                                                   Reading the SIST0 register returns the status of the
                                                   various interrupt conditions, whether or not they
                                                   are enabled in the SIEN0 register. Each bit set in-
                                                   dicates that the corresponding condition has oc-
                                                   curred. Reading the SIST0 will clear the interrupt
                                                   status.

                                                   Reading this register will clear any bits that are set
                                                   at the time the register is read, but will not neces-
                                                   sarily clear the register because additional inter-
                                                   rupts may be pending (the SYM53C810A stacks
                                                   interrupts). SCSI interrupt conditions may be indi-
                                                   vidually masked through the SIEN0 register.

                                                   When performing consecutive 8-bit reads of the
                                                   DSTAT, SIST0, and SIST1 registers (in any or-
                                                   der), insert a delay equivalent to 12 CLK periods
                                                   between the reads to ensure the interrupts clear
                                                   properly. Also, if reading the registers when both
                                                   the ISTAT SIP and DIP bits may not be set, the
                                                   SIST0 and SIST1 registers should be read before
                                                   the DSTAT register to avoid missing a SCSI inter-
                                                   rupt. For more information on interrupts, refer to
                                                   Chapter 2, "Functional Description."

                                                   Bit 7 M/A (Initiator Mode: Phase Mis-
                                                                match; Target Mode: SATN/ Active)

                                                       In initiator mode, this bit is set if the SCSI
                                                       phase asserted by the target does not match the
                                                       instruction.The phase is sampled when SREQ/
                                                       is asserted by the target. In target mode, this
                                                       bit is set when the SATN/ signal is asserted by
                                                       the initiator.

                                                   Bit 6 CMP (Function Complete)
                                                       This bit is set when an arbitration only or full
                                                       arbitration sequence has completed.

5-38                                                                          SYM53C810A Data Manual
                                                     Operating Registers

Bit 5 SEL (Selected)                                     6. Residual data in the Synchronous data
    This bit is set when the SYM53C810A is                    FIFO - a transfer other than synchronous
    selected by another SCSI device. The Enable               data receive was started with data left in the
    Response to Selection bit must have been set in           synchronous data FIFO.
    the SCID register (and the RESPID register
    must hold the chip's ID) for the                 Bit 2 UDC (Unexpected Disconnect)
    SYM53C810A to respond to selection                   This bit is set when the SYM53C810A is oper-
    attempts.                                            ating in initiator mode and the target device
                                                         unexpectedly disconnects from the SCSI bus.
Bit 4 RSL (Reselected)                                   This bit is only valid when the SYM53C810A
    This bit is set when the SYM53C810A is rese-         operates in the initiator mode. When the
    lected by another SCSI device. The Enable            SYM53C810A operates in low level mode, any
    Response to Reselection bit must have been set       disconnect will cause an interrupt, even a valid
    in the SCID register (and the RESPID register        SCSI disconnect. This bit will also be set if a
    must hold the chip's ID) for the                     selection time-out occurs (it may occur before,
    SYM53C810A to respond to reselection                 at the same time, or stacked after the STO
    attempts.                                            interrupt, since this is not considered an
                                                         expected disconnect).
Bit 3 SGE (SCSI Gross Error)
    This bit is set when the SYM53C810A              Bit 1 RST (SCSI RST/ Received)
    encounters a SCSI Gross Error Condition.             This bit is set when the SYM53C810A detects
    The following conditions can result in a SCSI        an active SRST/ signal, whether the reset was
    Gross Error Condition:                               generated external to the chip or caused by the
                                                         Assert SRST/ bit in the SCNTL1 register.This
    1. Data Underflow - the SCSI FIFO register           SYM53C810A SCSI reset detection logic is
         was read when no data was present.              edge-sensitive, so that multiple interrupts will
                                                         not be generated for a single assertion of the
    2. Data Overflow - too many bytes were               SRST/ signal.
         written to the SCSI FIFO or the
         synchronous offset caused the SCSI FIFO     Bit 0 PAR (Parity Error)
         to be overwritten.                              This bit is set when the SYM53C810A detects
                                                         a parity error while receiving SCSI data. The
    3. Offset Underflow - the SYM53C810A is              Enable Parity Checking bit (bit 3 in the
         operating in target mode and a SACK/            SCNTL0 register) must be set for this bit to
         pulse is received when the outstanding          become active. The SYM53C810A always gen-
         offset is zero.                                 erates parity when sending SCSI data.

    4. Offset Overflow - the other SCSI device
         sent a SREQ/ or SACK/ pulse with data
         which exceeded the maximum
         synchronous offset defined by the SXFER
         register.

    5. A phase change occurred with an
         outstanding synchronous offset when the
         SYM53C810A was operating as an
         initiator.

SYM53C810A Data Manual                               5-39
Operating Registers

Register 43 (C3)                                      Register 44 (C4)
SCSI Interrupt Status One (SIST1)                     SCSI Longitudinal Parity (SLPAR)
Read Only                                             Read/Write

RES   RES   RES      RES  RES  STO  GEN  HTH          This register performs a bytewise longitudinal par-
                                                      ity check on all SCSI data received or sent through
7     6     5        4    3    2    1    0            the SCSI core. If one of the bytes received or sent
                                                      (usually the last) is the set of correct even parity
Default>>>                                            bits, SLPAR should go to zero (assuming it started
                                                      at zero). As an example, suppose that the following
X     X     X        X    X    0    0    0            three data bytes and one check byte are received
                                                      from the SCSI bus (all signals are shown active
Reading the SIST1 register returns the status of the  high):
various interrupt conditions, whether or not they
are enabled in the SIEN1 register. Each bit that is
set indicates the corresponding condition has oc-
curred.

Reading the SIST1 register will clear the interrupt
condition.

Bits 7-3 Reserved                                     Data Bytes   Running SLPAR
                                                      ---
Bit 2 STO (Selection or Reselection                   1. 11001100  00000000
             Time-out)                                2. 01010101  11001100 (XOR of word 1)
                                                      3. 00001111  10011001 (XOR of word 1 and 2)
    This bit is set when the SCSI device which the                 10010110 (XOR of word 1, 2 and 3)
    SYM53C810A53C810A was attempting to               4. 10010110  Even Parity >>>10010110
    select or reselect did not respond within the                  00000000
    programmed time-out period. See the descrip-
    tion of the STIME0 register, bits 3-0, for more   A one in any bit position of the final SLPAR value
    information on the time-out timer.                would indicate a transmission error.

Bit 1 GEN (General Purpose Timer                      The SLPAR register can also be used to generate
             Expired)                                 the check bytes for SCSI send operations. If the
                                                      SLPAR register contains all zeros prior to sending
    This bit is set when the general purpose timer    a block move, it will contain the appropriate check
    has expired. The time measured is the time        byte at the end of the block move. This byte must
    between enabling and disabling of the timer.      then be sent across the SCSI bus.
    See the description of the STIME1 register,
    bits 3-0, for more information on the general     Note: writing any value to this register resets it to
    purpose timer.                                             zero.

Bit 0 HTH (Handshake-to-Handshake                     The longitudinal parity checks are meant to provide
             Timer Expired)                           an added measure of SCSI data integrity and are
                                                      entirely optional. This register does not latch SCSI
    This bit is set when the handshake-to-hand-       selection/reselection IDs under any circumstances.
    shake timer has expired. The time measured is     The default value of this register is zero.
    the SCSI Request to Request (target) or
    Acknowledge to Acknowledge (initiator)
    period. See the description of the STIME0
    register, bits 7-4, for more information on the
    handshake-to-handshake timer.

5-40                                                               SYM53C810A Data Manual
                                                                                   Operating Registers

Register 46 (C6)                                        Register 47 (C7)
Memory Access Control (MACNTL)                          General Purpose Pin Control (GPCNTL)
Read/Write                                              Read/Write

TYP3 TYP2   TYP1        TYP0  DWR  DRD PSCPT SCPTS      ME  FE      RES  RES  RES  RES GPIO1 GPIO0
              5           4     3
7  6                               2  1           0     7   6       5    4    3    2  1  0
              0           0     0
Default>>>                                              Default>>>

0  1                               0  0           0     0   0       X    0    1    1  1  1

Bits 7-4 TYP3-0 (Chip Type)                             This register is used to determine if the pins con-
    These bits identify the chip type for software      trolled by the General Purpose register (GPREG)
    purposes.                                           are inputs or outputs. Bits 1-0 in GPCNTL corre-
                                                        spond to bits 1-0 in the GPREG register. When the
Bits 3 through 0 of this register are used to deter-    bits are enabled as inputs, an internal pull-up is also
mine if an external bus master access is to local or    enabled.
far memory. When bits 3 through 0 are set, the cor-
responding access is considered local and the           Bit 7 Master Enable
MAC/_TESTOUT pin is driven high. When these                 The internal bus master signal will be pre-
bits are clear, the corresponding access is to far          sented on GPIO1 if this bit is set, regardless of
memory and the MAC/_TESTOUT pin is driven                   the state of Bit 1 (GPIO1_EN).
low. This function is enabled after a Transfer Con-
trol SCRIPTS instruction is executed.                   Bit 6 Fetch Enable
                                                            The internal op code fetch signal will be pre-
Bit 3 DWR (DataWR)                                          sented on GPIO0 if this bit is set, regardless of
    This bit is used to define if a data write is con-      the state of Bit 0 (GPIO0_EN).
    sidered local memory access.

                                                        Bit 5 Reserved

Bit 2 DRD (DataRD)                                      Bits 1-0 GPIO1_EN­ GPIO0_EN (GPIO
    This bit is used to define if a data read is con-                Enable)
    sidered local memory access.
                                                            These bits power up set, causing the GPIO1
Bit 1 PSCPT (Pointer SCRIPTS)                               and GPIO0 pins to become inputs. Resetting
    This bit is used to define if a pointer to a            these bits causes GPIO1-0 to become outputs.
    SCRIPTS indirect or table indirect fetch is
    considered local memory access.

Bit 0 SCPTS (SCRIPTS)
    This bit is used to define if a SCRIPTS fetch is
    considered local memory access.

SYM53C810A Data Manual                                                                   5-41
Operating Registers

Register 48 (C8)                                       HTH 7-4, SEL 3-0,  Minimum Time-out
SCSI Timer Zero (STIME0)                                    GEN 3-0
Read /Write

HTH   HTH   HTH      HRH  SEL  SEL  SEL  SEL                              40 MHz     50 MHz

7     6     5        4    3    2    1    0             0000               Disabled   Disabled

Default>>>

0     0     0        0    0    0    0    0             0001               125 µs     100 µs

                                                       0010               250 µs     200 µs

Bits 7-4 HTH (Handshake-to-Handshake                   0011               500 µs     400 µs
             Timer Period)
                                                       0100               1 ms       800 µs
    These bits select the handshake-to-handshake
    time-out period, the maximum time between          0101               2 ms       1.6 ms
    SCSI handshakes (SREQ/ to SREQ/ in target
    mode, or SACK/ to SACK/ in initiator mode).        0110               4 ms       3.2 ms
    When this timing is exceeded, an interrupt is
    generated and the HTH bit in the SIST1 regis-      0111               8 ms       6.4 ms
    ter is set. The following table contains time-out
    periods for the Handshake-to-Handshake             1000               16 ms      12.8 ms
    Timer, the Selection/Reselection Timer (bits 3-
    0), and the General Purpose Timer (STIME1          1001               32 ms      25.6 ms
    bits 3-0). For a more detailed explanation of
    interrupts, refer to Chapter 2, "Functional        1010               64 ms      51.2 ms
    Description."
                                                       1011               128 ms     102.4 ms

                                                       1100               256 ms     204.8 ms

                                                       1101               512 ms     409.6 ms

                                                       1110               1.024 sec  819.2 ms

                                                       1111               2.048 sec  1.6384 sec

                                                       These values will be correct if the CCF bits in the SCNTL3
                                                       register are set according to the valid combinations in the bit
                                                       description.

                                                       Bits 3-0 SEL (Selection Time-Out)
                                                           These bits select the SCSI selection/reselection
                                                           time-out period. When this timing (plus the
                                                           200 µs selection abort time) is exceeded, the
                                                           STO bit in the SIST1 register is set. For a
                                                           more detailed explanation of interrupts, refer
                                                           to Chapter 2, "Functional Description."

5-42                                                                      SYM53C810A Data Manual
                                                      Operating Registers

Register 49 (C9)                                      Register 4A (CA)
SCSI Timer One (STIME1)                               Response ID (RESPID)
Read/Write                                            Read/Write

RES  RES    RES         RES GEN3 GEN2 GEN1 GEN0       This register contains the IDs that the chip re-
                                                      sponds to on the SCSI bus. Each bit represents one
7    6      5           4  3  2  1  0                 possible ID with the most significant bit represent-
                                                      ing ID 7 and the least significant bit representing
Default>>>                                            ID 0. The SCID register still contains the chip ID
                                                      used during arbitration. The chip can respond to
X    X      X           X  0  0  0  0                 more than one ID because more than one bit can be
                                                      set in the RESPID register. However, the chip can
Bits 7-4 Reserved                                     arbitrate with only one ID value in the SCID regis-
                                                      ter.
Bits 3-0 GEN3-0 (General Purpose Timer
             Period)

    These bits select the period of the general pur-
    pose timer. The time measured is the time
    between enabling and disabling of the timer.
    When this timing is exceeded, the GEN bit in
    the SIST1 register is set. Refer to the table
    under STIME0, bits 3-0, for the available
    time-out periods.

Note: to reset a timer before it has expired and to
         obtain repeatable delays, the time value
         must be written to zero first, and then
         written back to the desired value. This is
         also required when changing from one time
         value to another. See Chapter 2,
         "Functional Description," for an
         explanation of how interrupts are
         generated when the timers expire.

SYM53C810A Data Manual                                5-43
Operating Registers

Register 4C (CC)                                      Bit 1 SOZ (SCSI Synchronous Offset
SCSI Test Zero (STEST0)                                            Zero)
Read Only
                                                           This bit indicates that the current synchronous
RES   SSAID SSAID SSAID  SLT  ART  SOZ SOM                SREQ/SACK offset is zero. This bit is not
                                                          latched and may change at any time. It is used
      2     1        0                                    in low level synchronous SCSI operations.
                                                          When this bit is set, the SYM53C810A, as an
7     6     5        4   3    2    1  0                   initiator, is waiting for the target to request
                                                          data transfers. If the SYM53C810A is a target,
Default>>>                                                then the initiator has sent the offset number of
                                                          acknowledges.
X     X     X        X   0    X    1  1
                                                      Bit 0 SOM (SCSI Synchronous Offset
Bit 7 Reserved                                                     Maximum)

Bits 6-4 SSAID (SCSI Selected As ID)                      This bit indicates that the current synchronous
    These bits contain the encoded value of the           SREQ/SACK offset is the maximum specified
    SCSI ID that the SYM53C810A was selected              by bits 3-0 in the SCSI Transfer register. This
    or reselected as during a SCSI selection or           bit is not latched and may change at any time.
    reselection phase. These bits are read only and       It is used in low level synchronous SCSI opera-
    contain the encoded value of 0-7 possible IDs         tions. When this bit is set, the SYM53C810A,
    that could be used to select the                      as a target, is waiting for the initiator to
    SYM53C810A. During a SCSI selection or                acknowledge the data transfers. If the
    reselection phase when a valid ID has been put        SYM53C810A is an initiator, then the target
    on the bus, and the 53C810A responds to that          has sent the offset number of requests.
    ID, the "selected as" ID is written into these
    bits.

Bit 3 SLT (Selection response logic test)
    This bit is set when the SYM53C810A is ready
    to be selected or reselected. This does not take
    into account the bus settle delay of 400 ns.
    This bit is used for functional test and fault
    purposes.

Bit 2 ART (Arbitration Priority Encoder
             Test)

    This bit will always be set when the
    SYM53C810A exhibits the highest priority ID
    asserted on the SCSI bus during arbitration. It
    is primarily used for chip level testing, but it
    may be used during low level mode operation
    to determine if the SYM53C810A has won
    arbitration.

5-44                                                  SYM53C810A Data Manual
                                                                               Operating Registers

Register 4D (CD)                                    Register 4E (CE)
SCSI Test One (STEST1)                              SCSI Test Two (STEST2)
Read/Write                                          Read/Write

SCLK SISO   RES         RES  RES  RES  RES  RES     SCE  ROF    RES  SLB  SZM  RES  EXT  LOW

7  6        5           4    3    2    1    0       7    6      5    4    3    2    1    0

Default>>>                                          Default>>>

0  0        X           X    X    X    X    X       0    0      X    0    0    X    0    0

Bit 7 SCLK                                          Bit 7 SCE (SCSI Control Enable)
    This bit, when set, disables the external SCLK      This bit, when set, allows all SCSI control and
    (SCSI Clock) pin, and causes the chip to use        data lines to be asserted through the SOCL
    the PCI clock as the internal SCSI clock. If a      and SODL registers regardless of whether the
    transfer rate of 10 MB/s is to be achieved on       SYM53C810A is configured as a target or ini-
    the SCSI bus, this bit must be cleared and the      tiator.
    chip must be connected to at least a 40 MHz
    external SCLK.                                  Note: this bit should not be set during normal
                                                             operation, since it could cause contention
Bit 6 SISO (SCSI Isolation Mode)                             on the SCSI bus. It is included for
    This bit allows the SYM53C810A to put the                diagnostic purposes only.
    SCSI bi-directional and input pins into a low
    power mode when the SCSI bus is not in use.     Bit 6 ROF (Reset SCSI Offset)
    When this bit is set, the SCSI bus inputs are       Setting this bit clears any outstanding synchro-
    logically isolated from the SCSI bus.               nous SREQ/SACK offset. This bit should be
                                                        set if a SCSI gross error condition occurs, to
Bits 5-0 Reserved                                       clear the offset when a synchronous transfer
                                                        does not complete successfully. The bit auto-
                                                        matically clears itself after resetting the syn-
                                                        chronous offset.

                                                    Bit 5 Reserved

                                                    Bit 4 SLB (SCSI Loopback Mode)
                                                        Setting this bit allows the SYM53C810A to
                                                        perform SCSI loopback diagnostics. That is, it
                                                        enables the SCSI core to simultaneously per-
                                                        form as both initiator and target.

                                                    Bit 3 SZM (SCSI High-Impedance Mode)
                                                         Setting this bit places all the open-drain
                                                        48 mA SCSI drivers into a high-impedance
                                                        state. This is to allow internal loopback mode
                                                        operation without affecting the SCSI bus.

                                                    Bit 2 Reserved

SYM53C810A Data Manual                                                                   5-45
Operating Registers

Bit 1 EXT( Extend SREQ/SACK                              Register 4F (CF)
             filtering)                                  SCSI Test Three (STEST3)
                                                         Read/Write
    Symbios Logic TolerANT SCSI receiver tech-
    nology includes a special digital filter on the      TE  STR     HSC  DSI  RES  TTM  CSF  STW
    SREQ/ and SACK/ pins which will cause
    glitches on deasserting edges to be disregarded.     7   6       5    4    3    2    1    0
    Setting this bit will increase the filtering period
    from 30ns to 60ns on the deasserting edge of         Default>>>
    the SREQ/ and SACK/ signals.
                                                         0   0       0    0    X    0    0    0
Note: this bit must never be set during fast SCSI
         (greater than 5M transfers per second)          Bit 7 TE (TolerANT Enable)
         operations, because a valid assertion could         Setting this bit enables the active negation por-
         be treated as a glitch.                             tion of TolerANT technology. Active negation
                                                             causes the SCSI Request, Acknowledge, Data,
Bit 0 LOW (SCSI Low level Mode)                              and Parity signals to be actively deasserted,
    Setting this bit places the SYM53C810A in                instead of relying on external pull-ups, when
    low level mode. In this mode, no DMA opera-              the SYM53C810A is driving these signals.
    tions occur, and no SCRIPTS execute. Arbi-               Active deassertion of these signals will occur
    tration and selection may be performed by                only when the SYM53C810A is in an informa-
    setting the start sequence bit as described in           tion transfer phase. TolerANT active negation
    the SCNTL0 register. SCSI bus transfers are              should be enabled to improve setup and deas-
    performed by manually asserting and polling              sertion times at fast SCSI timings. Active nega-
    SCSI signals. Clearing this bit allows instruc-          tion is disabled after reset or when this bit is
    tions to be executed in SCSI SCRIPTS mode.               cleared. For more information on TolerANT
                                                             technology, refer to Chapter 1.
Note: it is not necessary to set this bit for access
         to the SCSI bit-level registers (SODL,          Bit 6 STR (SCSI FIFO Test Read)
         SBCL, and input registers).                         Setting this bit places the SCSI core into a test
                                                             mode in which the SCSI FIFO can be easily
                                                             read. Reading the SODL register will cause the
                                                             FIFO to unload.

                                                         Bit 5 HSC (Halt SCSI Clock)
                                                             Asserting this bit causes the internal divided
                                                             SCSI clock to come to a stop in a glitchless
                                                             manner. This bit may be used for test purposes
                                                             or to lower IDD during a power down mode.

5-46                                                                                SYM53C810A Data Manual
                                                          Operating Registers

Bit 4 DSI (Disable Single Initiator                       Register 50 (D0)
             Response)                                    SCSI Input Data Latch (SIDL)
                                                          Read Only
    If this bit is set, the SYM53C810A will ignore
    all bus-initiated selection attempts that employ      This register is used primarily for diagnostic testing,
    the single-initiator option from SCSI-1. In           programmed I/O operation or error recovery. Data
    order to select the SYM53C810A while this bit         received from the SCSI bus can be read from this
    is set, the SYM53C810A's SCSI ID and the              register. Data can be written to the SODL register
    initiator's SCSI ID must both be asserted.This        and then read back into the SYM53C810A by
    bit should be asserted in SCSI-2 systems so           reading this register to allow loopback testing.
    that a single bit error on the SCSI bus will not      When receiving SCSI data, the data will flow into
    be interpreted as a single initiator response.        this register and out to the host FIFO. This register
                                                          differs from the SBDL register; SIDL contains
Bit 3 Reserved                                            latched data and the SBDL always contains exactly
                                                          what is currently on the SCSI data bus. Reading
Bit 2 TTM (Timer Test Mode)                               this register causes the SCSI parity bit to be
    Setting this bit facilitates testing of the selec-    checked, and will cause a parity error interrupt if
    tion time-out, general purpose, and hand-             the data is not valid. The power-up values are inde-
    shake-to-handshake timers by greatly reducing         terminate.
    all three time-out periods. Setting this bit starts
    all three timers and, if the respective bits in the
    SIEN1 register are set, causes the
    SYM53C810A to generate interrupts at time-
    out. This bit is intended for internal manufac-
    turing diagnosis and should not be used.

Bit 1 CSF (Clear SCSI FIFO)
    Setting this bit will cause the "full flags" for the
    SCSI FIFO to be cleared. This empties the
    FIFO. This bit is self-resetting. In addition, the
    SCSI FIFO pointers, the SIDL, SODL, and
    SODR Full bits in the SSTAT0 register are
    cleared.

Bit 0 STW (SCSI FIFO Test Write)
    Setting this bit places the SCSI core into a test
    mode in which the FIFO can easily be written.
    While this bit is set, writes to the SODL regis-
    ter will cause the entire word contained in this
    register to be loaded into the FIFO.Writing the
    least significant byte of the SODL register will
    cause the FIFO to load.

SYM53C810A Data Manual                                    5-47
Operating Registers

Registers 54 (D4)                                       Registers 58 (D8)
SCSI Output Data Latch (SODL)                           SCSI Bus Data Lines (SBDL)
Read/Write                                              Read Only

This register is used primarily for diagnostic testing  This register contains the SCSI data bus status.
or programmed I/O operation. Data written to this       Even though the SCSI data bus is active low, these
register is asserted onto the SCSI data bus by set-     bits are active high. The signal status is not latched
ting the Assert Data Bus bit in the SCNTL1 regis-       and is a true representation of exactly what is on the
ter. This register is used to send data via             data bus at the time the register is read. This regis-
programmed I/O. Data flows through this register        ter is used when receiving data via programmed
when sending data in any mode. It is also used to       I/O. This register can also be used for diagnostic
write to the synchronous data FIFO when testing         testing or in low level mode. The power-up value of
the chip. The power-up value of this register is in-    this register is indeterminate.
determinate.

5-48                                                    SYM53C810A Data Manual
                                                      Operating Registers

Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write)

This is a general purpose user definable scratch pad
register. Apart from CPU access, only Register
Read/Write and Memory Moves directed at the
SCRATCH register will alter its contents. The
power-up values are indeterminate.

The SYM53C810A cannot fetch SCRIPTS in-
structions from this location.

SYM53C810A Data Manual                                5-49
Operating Registers

5-50                 SYM53C810A Data Manual
                                                        Instruction Set of the I/O Processor
                                                                                SCSI SCRIPTS

Chapter 6

Instruction Set of the I/O Processor

After power up and initialization of the                instruction may be written to the DMA SCRIPTS
SYM53C810A, the chip can operate in the low             Pointer register to restart the automatic fetching
level register interface mode, or using SCSI            and execution of instructions.
SCRIPTS.
With the low level register interface, the user has     The SCSI SCRIPTS mode of execution allows the
access to the DMA control logic and the SCSI bus        SYM53C810A to make decisions based on the sta-
control logic. An external processor has access to      tus of the SCSI bus, so that the microprocessor
the SCSI bus signals and the low level DMA sig-         does not have to service all of the interrupts inher-
nals, which allows creation of complicated board        ent in I/O operations.
level test algorithms. The low level interface is use-
ful for backward compatibility with SCSI devices        Given the rich set of SCSI-oriented features
that require certain unique timings or bus              included in the instruction set, and the ability to
sequences to operate properly. Another feature          re-enter the SCSI algorithm at any point, this high
allowed at the low level is loopback testing. In        level interface is all that is required for both normal
loopback mode, the SCSI core can be directed to         and exception conditions. There is no need to
talk to the DMA core to test internal data paths all    switch to low level mode for error recovery.
the way out to the chip's pins.
                                                        Five types of SCRIPTS instructions are imple-
SCSI SCRIPTS                                            mented in the SYM53C810A:

To operate in the SCSI SCRIPTS mode, the                s Block Move--used to move data between the
SYM53C810A requires only a SCRIPTS start                    SCSI bus and memory
address. The start address must be at a dword
(four byte) boundary. This aligns the following         s I/O or Read/Write--causes the SYM53C810A
SCRIPTS at a dword boundary, since all                      to trigger common SCSI hardware sequences,
SCRIPTS are 8 or 12 bytes long. All instructions            or to move registers
are fetched from external memory. The
SYM53C810A fetches and executes its own                 s Transfer Control-- allows SCRIPTS
instructions by becoming a bus master on the host           instructions to make decisions based on real
bus and fetching two or three 32-bit words into its         time SCSI bus conditions
registers. Instructions are fetched until an inter-
rupt instruction is encountered, or until an unex-      s Memory Move-- causes the SYM53C810A to
pected event (such as a hardware error) causes an           execute block moves between different parts of
interrupt to the external processor.                        main memory
Once an interrupt is generated, the SYM53C810A
halts all operations until the interrupt is serviced.   s Load and Store--provides a more efficient way
Then, the start address of the next SCRIPTS                 to move data to/from memory from/to an
                                                            internal register in the chip without using the
SYM53C810A Data Manual                                      Memory Move instruction.

                                                        Each instruction consists of two or three 32-bit
                                                        words. The first 32-bit word is always loaded into
                                                        the DCMD and DBC registers, the second into
                                                        the DSPS register. The third word, used only by
                                                        Memory Move instructions, is loaded into the
                                                        TEMP shadow register. In an indirect I/O or Move
                                                        instruction, the first two 32-bit op code fetches will
                                                        be followed by one or two more 32-bit fetch cycles.

                                                                                                                                     6-1
Instruction Set of the I/O Processor
SCSI SCRIPTS

Sample Operation                                      The process repeats until the internally stored byte
                                                      count has reached zero. The SYM53C810A
The following example describes execution of a        releases the PCI bus and then requests use of the
SCRIPTS instruction.This sample operation is for      PCI bus again for another SCRIPTS instruction
a Block Move instruction. Figure 6-1 illustrates a    fetch cycle, using the incremented stored address
SCRIPTS Initiator Write operation, which uses         maintained in the DMA SCRIPTS Pointer regis-
several Block Move instructions.                      ter. Execution of SCRIPTS instructions continues
                                                      until an error condition occurs or an interrupt
1. The host CPU, through programmed I/O,              SCRIPTS instruction is received. At this point, the
    gives the DMA SCRIPTS Pointer (DSP)               SYM53C810A interrupts the host CPU and waits
    register (in the Operating Register file) the     for further servicing by the host system. It can exe-
    starting address in main memory that points to    cute independent Block Move instructions, speci-
    a SCSI SCRIPTS program for execution.             fying new byte counts and starting locations in
                                                      main memory. In this manner, the SYM53C810A
2. Loading the DSP register causes the                performs scatter/gather operations on data without
    SYM53C810A to request use of the PCI bus          requiring help from the host program, generating a
    to fetch its first instruction from main memory   host interrupt, or requiring an external DMA con-
    at the address just loaded.                       troller to be programmed.

3. The SYM53C810A typically fetches two
    dwords (64 bits) and decodes the high order
    byte of the first dword as a SCRIPTS
    instruction. If the instruction is a Block Move,
    the lower three bytes of the first dword are
    stored and interpreted as the number of bytes
    to be moved. The second dword is stored and
    interpreted as the 32-bit beginning address in
    main memory to which the move is directed.

4. For a SCSI send operation, the SYM53C810A
    waits until there is enough space in the DMA
    FIFO to transfer a programmable size block of
    data. For a SCSI receive operation, it waits
    until enough data is collected in the DMA
    FIFO for transfer to memory.

5. SYM53C810A requests use of the PCI bus
    again, this time for data transfers.

6. When the SYM53C810A is again granted the
    PCI bus, it will execute (as a bus master) a
    burst transfer (programmable size) of data,
    decrement the internally stored remaining byte
    count, increment the address pointer, and then
    release the PCI bus. The SYM53C810A stays
    off the PCI bus until the FIFO can again hold
    (for a write) or has collected (for a read)
    enough data to repeat the process.

6-2                                                   SYM53C810A Data Manual
                                                                                Instruction Set of the I/O Processor
                                                                                                        SCSI SCRIPTS

                           System Processor                       S  Write DSP

                               System Memory                      y

                               SCSI Initiator Write Example       s
                        · select ATN 0, alt_addr
                        · move 1, identify_msg_buf, when MSG_OUT  t  Fetch
                        · move 6, cmd_buf, when CMD
                        · move 512, data_buf, when DATA_OUT       e SCRIPTS     SYM53C810A SCSI
                        · move 1, stat_in_buf, when STATUS
                        · move 1, msg_in_buf, when MSG_IN         m             Bus
                        · move SCNTL2 & 7F to SCNTL2
                        · clear ACK                               B
                        · wait disconnect alt2
                        · int 10                                  u  Data

                                          Data Structure          s
                               Message Buffer
                               Command Buffer
                               Data Buffer
                               Status Buffer

                        Figure 6-1: SCRIPTS Overview

SYM53C810A Data Manual                                                                           6-3
Instruction Set of the I/O Processor
Block Move Instructions

Block Move Instructions                               Indirect
                                                          Use the fetched byte count, but fetch the data
The Block Move SCRIPTS instruction is used to             address from the address in the instruction.
move data between the SCSI bus and memory. For
a Block Move instruction, the SYM53C810A              Command     Byte Count
operates much like a chaining DMA device with a
SCSI controller attached. Figure 6-2 illustrates the              Address of Pointer to Data
register bit values that represent a Block Move
instruction. In Block Move instructions, bits 5 and       Once the data pointer address is loaded, it is
4 (SIOM and DIOM) in the DMODE register                   executed as when the chip operates in the
determine whether the source/destination address          direct mode. This indirect feature allows a
resides in memory or I/O space. When data is              table of data buffer addresses to be specified.
being moved onto the SCSI bus, SIOM controls              Using the SCSI SCRIPTS assembler, the table
whether that data comes from I/O or memory                offset is placed in the SCRIPTS file when the
space. When data is being moved off of the SCSI           program is assembled. Then at the actual data
bus, DIOM controls whether that data goes to I/O          transfer time, the offsets are added to the base
or memory space.                                          address of the data address table by the exter-
                                                          nal processor. The logical I/O driver builds a
First Dword                                               structure of addresses for an I/O rather than
                                                          treating each address individually. This feature
Bits 31-30 Instruction Type-Block Move                    makes it possible to locate SCSI SCRIPTS in a
                                                          PROM.
Bit 29 Indirect Addressing
                                                      Note: indirect and table indirect addressing
    When this bit is cleared, user data is moved to            cannot be used simultaneously; only one
    or from the 32-bit data start address for the              addressing method can be used at a time.
    Block Move instruction. The value is loaded
    into the chip's address register and incre-       Bit 28 Table Indirect
    mented as data is transferred. The address of
    data to be moved is in the second dword of this       When this bit is set, the 24-bit signed value in
    instruction.                                          the start address of the move is treated as a rel-
                                                          ative displacement from the value in the DSA
    When set, the 32-bit user data start address for      register. Both the transfer count and the
    the Block Move is the address of a pointer to         source/destination address are fetched from
    the actual data buffer address. The value at the      this address.
    32-bit start address is loaded into the chip's
    DNAD register via a third dword fetch (4-byte     Command      Not Used
    transfer across the host computer bus).           Don't Care  Table Offset

Direct                                                Use the signed integer offset in bits 23-0 of the
     The byte count and absolute address are as       second four bytes of the instruction, added to
    follows.                                          the value in the DSA register, to fetch first the
                                                      byte count and then the data address. The
     Command               Byte Count                 signed value is combined with the data struc-
              Address of Data                         ture base address to generate the physical
                                                      address used to fetch values from the data
                                                      structure. Sign-extended values of all ones for
                                                      negative values are allowed, but bits 31-24 are
                                                      ignored.

6-4                                                               SYM53C810A Data Manual
                                                                                                 Instruction Set of the I/O Processor
                                                                                                             Block Move Instructions

                        DCMD Register                            DBC Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                          I/O                    24-bit Block Move byte counter
                                       C/D

                                       MSG/

                        Op Code

                        Table Indirect Addressing

                        Indirect Addressing (53C700 compatible)

                           0 - Instruction Type - Block Move
                        0 - Instruction Type - Block Move

                                                     DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                        Figure 6-2: Block Move Instruction Register

SYM53C810A Data Manual                                                                           6-5
Instruction Set of the I/O Processor
Block Move Instructions

     Prior to the start of an I/O, the Data Structure  Target Mode
     Base Address register (DSA) should be loaded
     with the base address of the I/O data structure.  OPC          Instruction Defined
     The address may be any address on a long
     word boundary.                                    0            MOVE

     After a Table Indirect op code is fetched, the    1            Reserved
     DSA is added to the 24-bit signed offset value
     from the op code to generate the address of the   1. The SYM53C810A verifies that it is connected
     required data; both positive and negative off-        to the SCSI bus as a target before executing
     sets are allowed. A subsequent fetch from that        this instruction.
     address brings the data values into the chip.
                                                       2. The SYM53C810A asserts the SCSI phase
     For a MOVE instruction, the 24-bit byte count         signals (SMSG/, SC_D/, and SI_O/) as defined
     is fetched from system memory. Then the 32-           by the Phase Field bits in the instruction.
     bit physical address is brought into the
     SYM53C810A. Execution of the move begins          3. If the instruction is for the command phase,
     at this point.                                        the SYM53C810A receives the first command
                                                           byte and decodes its SCSI Group Code.
     SCRIPTS can directly execute operating sys-
     tem I/O data structures, saving time at the           a) If the SCSI Group Code is either Group 0,
     beginning of an I/O operation. The I/O data                Group 1, Group 2, or Group 5, then the
     structure can begin on any dword boundary                  SYM53C810A overwrites the DBC
     and may cross system segment boundaries.                   register with the length of the Command
                                                                Descriptor Block: 6, 10, or 12 bytes.
     There are two restrictions on the placement of
     pointer data in system memory: the eight bytes        b) If any other Group Code is received, the
     of data in the MOVE instruction must be con-               DBC register is not modified and the
     tiguous, as shown below; and indirect data                 SYM53C810A will request the number of
     fetches are not available during execution of a            bytes specified in the DBC register. If the
     Memory-to-Memory DMA operation.                            DBC register contains 000000h, an illegal
                                                                instruction interrupt is generated.
     00  Byte Count
                                                       4. The SYM53C810A transfers the number of
         Physical Data Address                             bytes specified in the DBC register starting at
                                                           the address specified in the DNAD register.
Bit 27 Op Code
                                                       5. If the SATN/ signal is asserted by the initiator
    This 1-bit field defines the instruction to be         or a parity error occurred during the transfer,
    executed as a block move (MOVE).                       the transfer can optionally be halted and an
                                                           interrupt generated. The Disable Halt on
                                                           Parity Error or ATN bit in the SCNTL1
                                                           register controls whether the SYM53C810A
                                                           will halt on these conditions immediately, or
                                                           wait until completion of the current Move.

6-6                                                                           SYM53C810A Data Manual
                                                                   Instruction Set of the I/O Processor
                                                                               Block Move Instructions

Initiator Mode                                        Bits 26-24 SCSI Phase

OPC                     Instruction Defined               This 3-bit field defines the desired SCSI infor-
                                                          mation transfer phase. When the
0                       Reserved                          SYM53C810A operates in initiator mode,
                                                          these bits are compared with the latched SCSI
1                       MOVE                              phase bits in the SSTAT1 register. When the
                                                          SYM53C810A operates in target mode, the
1. The SYM53C810A verifies that it is connected           SYM53C810A asserts the phase defined in this
    to the SCSI bus as an initiator before executing      field.The following table describes the possible
    this instruction.                                     combinations and the corresponding SCSI
                                                          phase.
2. The SYM53C810A waits for an unserviced
    phase to occur. An unserviced phase is defined    MSG C/D I/O  SCSI Phase
    as any phase (with SREQ/ asserted) for which                   Data out
    the SYM53C810A has not yet transferred data       0  0  0      Data in
    by responding with a SACK/.                                    Command
                                                      0  0  1      Status
3. The SYM53C810A compares the SCSI phase                          Reserved out
    bits in the DCMD register with the latched        0  1  0      Reserved in
    SCSI phase lines stored in the SSTAT1                          Message out
    register. These phase lines are latched when      0  1  1      Message in
    SREQ/ is asserted.
                                                      1  0  0
4. If the SCSI phase bits match the value stored
    in the SSTAT1 register, the SYM53C810A            1  0  1
    will transfer the number of bytes specified in
    the DBC register starting at the address          1  1  0
    pointed to by the DNAD register.
                                                      1  1  1
5. If the SCSI phase bits do not match the value
    stored in the SSTAT1 register, the                Bits 23-0 Transfer Counter
    SYM53C810A generates a phase mismatch
    interrupt and the instruction is not executed.        This 24-bit field specifies the number of data
                                                          bytes to be moved between the SYM53C810A
6. During a Message Out phase, after the                  and system memory. The field is stored in the
    SYM53C810A has performed a Select with                DBC register. When the SYM53C810A trans-
    Attention (or SATN/ has been manually                 fers data to/from memory, the DBC register is
    asserted with a Set ATN instruction), the             decremented by the number of bytes trans-
    SYM53C810A will deassert SATN/ during the             ferred. In addition, the DNAD register is
    final SREQ/SACK handshake of the first move           incremented by the number of bytes trans-
    of Message Out bytes after SATN/ was set.             ferred. This process is repeated until the DBC
                                                          register has been decremented to zero. At that
7. When the SYM53C810A is performing a block              time, the SYM53C810A fetches the next
    move for Message In phase, it will not deassert       instruction.
    the SACK/ signal for the last SREQ/SACK
    handshake. The SACK signal must be cleared            If bit 28 is set, indicating table indirect
    using the Clear SACK I/O instruction.                 addressing, this field is not used. The byte
                                                          count is instead fetched from a table pointed to
                                                          by the DSA register.

SYM53C810A Data Manual                                                           6-7
Instruction Set of the I/O Processor
I/O Instructions

Second Dword                                           I/O Instructions

Bits 31-0 Start Address                                The I/O SCRIPTS instruction causes the
                                                       SYM53C810A to trigger common SCSI hardware
    This 32-bit field specifies the starting address   sequences such as Set/Clear ACK, Set/Clear ATN,
    of the data to be moved to/from memory. This       Set/Clear Target Mode, Select With ATN, or Wait
    field is copied to the DNAD register.When the      for Reselect. Figure 6-3 illustrates the register bit
    SYM53C810A transfers data to or from mem-          values that represent an I/O instruction.
    ory, the DNAD register is incremented by the
    number of bytes transferred.                       First Dword

    When bit 29 is set, indicating indirect address-   Bits 31-30 Instruction Type - I/O Instruction
    ing, this address is a pointer to an address in    Bits 29-27 Op Code
    memory that points to the data location. When
    bit 28 is set, indicating table indirect address-      The following Op Code bits have different
    ing, the value in this field is an offset into a       meanings, depending on whether the
    table pointed to by the DSA. The table entry           SYM53C810A is operating in initiator or tar-
    contains byte count and address information.           get mode. Note: Op Code selections 101-111
                                                           are considered Read/Write instructions, and
                                                           are described in that section.

                                                       Target Mode

                                                       OPC2  OPC1   OPC0  Instruction Defined
                                                       0     0      0     Reselect
                                                       0     0      1     Disconnect
                                                       0     1      0     Wait Select
                                                       0     1      1     Set
                                                       1     0      0     Clear

                                                       Reselect Instruction

                                                       1. The SYM53C810A arbitrates for the SCSI bus
                                                           by asserting the SCSI ID stored in the SCID
                                                           register. If the SYM53C810A loses arbitration,
                                                           then it tries again during the next available
                                                           arbitration cycle without reporting any lost
                                                           arbitration status.

                                                       2. If the SYM53C810A wins arbitration, it
                                                           attempts to reselect the SCSI device whose ID
                                                           is defined in the destination ID field of the
                                                           instruction. Once the SYM53C810A has won
                                                           arbitration, it fetches the next instruction from
                                                           the address pointed to by the DSP register.

6-8                                                                       SYM53C810A Data Manual
3. Therefore, the SCRIPTS can move on to the              Instruction Set of the I/O Processor
     next instructions before the reselection has                                I/O Instructions
     completed. It will continue executing
     SCRIPTS until a SCRIPTS instruction that                                                        6-9
     requires a response from the initiator is
     encountered.

4. If the SYM53C810A is selected or reselected
     before winning arbitration, it fetches the next
     instruction from the address pointed to by the
     32-bit jump address field stored in the DNAD
     register. The SYM53C810A should manually
     be set to initiator mode if it is reselected, or to
     target mode if it is selected.

Disconnect Instruction
The SYM53C810A disconnects from the SCSI
bus by deasserting all SCSI signal outputs.
Wait Select Instruction

1. If the SYM53C810A is selected, it fetches the
     next instruction from the address pointed to by
     the DSP register.

2. If reselected, the SYM53C810A fetches the
     next instruction from the address pointed to by
     the 32-bit jump address field stored in the
     DNAD register. The SYM53C810A should
     manually be set to initiator mode when
     reselected.

3. If the CPU sets the SIGP bit in the ISTAT
     register, the SYM53C810A will abort the Wait
     Select instruction and fetch the next
     instruction from the address pointed to by the
     32-bit jump address field stored in the DNAD
     register.

Set Instruction
When the SACK/ or SATN/ bits are set, the corre-
sponding bits in the SOCL register are set. SACK/
or SATN/ should not be set except for testing pur-
poses.When the target bit is set, the corresponding
bit in the SCNTL0 register is also set. When the
carry bit is set, the corresponding bit in the Arith-
metic Logic Unit (ALU) is set.
Note: none of the signals are set on the SCSI bus

          in target mode.

SYM53C810A Data Manual
Instruction Set of the I/O Processor
I/O Instructions

      DCMD Register                   DBC Register

      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                      RES           RES RES                 RES

                                                                                                                  Set/Clear ATN/

                                                                                                       Set/Clear ACK/

                                                                                           Set/Clear Target Mode

                                                                                         Set/Clear Carry

                                                                Encoded Destination ID 0
                                                            Encoded Destination ID 1
                                                        Encoded Destination ID 2
                                                    Reserved
                                                 Reserved
                                            Reserved
                                         Reserved
                                     Reserved
                                 Select with ATN/
                             Table Indirect Mode
                         Relative Address Mode
                     Op Code bit 0
                 Op Code bit 1
             Op Code bit 2
         1 - Instruction Type - I/O
      0 - Instruction Type - I/O

                                 Second 32-bit word of the I/O instruction

                                                             DSPSRegister
      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                                      32-bit Jump Address
                                      Figure 6-3: I/O Instruction Register

6-10                                                                             SYM53C810A Data Manual
                                                       Instruction Set of the I/O Processor
                                                                              I/O Instructions

Clear Instruction                                          32-bit jump address field stored in the DNAD
When the SACK/ or SATN/ bits are set, the corre-           register. The SYM53C810A should manually
sponding bits are cleared in the SOCL register.            be set to initiator mode if it is reselected, or to
SACK/ or SATN/ should not be set except for test-          target mode if it is selected.
ing purposes. When the target bit is set, the corre-
sponding bit in the SCNTL0 register is cleared.        4. If the Select with SATN/ field is set, the
When the carry bit is set, the corresponding bit in        SATN/ signal is asserted during the selection
the ALU is cleared.                                        phase.
Note: none of the signals are reset on the SCSI
                                                       Wait Disconnect Instruction
         bus in target mode.
                                                       1. The SYM53C810A waits for the target to
Initiator Mode                                             perform a "legal" disconnect from the SCSI
                                                           bus. A "legal" disconnect occurs when SBSY/
OPC2  OPC1  OPC0        Instruction Defined                and SSEL/ are inactive for a minimum of one
0     0     0           Select                             Bus Free delay (400 ns), after the
0     0     1           Wait Disconnect                    SYM53C810A has received a Disconnect
0     1     0           Wait Reselect                      Message or a Command Complete Message.
0     1     1           Set
1     0     0           Clear                          Wait Reselect Instruction

Select Instruction                                     1. If the SYM53C810A is selected before being
                                                           reselected, it fetches the next instruction from
1. The SYM53C810A arbitrates for the SCSI bus              the address pointed to by the 32-bit jump
    by asserting the SCSI ID stored in the SCID            address field stored in the DNAD register. The
    register. If the SYM53C810A loses arbitration,         SYM53C810A should be manually set to
    it tries again during the next available               target mode when selected.
    arbitration cycle without reporting any lost
    arbitration status.                                2. If the SYM53C810A is reselected, it fetches
                                                           the next instruction from the address pointed
2. If the SYM53C810A wins arbitration, it                  to by the DSP register.
    attempts to select the SCSI device whose ID is
    defined in the destination ID field of the         3. If the CPU sets the SIGP bit in the ISTAT
    instruction. Once the SYM53C810A has won               register, the SYM53C810A will abort the Wait
    arbitration, it fetches the next instruction from      Reselect instruction and fetch the next
    the address pointed to by the DSP register.            instruction from the address pointed to by the
    Therefore, the SCRIPTS program can move to             32-bit jump address field stored in the DNAD
    the next instruction before the selection has          register.
    completed. It will continue executing
    SCRIPTS until a SCRIPTS instruction that           Set Instruction
    requires a response from the target is
    encountered.                                       When the SACK/ or SATN/ bits are set, the corre-
                                                       sponding bits in the SOCL register are set. When
3. If the SYM53C810A is selected or reselected         the Target bit is set, the corresponding bit in the
    before winning arbitration, it fetches the next    SCNTL0 register is also set.When the Carry bit is
    instruction from the address pointed to by the     set, the corresponding bit in the ALU is set.

                                                       Clear Instruction

                                                       When the SACK/or SATN/ bits are set, the corre-
                                                       sponding bits are cleared in the SOCL register.
                                                       When the Target bit is set, the corresponding bit in

SYM53C810A Data Manual                                 6-11
Instruction Set of the I/O Processor
I/O Instructions

the SCNTL0 register is cleared. When the Carry        2. An I/O command structure must have all four
bit is set, the corresponding bit in the ALU is           bytes contiguous in system memory, as shown
cleared.                                                  below. The offset/period bits are ordered as in
                                                          the SXFER register. The configuration bits are
Bit 26 Relative Addressing Mode                           ordered as in the SCNTL3 register.

    When this bit is set, the 24-bit signed value in  Config          ID          Offset/         (00)
    the DNAD register is used as a relative dis-
    placement from the current DSP address. This                                  period
    bit should only be used in conjunction with the
    Select, Reselect, Wait Select, and Wait Reselect  This bit should only be used in conjunction
    instructions. The Select and Reselect instruc-    with the Select, Reselect, Wait Select, and Wait
    tions can contain an absolute alternate jump      Reselect instructions. Bits 25 and 26 may be
    address or a relative transfer address.           set individually or in combination:

Bit 25 Table Indirect Mode                            Direct              Bit 25  Bit 26
                                                      Table Indirect      0       0
    When this bit is set, the 24-bit signed value in  Relative            0       1
    the DBC register is added to the value in the     Table Relative      1       0
    DSA register, used as an offset relative to the                       1       1
    value in the Data Structure Base Address
    (DSA) register. The SCNTL3 value, SCSI ID,        Direct
    synchronous offset and synchronous period are     Uses the device ID and physical address in the
    loaded from this address. Prior to the start of   instruction.
    an I/O, the DSA should be loaded with the
    base address of the I/O data structure. The       Command         ID  Not Used Not Used
    address may be any address on a dword bound-
    ary. After a Table Indirect op code is fetched,                   Absolute Alternate Address
    the DSA is added to the 24-bit signed offset
    value from the op code to generate the address    Table Indirect
    of the required data; both positive and negative  Uses the physical jump address, but fetches data
    offsets are allowed. A subsequent fetch from      using the table indirect method.
    that address brings the data values into the
    chip.                                             Command                     Table Offset

    SCRIPTS can directly execute operating sys-                       Absolute Alternate Address
    tem I/O data structures, saving time at the
    beginning of an I/O operation. The I/O data       Relative
    structure can begin on any dword boundary         Uses the device ID in the instruction, but treats
    and may cross system segment boundaries.          the alternate address as a relative jump.
    There are two restrictions on the placement of
    data in system memory:

1. The I/O data structure must lie within the 8
    MB above or below the base address.

                                                      Command         ID  Not Used                Not Used

                                                                      Alternate Jump Offset

6-12                                                                              SYM53C810A Data Manual
                                                                          Instruction Set of the I/O Processor
                                                                                                 I/O Instructions

Table Relative                                         Bit 6  Set/Clear SACK/
Treats the alternate jump address as a relative
jump and fetches the device ID, synchronous off-       Bit 3  Set/Clear SATN/
set, and synchronous period indirectly. Adds the
value in bits 23-0 of the first four bytes of the      These two bits are used in conjunction with a
SCRIPTS instruction to the data structure base         Set or Clear instruction to assert or deassert
address to form the fetch address.                     the corresponding SCSI control signal. Bit 6
                                                       controls the SCSI SACK/ signal; bit 3 controls
                                                       the SCSI SATN/ signal.

Command                   Table Offset                 Setting either of these bits will set or reset the
         Alternate Jump Offset                         corresponding bit in the SOCL register,
                                                       depending on the instruction used. The Set
Bit 24 Select with ATN/                                instruction is used to assert SACK/ and/or
                                                       SATN/ on the SCSI bus.The Clear instruction
This bit specifies whether SATN/ will be               is used to deassert SACK/ and/or SATN/ on
asserted during the selection phase when the           the SCSI bus.
SYM53C810A is executing a Select instruc-
tion. When operating in initiator mode, set this       Since SACK/ and SATN/ are initiator signals,
bit for the Select instruction. If this bit is set on  they will not be asserted on the SCSI bus
any other I/O instruction, an illegal instruction      unless the SYM53C810A is operating as an
interrupt is generated.                                initiator or the SCSI Loopback Enable bit is
                                                       set in the STEST2 register.

Bits 18-16 Encoded SCSI Destination ID                 The Set/Clear SCSI ACK/ATN instruction
                                                       would be used after message phase Block Move
This 3-bit field specifies the destination SCSI        operations to give the initiator the opportunity
ID for an I/O instruction.                             to assert attention before acknowledging the
                                                       last message byte. For example, if the initiator
Bit 10 Set/Clear Carry                                 wishes to reject a message, an Assert SCSI
                                                       ATN instruction would be issued before a
This bit is used in conjunction with a Set or          Clear SCSI ACK instruction.
Clear instruction to set or clear the Carry bit.
Setting this bit with a Set instruction asserts        Bits 2-0 Reserved
the Carry bit in the ALU. Setting this bit with a
Clear instruction deasserts the Carry bit in the
ALU.

Bit 9  Set/Clear Target Mode                           Second Dword

This bit is used in conjunction with a Set or          Bits 31-0 Start Address
Clear instruction to set or clear target mode.
Setting this bit with a Set instruction config-            This 32-bit field contains the memory address
ures the SYM53C810A as a target device (this               to fetch the next instruction if the selection or
sets bit 0 of the SCNTL0 register). Clearing               reselection fails.
this bit with a Clear instruction configures the
SYM53C810A as an initiator device (this                    If relative or table relative addressing is used,
clears bit 0 of the SCNTL0 register).                      this value is a 24-bit signed offset relative to the
                                                           current DSP register value.

SYM53C810A Data Manual                                                         6-13
Instruction Set of the I/O Processor
Read/Write Instructions

Read/Write Instructions                                Second Dword

The Read/Write Instruction type moves the con-         Bits 31-0 Destination Address
tents of one register to another, or performs arith-       This field contains the 32-bit destination
metic operations such as AND, OR, XOR,                     address where the data is to be moved.
Addition, and Shift. Figure 6-4 illustrates the reg-
ister bit values that represent a Read/Write instruc-  Read-Modify-Write
tion.                                                  Cycles

First Dword                                            During these cycles the register is read, the
                                                       selected operation is performed, and the result is
Bits 31-30 Instruction Type - Read/Write               written back to the source register.
    Instruction                                        The Add operation can be used to increment or
    The Read/Write instruction uses operator bits      decrement register values (or memory values if
    26 through 24 in conjunction with the op code      used in conjunction with a Memory-to-Register
    bits to determine which instruction is currently   Move operation) for use as loop counters.
    selected.
                                                       Move to/from
Bits 29-27 Op Code                                     SFBR Cycles
    The combinations of these bits determine if the
    instruction is a Read/Write or an I/O instruc-     All operations are read-modify-writes. However,
    tion. Op codes 000 through 100 are considered      two registers are involved, one of which is always
    I/O instructions. Refer to Table 6-1 for field     the SFBR. The possible functions of this instruc-
    definitions.                                       tion are:

Bits 26-24 Operator                                    s Write one byte (value contained within the
    These bits are used in conjunction with the op         SCRIPTS instruction) into any chip register.
    code bits to determine which instruction is
    currently selected. Refer to Table 6-1 for field   s Move to/from the SFBR from/to any other
    definitions.                                           register.

Bits 22-16 Register Address - A(6-0)                   s Alter the value of a register with AND/OR/
    Register values may be changed from                    ADD/XOR/SHIFT LEFT/SHIFT RIGHT
    SCRIPTS in read-modify-write cycles or move            operators.
    to/from SFBR cycles. A(6-0) select an 8-bit
    source/destination register within the             s After moving values to the SFBR, the compare
    SYM53C810A.                                            and jump, call, or similar instructions may be
                                                           used to check the value.

                                                       s A Move-to-SFBR followed by a Move-from-
                                                           SFBR can be used to perform a register to
                                                           register move.

6-14                                                   SYM53C810A Data Manual
                                                                                              Instruction Set of the I/O Processor
                                                                                                           Read/Write Instructions

                        DCMD Register                                         DBC Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                                                              Immediate Data   Reserved
                                                                                              (must be 0)

                                                                          A0

                                                                      A1

                                                                      A2 Register

                                                                  A3      Address

                                                            A4

                                                        A5

                                                    A6

                                                    0 (Reserved)

                                       Operator 0

                                       Operator 1

                                       Operator 2

                        Op Code bit 0

                        Op Code bit 1

                        Op Code bit 2

                        1 - Instruction Type - R/W

                        0 - Instruction Type - R/W

                                                     DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                        Figure 6-4: Read/Write Register Instruction

SYM53C810A Data Manual                                                                                     6-15
Instruction Set of the I/O Processor
Read/Write Instructions

                                      Table 6-1: Read/Write Instructions

Operator  Op Code 111                    Op Code 110                                     Op Code 101
          Read Modify Write              Move to SFBR                                    Move from SFBR

000       Move data into register.       Move data into SFBR regis-                      Move data into register.
                                                                                         Syntax: "Move data8 to
          Syntax: "Move data8 to         ter. Syntax: "Move data8 to                     RegA"

          RegA"                          SFBR"                                           Shift the SFBR register one
                                                                                         bit to the left and place the
001*      Shift register one bit to the  Shift register one bit to the                   result in the register. Syntax:
          left and place the result in   left and place the result in                    "Move SFBR SHL RegA"
          the same register. Syntax:     the SFBR register. Syntax:
          "Move RegA SHL RegA"           "Move RegA SHL SFBR"                            OR data with SFBR and
                                                                                         place the result in the regis-
010       OR data with register and      OR data with register and                       ter. Syntax: "Move SFBR |
                                                                                         data8 to RegA"
          place the result in the same place the result in the SFBR
                                                                                         XOR data with SFBR and
          register. Syntax: "Move        register. Syntax: "Move                         place the result in the regis-
                                                                                         ter. Syntax: "Move SFBR
          RegA | data8 to RegA"          RegA | data8 to SFBR"                           XOR data8 to RegA"

011       XOR data with register and XOR data with register and                          AND data with SFBR and
                                                                                         place the result in the regis-
          place the result in the same place the result in the SFBR                      ter. Syntax: "Move SFBR &
                                                                                         data8 to RegA"
          register. Syntax: "Move        register. Syntax: "Move
                                                                                         Shift the SFBR register one
          RegA XOR data8 to RegA" RegA XOR data8 to SFBR"                                bit to the right and place the
                                                                                         result in the register. Syntax:
100       AND data with register and AND data with register and                          "Move SFBR SHR RegA"

          place the result in the same place the result in the SFBR                      Add data to SFBR without
                                                                                         carry and place the result in
          register. Syntax: "Move        register. Syntax: "Move                         the register. Syntax: "Move
                                                                                         SFBR + data8 to RegA"
          RegA & data8 to RegA"          RegA & data8 to SFBR"
                                                                                         Add data to SFBR with
101*      Shift register one bit to the  Shift register one bit to the                   carry and place the result in
          right and place the result in  right and place the result in                   the register. Syntax: "Move
          the same register. Syntax:     the SFBR register. Syntax:                      SFBR + data8 to RegA with
          "Move RegA SHR RegA"           "Move RegA SHR SFBR"                            carry"

110       Add data to register without Add data to register without

          carry and place the result in carry and place the result in

          the same register. Syntax:     the SFBR register. Syntax:

          "Move RegA + data8 to          "Move RegA + data8 to

          RegA"                          SFBR"

111       Add data to register with      Add data to register with

          carry and place the result in carry and place the result in

          the same register. Syntax:     the SFBR register. Syntax:

          "Move RegA + data8 to          "Move RegA + data8 to

          RegA with carry"               SFBR with carry"

Notes:
1. Substitute the desired register name or address for "RegA" in the syntax examples
2. data8 indicates eight bits of data
* Data is shifted through the Carry bit and the Carry bit is shifted into the data byte

6-16                                                                                     SYM53C810A Data Manual
                                                        Instruction Set of the I/O Processor
                                                               Transfer Control Instructions

Transfer Control                                            instruction.
Instructions
                                                        2. If the comparisons are false, the
The Transfer Control, or Conditional Jump,                  SYM53C810A fetches the next instruction
instruction allows you to write SCRIPTS that                from the address pointed to by the DSP
make decisions based on real time conditions on             register, leaving the instruction pointer
the SCSI bus, such as phase or data. This instruc-          unchanged.
tion type includes Jump, Call, Return, and Inter-
rupt instructions. Figure 6-5 illustrates the register  Call Instruction
bit values that represent a Transfer Control
instruction.                                            1. The SYM53C810A can do a true/false
                                                            comparison of the ALU carry bit, or compare
First Dword                                                 the phase and/or data as defined by the Phase
                                                            Compare, Data Compare, and True/False bit
Bits 31-30 Instruction Type - Transfer Control              fields. If the comparisons are true, the
    Instruction                                             SYM53C810A loads the DSP register with the
                                                            contents of the DSPS register and that address
Bits 29-27 Op Code                                          value becomes the address of the next
    This 3-bit field specifies the type of transfer         instruction.
    control instruction to be executed. All transfer
    control instructions can be conditional. They           When the SYM53C810A executes a Call
    can be dependent on a true/false comparison             instruction, the instruction pointer contained
    of the ALU Carry bit or a comparison of the             in the DSP register is stored in the TEMP reg-
    SCSI information transfer phase with the                ister. Since the TEMP register is not a stack
    Phase field, and/or a comparison of the First           and can only hold one dword, nested call
    Byte Received with the Data Compare field.              instructions are not allowed.
    Each instruction can operate in initiator or tar-
    get mode.                                           2. If the comparisons are false, the
                                                            SYM53C810A fetches the next instruction
                                                            from the address pointed to by the DSP
                                                            register and the instruction pointer is not
                                                            modified.

OPC2  OPC1  OPC0  Instruction Defined                   Return Instruction
0     0     0     Jump
0     0     1     Call                                  1. The SYM53C810A can do a true/false
0     1     0     Return                                    comparison of the ALU carry bit, or compare
0     1     1     Interrupt                                 the phase and/or data as defined by the Phase
1     X     X     Reserved                                  Compare, Data Compare, and True/False bit
                                                            fields. If the comparisons are true, then the
Jump Instruction                                            SYM53C810A loads the DSP register with the
                                                            contents of the DSPS register. That address
1. The SYM53C810Acan do a true/false                        value becomes the address of the next
     comparison of the ALU carry bit, or compare            instruction.
     the phase and/or data as defined by the Phase
     Compare, Data Compare and True/False bit               When a Return instruction is executed, the
     fields. If the comparisons are true, the               value stored in the TEMP register is returned
     SYM53C810A loads the DSP register with the             to the DSP register. The SYM53C810A does
     contents of the DSPS register. The DSP                 not check to see whether the Call instruction
     register now contains the address of the next          has already been executed. It will not generate
                                                            an interrupt if a Return instruction is executed
SYM53C810A Data Manual                                      without previously executing a Call instruc-
                                                            tion.

                                                                                                                                   6-17
Instruction Set of the I/O Processor
Transfer Control Instructions

      DCMD Register                   DBC Register

      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                                                  Mask for compare    Data to be compared
                                                                                       with the SCSI First
                                                                Wait for Valid Phase
                                                            Compare Phase                Byte Received
                                                        Compare Data
                                                    Jump if: True=1, False=0
                                                 Interrupt on the Fly
                                             Carry Test
                                         0 (Reserved)
                                     Relative addressing mode
                                 I/O
                             C/D
                         MSG
                     Op Code bit 0
                 Op Code bit 1
             Op Code bit 2
          0 - Instruction Type - Transfer Control
      1- Instruction Type - Transfer Control

                                                           DSPS Register
      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                      Figure 6-5: Transfer Control Instruction

6-18                                                                                                        SYM53C810A Data Manual
                                                                       Instruction Set of the I/O Processor
                                                                              Transfer Control Instructions

2. If the comparisons are false, then the                  ing SCSI phase. These bits are only valid when
    SYM53C810A fetches the next instruction                the SYM53C810A is operating in initiator
    from the address pointed to by the DSP                 mode; when the SYM53C810A is operating in
    register and the instruction pointer will not be       the target mode, these bits should be cleared.
    modified.

Interrupt Instructions                                  MSG C/D I/O    SCSI Phase
Interrupt                                                              Data out
                                                        0  0        0  Data in
    a) The SYM53C810A can do a true/false                              Command
         comparison of the ALU carry bit, or            0  0        1  Status
         compare the phase and/or data as defined                      Reserved out
         by the Phase Compare, Data Compare,            0  1        0  Reserved in
         and True/False bit fields. If the                             Message out
         comparisons are true, then the                 0  1        1  Message in
         SYM53C810A generates an interrupt by
         asserting the IRQ/ signal.                     1  0        0

    b) The 32-bit address field stored in the           1  0        1
         DSPS register (not DNAD as in 53C700)
         can contain a unique interrupt service         1  1        0
         vector. When servicing the interrupt, this
         unique status code allows the ISR to           1  1        1
         quickly identify the point at which the
         interrupt occurred.                            Bit 23 Relative Addressing Mode

    c) The SYM53C810A halts and the DSP                     When this bit is set, the 24-bit signed value in
         register must be written to start any further      the DSPS register is used as a relative offset
         operation.                                         from the current DSP address (which is point-
                                                            ing to the next instruction, not the one cur-
Interrupt on-the-Fly                                        rently executing). Relative mode does not
                                                            apply to Return and Interrupt SCRIPTS.
    a) The SYM53C810A can do a true/false
         comparison of the ALU carry bit or                Jump/Call an Absolute Address
         compare the phase and/or data as defined          Start execution at the new absolute address.
         by the Phase Compare, Data Compare,
         and True/False bit fields. If the                 Command     Condition Codes
         comparisons are true, and the Interrupt on
         the Fly bit is set (bit 20), the                           Absolute Alternate Address
         SYM53C810A will assert the Interrupt on
         the Fly bit (ISTAT bit 2).                        Jump/Call a Relative Address
                                                           Start execution at the current address plus (or
Bits 26-24 SCSI Phase                                      minus) the relative offset.

    This 3-bit field corresponds to the three SCSI      Command        Condition Codes
    bus phase signals which are compared with the       Don't Care     Alternate Jump Offset
    phase lines latched when SREQ/ is asserted.
    Comparisons can be performed to determine              The SCRIPTS program counter is a 32-bit
    the SCSI phase actually being driven on the            value pointing to the SCRIPTS instruction
    SCSI bus. The following table describes the            currently being executed by the
    possible combinations and their correspond-            SYM53C810A. The next address is formed by
                                                           adding the 32-bit program counter to the 24-
                                                           bit signed value of the last 24 bits of the Jump

SYM53C810A Data Manual                                                                          6-19
Instruction Set of the I/O Processor
Transfer Control Instructions

    or Call instruction. Because it is signed (twos    must be true to branch on a true condition.
    compliment), the jump can be forward or            Both compares must be false to branch on a
    backward.                                          false condition.

     A relative transfer can be to any address within  Bit 19  Result of  Action
    a 16-MB segment. The program counter is                    Compare
    combined with the 24-bit signed offset (using        0                Jump Taken
    addition or subtraction) to form the new exe-        0       False    No Jump
    cution address.                                      1       True     No Jump
                                                         1       False    Jump Taken
    SCRIPTS programs may contain a mixture of                    True
    direct jumps and relative jumps to provide
    maximum versatility when writing SCRIPTS.          Bit 18 Compare Data
    For example, major sections of code can be
    accessed with far calls using the 32-bit physical      When this bit is set, the first byte received from
    address, then local labels can be called using         the SCSI data bus (contained in SFBR regis-
    relative transfers. If a SCRIPTS instruction           ter) is compared with the Data to be Com-
    uses only relative transfers it would not require      pared Field in the Transfer Control instruction.
    any run time alteration of physical addresses,         The Wait for Valid Phase bit controls when this
    and could be stored in and executed from a             compare will occur. The Jump if True/False bit
    PROM.                                                  determines the condition (true or false) to
                                                           branch on.
Bit 21 Carry Test
                                                       Bit 17 Compare Phase
    When this bit is set, decisions based on the
    ALU carry bit can be made. True/False com-             When the SYM53C810A is in initiator mode,
    parisons are legal, but Data Compare and               this bit controls phase compare operations.
    Phase Compare are illegal.                             When this bit is set, the SCSI phase signals
                                                           (latched by SREQ/) are compared to the Phase
Bit 20 Interrupt on the Fly                                Field in the Transfer Control instruction; if
                                                           they match, the comparison is true. The Wait
    When this bit is set, the Interrupt instruction        for Valid Phase bit controls when the compare
    will not halt the SCRIPTS processor. Once the          will occur. When the SYM53C810A is operat-
    interrupt occurs, the Interrupt on the Fly bit         ing in target mode this bit, when set, tests for
    (ISTAT bit 2) will be asserted.                        an active SCSI SATN/ signal.

Bit 19 Jump If True/False                              Bit 16 Wait For Valid Phase

    This bit determines whether the                        If the Wait for Valid Phase bit is set, the
    SYM53C810A should branch when a compar-                SYM53C810A waits for a previously unser-
    ison is true or when a comparison is false. This       viced phase before comparing the SCSI phase
    bit applies to phase compares, data compares,          and data. If the Wait for Valid Phase bit is clear,
    and carry tests. If both the Phase Compare and         the SYM53C810A compares the SCSI phase
    Data Compare bits are set, then both compares          and data immediately.

6-20                                                                      SYM53C810A Data Manual
                                                      Instruction Set of the I/O Processor
                                                               Memory Move Instructions

Bits 15-8 Data Compare Mask                           Memory Move Instructions

    The Data Compare Mask allows a SCRIPTS            This SCRIPTS Instruction allows the
    instruction to test certain bits within a data    SYM53C810A to execute high performance block
    byte. During the data compare, any mask bits      moves of 32-bit data from one part of main mem-
    that are set cause the corresponding bit in the   ory to another. In this mode, the SYM53C810A is
    SFBR data byte to be ignored. For instance, a     an independent, high performance DMA control-
    mask of 01111111b and data compare value of       ler irrespective of SCSI operations. Since the regis-
    1XXXXXXXb allows the SCRIPTS proces-              ters of the SYM53C810A can be mapped into
    sor to determine whether or not the high order    system memory, this SCRIPTS instruction also
    bit is set while ignoring the remaining bits.     moves an SYM53C810A register to or from mem-
                                                      ory or another SYM53C810A register. Figure 6-6
Bits 7-0 Data Compare Value                           illustrates the register bit values that represent a
                                                      Memory Move instruction.
    This 8-bit field is the data to be compared
    against the SCSI First Byte Received (SFBR)       For Memory Move instructions, bits 5 and 4
    register. These bits are used in conjunction      (SIOM and DIOM) in the DMODE register
    with the Data Compare Mask Field to test for      determine whether the source or destination
    a particular data value.                          addresses reside in memory or I/O space. By set-
                                                      ting these bits appropriately, data may be moved
Second Dword                                          within memory space, within I/O space, or
                                                      between the two address spaces.
Bits 31-0 Jump Address
                                                      The Memory Move instruction is used to copy the
    This 32-bit field contains the address of the     specified number of bytes from the source address
    next instruction to fetch when a jump is taken.   to the destination address.
    Once the SYM53C810A has fetched the
    instruction from the address pointed to by        Allowing the SYM53C810A to perform memory
    these 32 bits, this address is incremented by 4,  moves frees the system processor for other tasks
    loaded into the DSP register and becomes the      and moves data at higher speeds than available
    current instruction pointer.                      from current DMA controllers. Up to 16 MB may
                                                      be transferred with one instruction. There are two
                                                      restrictions:

                                                      1. Both the source and destination addresses
                                                          must start with the same address alignment
                                                          (A(1-0) must be the same). If source and
                                                          destination are not aligned, then an illegal
                                                          instruction interrupt will occur.

                                                      2. Indirect addresses are not allowed. A burst of
                                                          data is fetched from the source address, put
                                                          into the DMA FIFO and then written out to
                                                          the destination address. The move continues
                                                          until the byte count decrements to zero, then
                                                          another SCRIPTS instruction is fetched from
                                                          system memory.

SYM53C810A Data Manual                                6-21
Instruction Set of the I/O Processor
Memory Move Instructions

      DCMD Register                            DBC Register

      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                 1 - No Flush  24-bit Memory Move byte counter
                             0 (Reserved)
                         0 (Reserved)
                     0 (Reserved)
                 0 (Reserved)
             0 (Reserved)
         1 - Instruction Type - Memory Move
      1 - Instruction Type - Memory Move

                                                           DSPS Register
      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                                           TEMP Register
      31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                    Figure 6-6: Memory to Memory Move Instruction

6-22                                                                                         SYM53C810A Data Manual
                                                      Instruction Set of the I/O Processor
                                                               Memory Move Instructions

The DSPS and DSA registers are additional hold-       Read/Write System
ing registers used during the Memory Move; how-       Memory from a SCRIPTS Instruction
ever, the contents of the DSA register are
preserved.                                            By using the Memory Move instruction, single or
                                                      multiple register values may be transferred to or
First Dword                                           from system memory.

Bits 31-30 Instruction Type - Memory Move             Because the SYM53C810A will respond to
    Instruction                                       addresses as defined in the Base I/O or Base Mem-
                                                      ory registers, it could be accessed during a Mem-
Bits 29-25 Reserved                                   ory Move operation if the source or destination
    These bits are reserved and must be zero. If      address decodes to within the chip's register space.
    any of these bits is set, an illegal instruction  If this occurs, the register indicated by the lower
    interrupt will occur.                             seven bits of the address is taken to be the data
                                                      source or destination. In this way, register values
Bit 24 No Flush                                       can be saved to system memory and later restored,
Note: this bit has no effect unless the Pre-fetch     and SCRIPTS can make decisions based on data
                                                      values in system memory.
         Enable bit in the DCNTL register is set.
         For information on SCRIPTS instruction       The SFBR is not writable via the CPU, and there-
         prefetching, see Chapter 2.                  fore not by a Memory Move. However, it can be
    When this bit is set, the SYM53C810A per-         loaded via SCRIPTS Read/Write operations. To
    forms a Memory Move (MMOV) without                load the SFBR with a byte stored in system mem-
    flushing the prefetch unit (NFMMOV). When         ory, the byte must first be moved to an intermedi-
    this bit is clear, the Memory Move instruction    ate SYM53C810A register (for example, a
    automatically flushes the prefetch unit. NFM-     SCRATCH register), and then to the SFBR.
    MOV should be used if the source and destina-
    tion are not within four instructions of the      The same address alignment restrictions apply to
    current MMOV instruction.                             register access operations as to normal mem-
Bits 23-0 Transfer Count                                  ory-to-memory transfers.
    The number of bytes to be transferred is stored
    in the lower 24 bits of the first instruction
    word.

Second Dword

Bits 31-0, DSPS Register
    These bits contain the source address of the
    Memory Move.

Third Dword

Bits 31-0, TEMP Register
    These bits contain the destination address for
    the Memory Move.

SYM53C810A Data Manual                                6-23
Instruction Set of the I/O Processor
Load and Store Instructions

Load and Store                                           Bit 28, DSA Relative
Instructions                                                 When this bit is clear, the value in the DSPS is
                                                             the actual 32-bit memory address to perform
The Load and Store instruction provides a more               the load/store to/from. When this bit is set, the
efficient way to move data from/to memory to/from            chip determines the memory address to per-
an internal register in the chip without using the           form the load/store to/from by adding the 24-
normal memory move instruction.                              bit signed offset value in the DSPS to the DSA.

The load and store instructions are represented by       Bits 27-26, Reserved
two-dword op codes. The first dword contains the         Bit 25, No Flush (Store instruction only)
DCMD and DBC register values. The second                 Note: this bit has no effect unless the Pre-fetch
dword contains the DSPS value. This is either the
actual memory location of where to load or store,                 Enable bit in the DCNTL register is set.
or the offset from the DSA, depending on the                      For information on SCRIPTS instruction
value of Bit 28 (DSA Relative).                                   prefetching, see Chapter 2.
                                                             When this bit is set, the SYM53C810A per-
A maximum of 4 bytes may be moved with these                 forms a Store without flushing the prefetch
instructions. The register address and memory                unit. When this bit is clear, the Store instruc-
address must have the same byte alignment, and               tion automatically flushes the prefetch unit. No
the count set such that it does not cross dword              Flush should be used if the source and destina-
boundaries. The destination memory address in                tion are not within four instructions of the cur-
the Store instruction and the source address in the          rent Store instruction.
Load instruction may not map back to the operat-         Bit 24, Load/Store
ing register set of the chip. If it does, a PCI illegal      When this bit is set, the instruction is a Load.
read/write cycle will occur, and the chip will issue         When cleared, it is a Store.
an interrupt (Illegal Instruction Detected) imme-        Bit 23, Reserved
diately following.                                       Bits 22-16, Register Address
                                                             A6-A0 select the register to load/store to/from
Bits A1, A0  Number of bytes allowed to load/                within the SYM053C810A.
             store                                       Note: It is not possible to load the SFBR register,
                                                                  although the SFBR contents may be stored
00           One, two, three or four                              in another location.
                                                         Bits 15-3, Reserved
01           One, two, or three.                         Bits 2-0, Byte Count
                                                             This value is the number of bytes to load/store.
10           One or two
                                                         Second Dword
11           One
                                                         Bits 31-0, Memory/IO Address / DSA Offset
The SIOM and DIOM bits in the DMODE regis-               This is the actual memory location of where to
ter determine whether the destination or source          load or store, or the offset from the DSA register
address of the instruction is in Memory space or I/      value.
O space. The Load/Store utilizes the PCI com-
mands for I/O READ and I/O WRITE to access                                                               SYM53C810A Data Manual
the I/O space.

First Dword

Bit 31-29, Instruction Type
These bits should be 111, indicating the Load and
Store instruction.

6-24
                                                                                               Instruction Set of the I/O Processor
                                                                                                       Load and Store Instructions

                        DCMD Register                                        DBC Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                                                                                   Reserved        Byte Count
                                                                                  (must be 0)  (Number of bytes

                                                                         A0                      to load/store)

                                                                     A1

                                                                     A2 Register

                                                                 A3      Address

                                                             A4

                                                         A5

                                                     A6

                                                0 (Reserved)

                                       Load/Store

                                       1 - No Flush

                                       0 - Reserved

                              0 - Reserved

                              X - DSA Relative

                           1

                           1 Instruction Type - Load and Store

                        1

                                  DSPS Register - Memory/ I/O Address/DSA Offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

                              Figure 6-7: Load and Store Instruction Format

SYM53C810A Data Manual                                                                                           6-25
Instruction Set of the I/O Processor
Load and Store Instructions

6-26                                  SYM53C810A Data Manual
                                                                    Electrical Characteristics
                                                                          DC Characteristics

Chapter 7

Electrical Characteristics

This chapter presents electrical and timing information for the SYM53C810A, using tables and timing
diagrams. Table 7-1 through Table 7-11 list the stress ratings, operating conditions, and DC characteris-
tics of the SYM53C810A. Table 7-12 and Figure 7-1 through Figure 7-5 show the effect of TolerANT
technology on the DC characteristics of the chip.The following section of this chapter presents the AC
characteristics of the SYM53C810A . The chip timings are presented in two sections. The first is the PCI
and external memory interface, followed by the SCSI interface timings.

DC Characteristics

                        Table 7-1: Absolute Maximum Stress Ratings

Symbol Parameter                Min        Max        Unit          Test Conditions

TSTG   Storage temperature      -55        150        °C            -
VDD    Supply voltage           -0.5       7.0
VIN    Input Voltage            VSS - 0.5  VDD + 0.5  V             -
ILP*   Latch-up current         ± 150      -
ESD**  Electrostatic discharge  -          2K         V             -

                                                      mA            -

                                                      V             MIL-STD 883C,

                                                                    Method 3015.7

Stresses beyond those listed above may cause permanent damage to the device.These are stress ratings only; functional operation of
the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
* -2V < VPIN < 8V

** SCSI pins only

SYM53C810A Data Manual                                                                                                                7-1
                                                                                                Electrical Characteristics
                                                                                                      DC Characteristics

                                             Table 7-2: Operating Conditions

Symbol Parameter                             Min        Max                               Unit  Test Conditions
                                                                                                -
VDD   Supply voltage                         4.75       5.25                              V     -
                                                                                          mA    -
IDD*  Supply current (dynamic) -                        130                               mA    -
                                                                                          °C    -
      Supply current (static)                -          1                                 °C/W

TA    Operating free air                     0          70

JA    Thermal resistance                     -          67

      (junction to ambient air)

Conditions that exceed the operating limits may cause the device to function incorrectly

*Average operating supply current is 50 mA.

                  Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/

Symbol Parameter                             Min        Max                               Unit  Test Conditions
                                                                                                -
VIH   Input high voltage                     2.0        VDD + 0.5                         V     -
                                             VSS - 0.5                                          2.5 mA
VIL   Input low voltage                      2.5        0.8                               V     48 mA
                                             VSS                                                -
VOH*  Output high voltage                    -10        3.5                               V     -
                                             -10
VOL   Output low voltage                                0.5                               V

IIN   Input leakage                                     10                                µA

IOZ   Tristate leakage                                  10                                µA

*TolerANT active negation enabled

7-2                                                                                             SYM53C810A Data Manual
                                                                  Electrical Characteristics
                                                                        DC Characteristics

        Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/

Symbol  Parameter             Min        Max                Unit  Test Conditions

VIH     Input high voltage    2.0        VDD + 0.5          V     -

VIL     Input low voltage     VSS - 0.5  0.8                V     -
                              VSS
VOL     Output low voltage    -10        0.5                V     48 mA
                              -500
IIN     Input leakage                    +10                µA    -
                              -10
        (SRST/ only)                     -50                µA

IOZ     Tristate leakage                 10                 µA    -

              Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN

Symbol  Parameter             Min        Max                Unit  Test Conditions

VIH     Input high voltage    2.0        VDD + 0.5          V     -

VIL     Input low voltage     VSS - 0.5  0.8                V     -

IIN     Input leakage         -1.0       1.0                µA    -

Note: CLK, SCLK, GNT/, and IDSEL have 100 µA pull-ups that are enabled when TESTIN is low.TESTIN has a 100 µA
pull-up that is always enabled.

                                    Table 7-6: Capacitance

Symbol  Parameter             Min        Max                Unit  Test Conditions
CI
CIO     Input capacitance of  -          7                  pF    -

        input pads

        Input capacitance of I/O -       10                 pF    -

        pads

SYM53C810A Data Manual                                                                                         7-3
                                                                               Electrical Characteristics
                                                                                     DC Characteristics

                          Table 7-7: Output Signal - MAC/_TESTOUT, REQ/

Symbol Parameter             Min                                    Max  Unit  Test Conditions
                                                                               -16 mA
VOH     Output high voltage  2.4                                    VDD  V     16 mA
                                                                               VDD - 0.5 V
VOL     Output low voltage   VSS                                    0.4  V     0.4 V
                                                                               -
IOH     Output high current  -8                                     -    mA

IOL     Output low current   16                                     -    mA

IOZ     Tristate leakage     -10                                    10   µA

Note: REQ/ has a 100 µA pull-up that is enabled when TESTIN is low

                             Table 7-8: Output Signal - IRQ/

Symbol Parameter             Min                                    Max  Unit  Test Conditions

VOH     Output high voltage  2.4                                    VDD  V     -8 mA

VOL     Output low voltage   VSS                                    0.4  V     8 mA

IOH     Output high current  -4                                     -    mA    VDD - 0.5 V

IOL     Output low current   8                                      -    mA    0.4 V

IOZ     Tristate leakage     -10                                    10   µA    -

Note: IRQ/ has a 100 µA pull-up that is enabled when TESTIN is low. IRQ/ can be enabled with a register bit as an open drain out-
put with an internal 100 µA pull-up.

                             Table 7-9: Output Signal - SERR/

Symbol  Parameter            Min                                    Max  Unit  Test Conditions
VOL     Output low voltage                                                     16 mA
IOL     Output low current   VSS                                    0.4  V     0.4 V
IOZ     Tristate leakage                                                       -
                             16                                     -    mA

                             -10                                    10   µA

7-4                                                                            SYM53C810A Data Manual
                                                                                                    Electrical Characteristics
                                                                                                          DC Characteristics

Table 7-10: Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/, DEVSEL/, STOP/,
                                                                 PERR/, PAR

Symbol Parameter          Min        Max                                                      Unit  Test Conditions

VIH  Input high voltage   2.0        VDD + 0.5                                                V     -
                                                                                                    -
VIL  Input low voltage    VSS - 0.5  0.8                                                      V     16 mA
                                                                                                    16 mA
VOH  Output high voltage  2.4        VDD                                                      V     VDD - 0.5
                                                                                                    0.4 V
VOL  Output low voltage   VSS        0.4                                                      V     VSS < VIN < VDD
                                                                                                    -
IOH  Output high current  -8         -                                                        mA

IOL  Output low current   16         -                                                        mA

IIN  Input leakage        -10        10                                                       µA

IOZ  Tristate leakage     -10        10                                                       µA

Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low

     Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/

Symbol Parameter          Min        Max                                                      Unit  Test Conditions

VIH  Input high voltage   2.0        VDD + 0.5                                                V     -
                                                                                                    -
VIL  Input low voltage    VSS - 0.5  0.8                                                      V     -16 mA
                                                                                                    16 mA
VOH  Output high voltage  2.4        VDD                                                      V     2.4V
                                                                                                    0.4 V
VOL  Output low voltage   VSS        0.4                                                      V     -
                                                                                                    -
IOH  Output high current  -8         -                                                        mA

IOL  Output low current   16         -                                                        mA

IIN  Input leakage        -10        10                                                       µA

IOZ  Tristate leakage     -10        10                                                       µA

Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low

SYM53C810A Data Manual                                                                                               7-5
                                                                                                          Electrical Characteristics
                                                                                                             TolerANT Technology

TolerANT Technology

       Table 7-12: TolerANT Active Negation Technology Electrical Characteristics

Symbol Parameter             Min    Max    Units                                                          Test Conditions

VOH1   Output high voltage   2.5    3.5    V                                                              IOH = 2.5 mA
VOL    Output low voltage    0.1    0.5
VIH    Input high voltage    2.0    7.0    V                                                              IOL = 48 mA
VIL    Input low voltage     -0.5   0.8
VIK    Input clamp voltage   -0.66  -0.77  V                                                              -

VTH                                 1.3    V                                                              Referenced to VSS
VTL                                 1.7
VTH-                                400    V                                                              VDD = 4.75;
VTL
IOH1                                24                                                                    II = -20 mA
IOL                                 200
IOSH1  Threshold, high to low 1.1   625    V                                                              -

       Threshold, low to high 1.5          V                                                              -

       Hysteresis            200           mV                                                             -

       Output high current   2.5           mA                                                             VOH = 2.5 V

       Output low current    100           mA                                                             VOL = 0.5 V

       Short-circuit output  -             mA                                                             Output driving low,

       high current                                                                                       pin shorted to VDD
                                                                                                          supply2

IOSL   Short-circuit output low -   95     mA                                                             Output driving
       current                                                                                            high, pin shorted to
                                                                                                          VSS supply
ILH    Input high leakage    -      10     µA
                                                                                                          -0.5 < VDD < 5.25
ILL    Input low leakage     -      -10    µA                                                             VPIN = 2.7 V

RI     Input resistance      20     -      M                                                              -0.5 < VDD < 5.25
                                                                                                          VPIN = 0.5 V
CP     Capacitance per pin   -      10     pF                                                             SCSI pins3

tR1    Rise time, 10% to 90% 9.7    18.5   ns                                                             PQFP

                                                                                                          Figure 7-1

Note:These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 k pull-up resistor

7-6                                                                                                       SYM53C810A Data Manual
                                                                                                          Electrical Characteristics
                                                                                                             TolerANT Technology

     Table 7-12: TolerANT Active Negation Technology Electrical Characteristics (Continued)

Symbol Parameter               Min         Max                      Units                                 Test Conditions

tF   Fall time, 90% to 10% 5.2             14.7                     ns                                    Figure 7-1
                                                                                                          Figure 7-1
dVH/dt Slew rate, low to high  0.15        0.49                     V/ns                                  Figure 7-1
                                                                                                          MIL-STD-883C;
dVL/dt Slew rate, high to low  0.19        0.52                     V/ns                                  3015-7
                                                                                                          -
ESD  Electrostatic discharge 2             -                        KV                                    Figure 7-2
                                                                                                          Figure 7-2
     Latch-up                  100         -                        mA

     Filter delay              20          30                       ns

     Extended filter delay     40          60                       ns

Note:These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 k pull-up resistor

                                    20 pF  47 

                                                     +

                                                                  2.5 V

                                                     -

                         Figure 7-1: Rise and Fall Time Test Conditions

     REQ/ or ACK/ Input                                              t1
                                                 VTH

     *t1 is the input filtering period

                                  Figure 7-2: SCSI Input Filtering

SYM53C810A Data Manual                                                                                                     7-7
                                                                                                                                                         Electrical Characteristics
                                                                                                                                                            TolerANT Technology

                                                                                        1.1  1.3

                                                    Received Logic Level  1

                                                                          0

                                                                                                  1.5                             1.7

                                                                                        Input Voltage (Volts)

                                               Figure 7-3: Hysteresis of SCSI Receiver

                                            +40

              INPUT CURRENT (milliAmperes)  +20

                                                 0                        -0.7 V                     8.2 V                                14.4 V
                                               -20                                                                                        HI-Z
                                                                                             OUTPUT
                                                                                             ACTIVE

                                            -40

                                                    -4                            0          4                                 8          12      16

                                                                                     INPUT VOLTAGE (Volts)

                 Figure 7-4: Input Current as a Function of Input Voltage

     0OUTPUT SINK CURRENT (milliAmperes)                                                                                       100
                                                                                         OUTPUT SOURCE CURRENT (milliAmperes)
     -200                                                                                                                         80

                                                                                                      60
     -400

                                                                                                      40

     -600
                                                                                                      20

     -800                                                                                                                         0

           0  1                             2       3                        4       5                                                 0      1   2   3  4        5

              OUTPUT VOLTAGE (Volts)                                                                                                      OUTPUT VOLTAGE (Volts)

              Figure 7-5: Output Current as a Function of Output Voltage

7-8                                                                                                                                                      SYM53C810A Data Manual
                                                                                                                          Electrical Characteristics
                                                                                                                                 AC Characteristics

AC Characteristics

The AC characteristics described in this section apply over the entire range of operating conditions (refer
to the DC Characteristics section), Chip timings are based on simulation at worst case voltage, tempera-
ture, and processing. Timings were developed with a load capacitance of 50 pF.

                                                   t1
                                            t3

                                  CLK/SCLK

                                               t4      t2

                                  Figure 7-6: Clock Timing Waveform

                                            Table 7-13: Clock Timing

Symbol  Parameter                           Min                               Max  Units
                                                                                   ns
t1      Bus clock cycle time                30                                DC   ns
                                                                                   ns
        SCSI clock cycle time (SCLK)* 25                                      60   ns
                                                                                   ns
t2      CLK low time**                      12                                -    ns
                                                                                   V/ns
        SCLK low time**                     10                                33   V/ns

t3      CLK high time**                     12                                -

        SCLK high time**                    10                                33

t4      CLK slew rate                       1                                 -

        SCLK slew rate                      1                                 -

* This parameter must be met to insure SCSI timings are within specification

**Duty cycle not to exceed 60/40

SYM53C810A Data Manual                                                                    7-9
                                                                                       Electrical Characteristics
                                                                                             AC Characteristics

         CLK

                                                         t2

    RST/                                         t1

                                     Figure 7-7: Reset Input Waveforms

                                                 Table 7-14: Reset Input Timings

Symbol Parameter                                                                  Min  Max  Units

t1            Reset pulse width                                                   10   -    tCLK

t2            Reset deasserted setup to CLK high                                  0    -    ns

                                             t2      t3      t1
                         IRQ/
                         CLK

                                     Figure 7-8: Interrupt Output Waveforms

                                     Table 7-15: Interrupt Output Timings

 Symbol       Parameter                                                           Min  Max  Units

 t1           CLK high to IRQ/ low                                                -    20   ns
 t2
 t3           CLK high to IRQ/ high                                               -    40   ns
7-10
              IRQ/ deassertion time                                               3    -    CLKs

                                                                                       SYM53C810A Data Manual
                                                                                                                          Electrical Characteristics
                                                                                                                  PCI Interface Timing Diagrams

PCI Interface Timing Diagrams

Figure 7-9 through Figure 7-18 represent signal activity when the SYM53C810A accesses the PCI bus.
The timings for the PCI bus interface are listed on page 7-22. The following timing diagrams are included
in this section:

Target Cycles
s PCI configuration register read
s PCI configuration register write
s Target read
s Target write

s

Initiator Cycles
s Op code fetch, non-burst
s Burst op code fetch
s Back-to-back read
s Back-to-back write
s Burst read
s Burst write

SYM53C810A Data Manual  7-11
                                                                                                   Electrical Characteristics
                                                                                           PCI Interface Timing Diagrams

                                         1                  2            3              4                5

                        CLK
      (Driven by System)

                        FRAME/   t1         t2
           (Driven by System)                       t3
                                   t1
                            AD/             t2                           Data Out
      (Driven by Master-Addr;      Addr                                             t
                                     In                     Byte Enable              2
                53C810A-Data)
                                   t1                                               t
                          C_BE/                                                      2
            (Driven by Master)     CMD

                           PAR              t2  t1                                         t3
      (Driven by Master-Addr;                                                                       Out
                                                In
                53C810A-Data)                              t2

                          IRDY/                         t1
            (Driven by Master)
                                                                            t
                         TRDY/                                               3
         (Driven by 53C810A)
                                                                            t3
                          STOP/
         (Driven by 53C810A)     t1                            t3

                        DEVSEL/             t2
        (Driven by 53C810A)

                          IDSEL
            (Driven by Master)

                                 Figure 7-9: PCI Configuration Register Read

7-12                                                                                       SYM53C810A Data Manual
                                                                                                Electrical Characteristics
                                                                                        PCI Interface Timing Diagrams

                                 1          2              3                         4  5

                 CLK
(Driven by System)

               FRAME/    t1
  (Driven by Master)
                         t          t2  t1                        t2
                    AD/   1
  (Driven by Master)
                         Addr                      Data In
                 C_BE/                                                       t
  (Driven by Master)         In                                               2

                  PAR/   t1         t2
  (Driven by Master)
                         CMD                  Byte Enable
                 IRDY/                  t1
  (Driven by Master)               t2

                 TRDY/                               t2
(Driven by 53C810A)                     t1

                 STOP/                                                           t2
(Driven by 53C810A)
                                                              t3
              DEVSEL/
(Driven by 53C810A)                                           t3

                IDSEL        t1                t3
   (Driven by Master)
                                    t2

                         Figure 7-10: PCI Configuration Register Write

SYM53C810A Data Manual                                                                     7-13
                                                                                            Electrical Characteristics
                                                                                    PCI Interface Timing Diagrams

                               1  2                           3            4  5  6  7  8                    9

                     CLK
      (Driven by System)

                      FRAME/    t1                            Byte Enable         t3
           (Driven by Master)         t2
                                                                                          Data
                           AD   t1                                                        Out
      (Driven by Master-Addr;
                               Addr                                                   t2
               53C810A-Data)     In                                                            t3
                                                                                                       Out
                        C_BE/            t2
           (Driven by Master)   t1                                                   t2

                          PAR  CMD                                               t3
      (Driven by Master-Addr;
                                        t2                                       t3
               53C810A-Data)                t1

                        IRDY/              In
           (Driven by Master)                        t2

                                             t1

                     TRDY
      (Driven by 53C810A)

                     STOP/
      (Driven by 53C810A)

                  DEVSEL/
      (Driven by 53C810A)

                                                          t3

                                  Figure 7-11: Target Read

7-14                                                                                   SYM53C810A Data Manual
                                                                                           Electrical Characteristics
                                                                                   PCI Interface Timing Diagrams

                            1           2         3          4  5            6  7  8                   9

              CLK
(Driven by System)

                        t
                         1

           FRAME/              t2
 (Driven by Master)
                        t1          t1                                       t2
              AD/
(Driven by Master)      Addr                     Data In                      t2
                         In                     Byte Enable                               t1
           C_BE/                           t2                                                      t2
(Driven by Master)              t2
                                                                             t2
            PAR/        t1                                         t
(Driven by Master)                                                 3
                        CMD
                               t2                                  t
                                                                   3
                                    t1

IRDY/

(Driven by Master)                  t1

             TRDY/
(Driven by 53C810A)

             STOP/
(Driven by 53C810A)

           DEVSEL/
(Driven by 53C810A)

                                              t3

                                                  Figure 7-12: Target Write

SYM53C810A Data Manual                                                                                    7-15
                                                                                                                                        Electrical Characteristics
                                                                                                                                PCI Interface Timing Diagrams

                               1        2  3  4  5   6                               7  8              9           10  11  12   13                          14  15

                    CLK                                                                                                                                         t8
      (Driven by System)

                                    t7
         GPIO0_FETCH/
      (Driven by 53C810A)*

                                                                        t9                 t10
                                              t6
      GPIO1_MASTER/
      (Driven by 53C810A)*                                               t4
                                                                       t5
                    REQ/                                               t3
      (Driven by 53C810A)
                                                                           Addr Out
                      GNT/                                         t3
       (Driven by Arbiter)

                  FRAME/                                                                 t1
      (Driven by 53C810A)                                                               Data

                  AD/                                                                    In                                                           Data
                                                                                                                                                        In
           (Driven by                                                                              t2
      53C810A-Addr;                                                                                                        Addr Out

         Target-Data)

                  C_BE/                              CMD                                BE                                 CMD      BE
      (Driven by 53C810A)                                                                          t1
                                                 t3       t3                                                  t2
                        PAR/
                   (Driven by                        t3                                            t1
             53C810A-Addr;                            t3                                                       t2
                 Target-Data)                                                                                  t2

                       IRDY/                                                             t1
      (Driven by 53C810A)

                     TRDY/
      (Driven by Target)

                    STOP/
      (Driven by Target)

                  DEVSEL/
      (Driven by Target)

                                              Figure 7-13: Op Code Fetch, non-burst

7-16                                                                                                                                SYM53C810A Data Manual
                                                                                                   Electrical Characteristics
                                                                                           PCI Interface Timing Diagrams

                        1         2  3      4  5           6             7      9          10 11     12

              CLK                                                                                t8
(Driven by System)

                              t7
   GPIO0_FETCH/
(Driven by 53C810A)*

                                                   t9                                       t10

GPIO1_MASTER/                           t6
(Driven by 53C810A)*
                                                   t4
              REQ/
(Driven by 53C810A)

                GNT/
 (Driven by Arbiter)

                                                       t5

            FRAME/                                   t3
(Driven by 53C810A)                                                  t1

                                                  t3                        Data   Data In
                                                       Addr Out              In

                  AD/                          t3                                  t2
           (Driven by
      53C810A-Addr;                                    CMD                  BE                       CMD
         Target-Data)
                                               t3             t3
            C_BE/
(Driven by 53C810A)                                                                    t1

                 PAR/                                           Out                In       In
            (Driven by                                     t3
       53C810A-Addr;                                                                        t2
          Target-Data)
                                                   t3                       t1
                IRDY/
 (Driven by 53C810A)                                                                        t2

              TRDY/                                               t1                        t2
  (Driven by Target)

                STOP/
  (Driven by Target)

             DEVSEL/
  (Driven by Target)

                                     Figure 7-14: Burst Op Code Fetch

SYM53C810A Data Manual                                                                                    7-17
                                                                                                                    Electrical Characteristics
                                                                                                            PCI Interface Timing Diagrams

                              1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

                         CLK
      (Driven by System)

             GPIO0_FETCH/                           t9                   t10
      (Driven by 53C810A)*
                                t        t5
           GPIO1_MASTER/         6
       (Driven by 53C810A)
                                     t4
                          REQ/
       (Driven by 53C810A)               t3                   t
                                                               1
                          GNT/           t3                Data In
          (Driven by Arbiter)                 Addr
                                               Out                   t2
                      FRAME/
       (Driven by 53C810A)               t3

                         AD/                                                                   Data In
                 (Driven by                                                       Addr
            53C810A-Addr;                                                         Out
                Target-Data)
                                             CMD BE                               CMD  BE
                       C_BE/                   t3
      (Driven by 53C810A)                             Out      t1                      Out              In
                                                               In
                         PAR/                    t3
                 (Driven by                                           t2
            53C810A-Addr;
                Target-Data)

                        IRDY/
      (Driven by 53C810A)

                   TRDY/                                   t1
      (Driven by Target)                                            t2

                  STOP/                                    t1                 t2
      (Driven by Target)

                 DEVSEL/
      (Driven by Target)

                                                        Figure 7-15: Back to Back Read

7-18                                                                                                        SYM53C810A Data Manual
                                                                                       Electrical Characteristics
                                                                               PCI Interface Timing Diagrams

                        123                  456 7         8 9 10 11 12 13 14 15 16

                 CLK

(Driven by System)

       GPIO0_FETCH/       t                           t
 (Driven by 53C810A)*      9                           10

   GPIO1_MASTER/          t6
 (Driven by 53C810A)*
                                         t4
                  REQ/
 (Driven by 53C810A)               t5
                                    t3
                   GNT/
  (Driven by Arbiter)     t3                                  t3
                                Addr Data                  Addr Data
            FRAME/              Out Out                    Out Out
(Driven by 53C810A)
                          t3                                   t3
                 AD/            CMD BE                     CMD BE
(Driven by 53C810A)                  t3
                                                                           t3
                C_BE/                        t3
(Driven by 53C810A)                                                        t2
                                                  t1
                   PAR/                          t2
(Driven by 53C810A)                              t1

                   IRDY/
   (Driven by 53C810A)

                 TRDY/
   (Driven by Target)

                 STOP/
   (Driven by Target)

              DEVSEL/
   (Driven by Target)

                                             Figure 7-16: Back to Back Write

SYM53C810A Data Manual                                                               7-19
7-20

                                                                            1   2  3        4        5         6        7  8  9        10 11 12 13            14 15 16           17 18  19

                                                                       CLK            t9                          t 10
                                                     (Driven by System)
                                                                            t6
                                                                   GPIO0_
                        Figure 7-17: Burst Read                     FETCH/              t5
                                                   (Driven by 53C810A)             t4

                                                                   GPIO1_             t3
                                                                 MASTER/
                                                   (Driven by 53C810A)                t3         t3

                                                                     REQ/                   Addr Out Data Out                 Addr Out Data Out Data Out      Addr Out Data Out
                                                  (Driven by 53C810A)                                                                                            CMD BE
                                                                                   t3            t3
                                                                     GNT/
                                                     (Driven by Arbiter)                    CMD      BE                       CMD      BE

                                                                   FRAME                    t3                                t3
                                                   (Driven by 53C810A)
                                                                                                 t3
                                                                        AD
                                                  (Driven by 53C810A)                                                              t1                     t2

SYM53C810A Data Manual                                             C_BE/                                                           t1                     t2                                   Electrical Characteristics
                                                 (Driven by 53C8150A                                                                                                                        PCI Interface Timing Diagrams

                                                                     PAR
                                                 (Driven by 53C810A)

                                                                   IRDY/
                                                 (Driven by 53C810A)

                                                                 TRDY/
                                                   (Driven by Target)

                                                                  STOP/
                                                   (Driven by Target)

                                                               DEVSEL/
                                                     (Driven by Target)
SYM53C810A Data Manual                                                       1   2  3        4        5         6        7  8  9        10 11 12 13            14 15 16           17 18  19

                                                                        CLK            t9                          t 10
                                                      (Driven by System)
                                                                             t6
                                                                    GPIO0_
                        Figure 7-18: Burst Write                    FETCH/               t5
                                                    (Driven by 53C810A)             t4

                                                                    GPIO1_             t3
                                                                 MASTER/
                                                    (Driven by 53C810A)                t3         t3

                                                                      REQ/                   Addr Out Data Out                 Addr Out Data Out Data Out      Addr Out Data Out
                                                   (Driven by 53C810A)                                                                                            CMD BE
                                                                                    t3            t3
                                                                      GNT/
                                                      (Driven by Arbiter)                    CMD      BE                       CMD      BE

                                                                    FRAME                    t3                                t3
                                                    (Driven by 53C810A)
                                                                                                  t3
                                                                         AD
                                                   (Driven by 53C810A)                                                              t1                     t2

                                                                    C_BE/                                                           t1                     t2                                   Electrical Characteristics
                                                  (Driven by 53C810A)                                                                                                                        PCI Interface Timing Diagrams

                                                                      PAR
                                                  (Driven by 53C810A)

                                                                    IRDY/
                                                  (Driven by 53C810A)

                                                                  TRDY/
                                                    (Driven by Target)

                                                                  STOP/
                                                    (Driven by Target)

                                                                DEVSEL/
                                                     (Driven by Target)

7-21
                                                            Electrical Characteristics
                                                              PCI Interface Timings

PCI Interface Timings

                   Table 7-16: SYM53C810A PCI Timings

Symbol  Parameter                                      Min  Max  Unit

t1      Shared signal input setup time                 7    -    ns
t2
t3      Shared signal input hold time                  0    -    ns
t4
t5      CLK to shared signal output valid              -    11   ns
t6
t7      Side signal input setup time                   10   -    ns
t8
t9      Side signal input hold time                    0    -    ns
t10
        CLK to side signal output valid                -    12   ns

        CLK high to FETCH/ low                         -    20   ns

        CLK high to FETCH/ high                        -    20   ns

        CLK high to MASTER/ low                        -    20   ns

        CLK high to MASTER/ high                       -    20   ns

7-22                                                        SYM53C810A Data Manual
                                                                                  Electrical Characteristics
                                                                                              SCSI Timings

SCSI Timings

Initiator
Asynchronous Send

           SREQ/            n                                                    n+1
                                                                                       n+1
            SACK/       t1                     t2
        SD7-SD0,                                                            Valid n+1
                               n
             SDP/
                        t3                     t4

                            Valid n

                        Figure 7-19: Initiator Asynchronous Send Waveforms

                        Table 7-17: Initiator Asynchronous Send Timings (5 MB/s)

Symbol  Parameter                                  Min                            Max       Units
                                                                                            ns
t1      SACK/asserted from SREQ/ asserted          10                             -         ns
t2      SACK/deasserted from SREQ/ deasserted                                               ns
t3      Data setup to SACK/asserted                10                             -         ns
t4      Data hold from SSREQ/deasserted
                                                   55                             -

                                                   20                             -

SYM53C810A Data Manual                                                                             7-23
                                                                               Electrical Characteristics
                                                                                           SCSI Timings

Initiator
Asynchronous Receive

           SREQ/                      n          t2                         n+1
                               t1          n                                      n+1
            SACK/                        t4
                      t3                                                  Valid n+1
        SD7-SD0,              Valid n
             SDP/

                   Figure 7-20: Initiator Asynchronous Receive Waveforms

                   Table 7-18: Initiator Asynchronous Receive Timings (5MB/s)

Symbol  Parameter                                    Min                       Max     Units
                                                                                       ns
t1      SACK/asserted from SREQ/asserted             10                        -       ns
t2      SACK/deasserted from SREQ/deasserted                                           ns
t3      Data setup to SREQ/asserted                  10                        -       ns
t4      Data hold from SACK/asserted
                                                     0                         -

                                                     0                         -

7-24                                                                           SYM53C810A Data Manual
                                                                               Electrical Characteristics
                                                                                           SCSI Timings

Target
Asynchronous Send

           SREQ/            n                                                  n+1
                                                  t2
            SACK/                    t1
                                         n                                          n+1
        SD7-SD0,
             SDP/       t3                    t4                        Valid n+1

                            Valid n

                        Figure 7-21: Target Asynchronous Send Waveforms

                        Table 7-19: Target Asynchronous Send Timings (5 MB/s)

Symbol  Parameter                                 Min                          Max       Units
                                                                                         ns
t1      SREQ/ deasserted from SACK/ asserted      10                           -         ns
t2      SREQ/ asserted from SACK/ deasserted                                             ns
t3      Data setup to SREQ/ asserted              10                           -         ns
t4      Data hold from SACK/ asserted
                                                  55                           -

                                                  20                           -

SYM53C810A Data Manual                                                                          7-25
                                                                                 Electrical Characteristics
                                                                                             SCSI Timings

Target
Asynchronous Receive

                SREQ/      n                                                    n+1
                                                  t2
                SACK/         t1
                                 n                                                   n+1
           SD15-SD0,
        SDP1/, SDP0/   t3                     t4                            Valid n+1

                              Valid n

                       Figure 7-22: Target Asynchronous Receive Waveforms

                       Table 7-20: Target Asynchronous Receive Timings (5 MB/s)

Symbol  Parameter                                 Min                            Max      Units
                                                                                          ns
t1      SREQ/ deasserted from SACK/ asserted      10                             -        ns
t2      SREQ/ asserted from SACK/ deasserted                                              ns
t3      Data setup to SACK/ asserted              10                             -        ns
t4      Data hold from SREQ/ deasserted
                                                  0                              -

                                                  0                              -

7-26                                                                             SYM53C810A Data Manual
                                                                                 Electrical Characteristics
                                                                                             SCSI Timings

Initiator and
Target Synchronous Transfers

                                            t1      t2

      SREQ/                                 n                                  n+1
    or SACK/                                                                     Valid n+1
                                                                                 Valid n+1
                               t3      t4
                                   Valid n
          Send Data
    SD7-SD0, SDP/

                               t5      t6
    Receive Data                   Valid n

      SD15-SD0,
    SDP1/, SDP0/

                        Figure 7-23: Initiator and Target Synchronous Transfers

                        Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s)

Symbol Parameter                                        Min                      Max        Units
                                                                                            ns
t1  Send SREQ/ or SACK/ assertion pulse width           90                       -          ns
                                                                                            ns
t2  Send SREQ/ or SACK/ deassertion pulse width         90                       -          ns
                                                                                            ns
t1  Receive SREQ/ or SACK/ assertion pulse width        90                       -          ns
                                                                                            ns
t2  Receive SREQ/ or SACK/ deassertion pulse width      90                       -          ns

t3  Send data setup to SREQ/ or SACK/ asserted          55                       -

t4  Send data hold from SREQ/ or SACK/ asserted         100                      -

t5  Receive data setup to SREQ/ or SACK/ asserted       0                        -

t6  Receive data hold from SREQ/ or SACK/ asserted      45                       -

SYM53C810A Data Manual                                                                             7-27
                                                                                                                Electrical Characteristics
                                                                                                                            SCSI Timings

        Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock)

Symbol  Parameter                                                    Min  Max                                                  Units

t1      Send SREQ/ or SACK/ assertion pulse width                    35                                         -              ns
t2      Send SREQ/ or SACK/ deassertion pulse width
t1      Receive SREQ/ or SACK/ assertion pulse width                 35                                         -              ns
t2      Receive SREQ/ or SACK/ deassertion pulse width
t3      Send data setup to SREQ/ or SACK/ asserted                   20                                         -              ns
t4      Send data hold from SREQ/ or SACK/ asserted
t5      Receive data setup to SREQ/ or SACK/ asserted                20                                         -              ns
t6      Receive data hold from SREQ/ or SACK/ asserted
                                                                     33                                         -              ns

                                                                     45                                         -              ns

                                                                     0                                          -              ns

                                                                     10                                         -              ns

        Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock)

Symbol Parameter                                                     Min  Max                                                  Units

t1      Send SREQ/ or SACK/ assertion pulse width                    35                                         -              ns

t2      Send SREQ/ or SACK/ deassertion pulse width                  35                                         -              ns

t1      Receive SREQ/ or SACK/ assertion pulse width                 20                                         -              ns

t2      Receive SREQ/ or SACK/ deassertion pulse width               20                                         -              ns

t3      Send data setup to SREQ/ or SACK/ asserted                   33                                         -              ns

t4      Send data hold from SREQ/ or SACK/ asserted                  40                                         -              ns

t5      Receive data setup to SREQ/ or SACK/ asserted                0                                          -              ns

t6      Receive data hold from SREQ/ or SACK/ asserted               10                                         -              ns

* Transfer period bits (bits 6-4 in the SXFER register) are set to zero and the Extra Clock cycle of Data Setup bit (bit 7 in
SCNTL1) is set.

* * Analysis of system configuration is recommended due to reduced driver skew margin in differential systems.

Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in STEST3).

7-28                                                                                                               SYM53C810A Data Manual
                                                                                             Register Summary

Appendix A

Register Summary

Register 00 (80)                                               Register 02 (82)
                                                               SCSI Control Two (SCNTL2)
SCSI Control Zero (SCNTL0)                                     Read/Write
Read/Write

ARB1 ARB0 START WATN EPC        RES  AAP    TRG                SDU       RES  RES  RES  RES  RES              RES  RES

7      6    5           4    3  2    1      0                  7         6    5    4      3  2                1    0

Default>>>                                                     Default>>>

1      1    0           0    0  X    0      0                  0         X    X    X      X  X                X    X

Bit 7       ARB1 (Arbitration mode bit 1)                      Bit 7        SDU (SCSI Disconnect Unexpected)
Bit 6       ARB0 (Arbitration mode bit 0)                      Bits 6-0     Reserved
Bit 5       START (Start sequence)
Bit 4       WATN (Select with SATN/ on a start sequence)       Register 03 (83)
Bit 3       EPC (Enable parity checking)                       SCSI Control Three (SCNTL3)
Bit 2       Reserved                                           Read/Write
Bit 1       AAP (Assert SATN/ on parity error)
Bit 0       TRG (Target role)                                  RES SCF2 SCF1 SCF0 RES CCF2 CCF1 CCF0

                                                               7         6    5    4      3  2                1    0

Register 01 (81)                                               Default>>>
SCSI Control One (SCNTL1)
Read/Write                                                     X         0    0    0      X  0                0    0

EXC    ADB  DHP         CON  RST AESP IARB  SST                Bit 7        Reserved
                                                               Bits 6-4     SCF2-0 (Synchronous Clock
7      6    5           4    3  2    1      0                  Bit 3        Reserved
                                                               Bits 2-0     CCF2-0 (Clock Conversion Factor)

Default>>>

0      0    0           0    0  0    0      0

Bit 7       EXC (Extra clock cycle of data setup)
Bit 6       ADB (Assert SCSI data bus)
Bit 5       DHP (Disable Halt on Parity Error or ATN) (Tar-
            get Only)
Bit 4       CON (Connected)
Bit 3       RST (Assert SCSI RST/ signal)
Bit 2       AESP (Assert even SCSI parity (force bad parity))
Bit 1       IARB (Immediate Arbitration)
Bit 0       SST (Start SCSI Transfer)

SYM53C810A Data Manual                                                                                             A-1
Register Summary

Register 04 (84)                                               Register 05 (85)
SCSI Chip ID (SCID)                                            SCSI Transfer (SXFER)
Read/Write                                                     Read/Write

RES       RRE    SRE  RES  RES ENC2 ENC1 ENC0                  TP2       TP1  TP0  RES MO3 MO2 MO1 MO0

     7    6      5    4    3  2  1                          0  7         6    5    4       3             2  1         0

     Default>>>                                                Default>>>

     X    0      0    X    X  0  0                          0  0         0    0    X       0             0  0         0

Bit 7            Reserved                                      Bits 7-5     TP2-0 (SCSI Synchronous Transfer Period)
Bit 6            RRE (Enable Response to                       Bit 4        Reserved
                 Reselection)                                  Bits 3-0     MO3-MO0 (Max SCSI synchronous offset)
Bit 5            SRE (Enable Response to Selection)
Bit 4-3          Reserved                                      Register 06 (86)
Bits 2-0         Encoded SYM53C810A Chip SCSI ID, bits 2-0     SCSI Destination ID (SDID)
                                                               Read/Write

                                                               RES       RES  RES  RES     RES ENC2 ENC1 ENC0

                                                               7         6    5    4       3             2  1         0

                                                               Default>>>

                                                               X         X    X    X       X             0  0         0

                                                               Bits 7-3     Reserved
                                                               Bits 2-0     Encoded destination SCSI ID

                                                               Register 07 (87)
                                                               General Purpose (GPREG)
                                                               Read/Write

                                                               RES       RES  RES  RES     RES  RES GPIO1 GPIO0

                                                               7         6    5    4       3             2  1         0

                                                               Default>>>

                                                               X         X    X    X       X             X  0         0

                                                               Bits 7-2     Reserved
                                                               Bits 1-0     GPIO1-GPIO0 (General Purpose)

                                                               Register 08 (88)
                                                               SCSI First Byte Received (SFBR)
                                                               Read/Write

                                                               1B7       1B6  1B5  1B4     1B3  1B2         1B1       1B0

                                                               7         6    5    4       3             2  1         0

                                                               Default>>>

                                                               0         0    0    0       0             0  0         0

A-2                                                                                             SYM53C810A Data Manual
                                                                                                 Register Summary

Register 09 (89)                                        Register 0C (8C)
SCSI Output Control Latch (SOCL)                        DMA Status (DSTAT)
Read /Write                                             Read Only

REQ       ACK  BSY      SEL      ATN MSG     C/D  I/O   DFE MDPE       BF   ABRT SSI             SIR     RES  IID

7         6    5        4        3        2  1    0     7         6    5    4      3             2       1    0

Default>>>                                              Default>>>

0         0    0        0        0        0  0    0     1         0    0    0      0             0       X    0

Bit 7        REQ(Assert SCSI REQ/ signal)               Bit 7        DFE (DMA FIFO empty)
Bit 6        ACK(Assert SCSI ACK/ signal)               Bit 6        MDPE (Master Data Parity Error)
Bit 5        BSY(Assert SCSI BSY/ signal)               Bit 5        BF (Bus fault)
Bit 4        SEL(Assert SCSI SEL/ signal)               Bit 4        ABRT (Aborted)
Bit 3        ATN(Assert SCSI ATN/ signal)               Bit 3        SSI (Single step interrupt)
Bit 2        MSG(Assert SCSI MSG/ signal)               Bit 2        SIR (SCRIPTS interrupt
Bit 1        C/D(Assert SCSI C_D/ signal)                            instruction received)
Bit 0        I/O(Assert SCSI I_O/ signal)               Bit 1        Reserved
                                                        Bit 0        IID (Illegal instruction detected)

Register 0A (8A)                                        Register 0D (8D)
SCSI Selector ID (SSID)                                 SCSI Status Zero (SSTAT0)
Read Only                                               Read Only

VAL       RES  RES      RES      RES ENID2 ENID1 ENID0

7         6    5        4        3        2  1    0     ILF       ORF  OLF  AIP    LOA WOA               RST SDP0/

Default>>>                                              7         6    5    4      3             2       1    0

0         X    X        X        X        0  0    0     Default>>>

                                                        0         0    0    0      0             0       0    0

Bit 7        VAL (SCSI Valid Bit)                       Bit 7        ILF (SIDL full)
Bits 6-3     Reserved                                   Bit 6        ORF (SODR full)
Bits 2-0     Encoded Destination SCSI ID                Bit 5        OLF (SODL full)
                                                        Bit 4        AIP (Arbitration in progress)
Register 0B (8B)                                        Bit 3        LOA (Lost arbitration)
SCSI Bus Control Lines (SBCL)                           Bit 2        WOA (Won arbitration)
Read Only                                               Bit 1        RST/ (SCSI RST/ signal)
                                                        Bit 0        SDP/ (SCSI SDP/ parity signal)

REQ       ACK  BSY      SEL      ATN MSG     C/D  I/O

7         6    5        4        3        2  1    0

Default>>>                                              Register 0E (8E)
                                                        SCSI Status One (SSTAT1)
X         X    X        X        X        X  X    X     Read Only

Bit 7        REQ (SREQ/ status)                         FF3       FF2  FF1  FF0 SDP0L MSG                C/D  I/O
Bit 6        ACK (SACK/ status)
Bit 5        BSY (SBSY/ status)                         7         6    5    4      3             2       1    0
Bit 4        SEL (SSEL/ status)
Bit 3        ATN SATN/ status)                          Default>>>
Bit 2        MSG (SMSG/ status)
Bit 1        C/D (SC_D/ status)                         0         0    0    0      X             X       X    X
Bit 0        I/O (SI_O/ status)
                                                        Bits 7-4     FF3-FF0 (FIFO flags)
                                                        Bit 3        SDPL (Latched SCSI parity)
                                                        Bit 2        MSG (SCSI MSG/ signal)
                                                        Bit 1        C/D (SCSI C_D/ signal)
                                                        Bit 0        I/O (SCSI I_O/ signal)

SYM53C810A Data Manual                                                                                        A-3
Register Summary

Register 0F (8F)                                            Register 1A (9A)
SCSI Status Two (SSTAT2)                                    Chip Test Two (CTEST2)
(Read Only)                                                 Read Only

RES       RES    RES  RES  RES           RES LDSC RES       DDIR SIGP      CIO  CM    RES TEOP DREQ DACK

     7    6      5    4       3          2        1    0    7         6    5    4     3    2                 1    0

     Default>>>                                             Default>>>

     X    X      X    X       X          X        1    X    0         0    X    X     0    0                 0    1

Bits 7-2         Reserved                                   Bit 7        DDIR (Data transfer direction)
Bit 1            LDSC (Last Disconnect)                     Bit 6        SIGP (Signal process)
Bit 0            Reserved                                   Bit 5        CIO (Configured as I/O)
                                                            Bit 4        CM (Configured as memory)
Registers 10-13 (90-93)                                     Bit 3        Reserved
Data Structure Address (DSA)                                Bit 2        TEOP (SCSI true end of process)
Read/Write                                                  Bit 1        DREQ (Data request status)
                                                            Bit 0        DACK (Data acknowledge status)

Register 14 (94)                                            Register 1B (9B)
Interrupt Status (ISTAT)                                    Chip Test Three (CTEST3)
(Read/Write)                                                Read/Write

ABRT SRST SIGP SEM CON INTF                       SIP  DIP  V3        V2   V1   V0    FLF  CLF               FM   WRIE

     7    6      5    4       3          2        1    0    7         6    5    4     3    2                 1    0

     Default>>>                                             Default>>>

     0    0      0    0       0          0        0    0    X         X    X    X     0    0                 0    0

Bit 7            ABRT (Abort operation)                     Bits 7-4     V3-V0 (Chip revision level)
Bit 6            SRST (Software reset)                      Bit 3        FLF (Flush DMA FIFO)
Bit 5            SIGP (Signal process)                      Bit 2        CLF (Clear DMA FIFO)
Bit 4            SEM (Semaphore)                            Bit 1        FM (Fetch pin mode)
Bit 3            CON (Connected)                            Bit 0        WRIE (Write and Invalidate Enable)
Bit 2            INTF (Interrupt on the Fly)
Bit 1            SIP (SCSI interrupt pending)               Registers 1C-1F (9C-9F)
Bit 0            DIP (DMA interrupt pending)                Temporary (TEMP)
                                                            Read/Write

Register 18 (98)                                            Register 20 (A0)
Chip Test Zero (CTEST0)                                     DMA FIFO (DFIFO)
Read/Write                                                  Read/Write

Register 19 (99)                                            RES       BO6  BO5  BO4   Bo3  BO2               BO1  BO0
Chip Test One (CTEST1)
Read Only                                                   7         6    5    4     3    2                 1    0

                                                            Default>>>

FMT3 FMT2 FMT1 FMT0 FFL3 FFL2 FFL1 FFL0                     X         0    0    0     0    0                 0    0

     7    6      5    4       3          2        1    0    Bit 7        Reserved
                                                            Bits 6-0     BO6-BO0 (Byte offset counter)
     Default>>>

     1    1      1    1       0          0        0    0

Bits 7-4         FMT3-0 (Byte empty in DMA FIFO)
Bits 3-0         FFL3-0 (Byte full in DMA FIFO)

A-4                                                                                        SYM53C810A Data Manual
                                                                                               Register Summary

Register 21 (A1)                                               Registers 28-2B (A8-AB)
Chip Test Four (CTEST4)                                        DMA Next Address (DNAD)
Read/Write                                                     Read/Write

BDIS ZMOD ZSD SRTM MPEE FBL2 FBL1 FBL0

7         6    5        4    3    2             1           0  Registers 2C-2F (AC-AF)
                                                               DMA SCRIPTS Pointer (DSP)
Default>>>                                                     Read/Write

0         0    0        0    0    0             0           0

Bit 7        BDIS (Burst Disable)                              Registers 30-33 (B0-B3)
Bit 6        ZMOD (High impedance mode)                        DMA SCRIPTS Pointer Save (DSPS)
Bit 5        ZSD (SCSI Data High Impedance)                    Read/Write
Bit 4        SRTM (Shadow Register Test Mode)
Bit 3        MPEE (Master Parity Error Enable)
Bits 2-0     FBL2-FBL0 (FIFO byte control)

Register 22 (A2)                                               Registers 34-37 (B4-B7)
Chip Test Five (CTEST5)                                        Scratch Register A (SCRATCH A)
Read/Write                                                     Read/Write

ADCK BBCK RES MASR DDIR RES                     RES  RES

7         6    5        4    3    2             1           0  Register 38 (B8)
                                                               DMA Mode (DMODE)
Default>>>                                                     Read/Write

0         0    X        0    0    X             X           X

Bit 7        ADCK (Clock address incrementor)                  BL1      BL0  SIOM DIOM ERL ERMP BOF                 MAN
Bit 6        BBCK (Clock byte counter)
Bit 5        Reserved                                          7        6    5   4      3      2               1    0
Bit 4        MASR (Master control for set or reset pulses)
Bit 3        DDIR (DMA direction)                              Default>>>
Bits 2-0     Reserved
                                                               0        0    0   0      0      0               0    0

Register 23 (A3)                                               Bit 7-6     BL1-BL0 (Burst length)
Chip Test Six (CTEST6)                                         Bit 5       SIOM (Source I/O-Memory Enable)
Read/Write                                                     Bit 4       DIOM (Destination I/O-Memory Enable)
                                                               Bit 3       ERL (Enable Read Line)
                                                               Bit 2       ERMP (Enable Read Multiple)
                                                               Bit 1       BOF (Burst Op Code Fetch Enable)
                                                               Bit 0       MAN (Manual Start Mode)

DF7       DF6  DF5      DF4  DF3  DF2           DF1  DF0

7         6    5        4    3    2             1           0

Default>>>                                                     Register 39 (B9)
                                                               DMA Interrupt Enable (DIEN)
0         0    0        0    0    0             0           0  Read/Write

Bits 7-0 DF7-DF0 (DMA FIFO)

                                                               RES MDPE      BF  ABRT SSI      SIR             RES  IID

                                                               7        6    5   4      3      2               1    0

Registers 24-26 (A4-A6)                                        Default>>>
DMA Byte Counter (DBC)
Read/Write                                                     X        0    0   0      0      0               X    0

Register 27 (A7)                                               Bit 7       Reserved
DMA Command (DCMD)                                             Bit 6       MDPE (Master Data Parity Error)
Read/Write                                                     Bit 5       BF (Bus fault)
                                                               Bit 4       ABRT (Aborted)
                                                               Bit 3       SSI (Single step interrupt)
                                                               Bit 2       SIR (SCRIPTS interrupt
                                                                           instruction received
                                                               Bit 1       Reserved
                                                               Bit 0       IID (Illegal instruction detected)

SYM53C810A Data Manual                                                                                              A-5
Register Summary

Register 3A (BA)                                          Register 41 (C1)
Scratch Byte Register (SBR)                               SCSI Interrupt Enable One (SIEN1)
Read/Write                                                Read/Write

                                                          RES       RES  RES  RES  RES        STO  GEN  HTH

Register 3B (BB)                                          7         6    5    4    3          2    1                0
DMA Control (DCNTL)
Read/Write                                                Default>>>

                                                          X         X    X    X    X          0    0                0

CLSE PFF         PFEN SSM IRQM STD              IRQD COM  Bits 7-3     Reserved
                                                          Bit 2        STO (Selection or Reselection Time-out)
     7  6        5    4      3      2           1    0    Bit 1        GEN (General Purpose Timer Expired)
                                                          Bit 0        HTH (Handshake to Handshake timer Expired)
     Default>>>

     0  0        0    0      0      0           0    0

Bit 7            CLSE (Cache Line Size Enable)            Register 42 (C2)
Bit 6            PFF (Pre-Fetch Flush)                    SCSI Interrupt Status Zero (SIST0)
Bit 5            PFEN (Pre-fetch Enable)                  Read Only
Bit 4            SSM (Single-step mode)
Bit 3            IRQM (IRQ Mode)                          M/A       CMP  SEL  RSL  SGE        UDC  RST  PAR
Bit 2            STD (Start DMA operation)
Bit 1            IRQD (IRQ Disable)                       7         6    5    4    3          2    1                0
Bit 0            COM (53C700 compatibility)
                                                          Default>>>

                                                          0         0    0    0    0          0    0                0

Register 3C-3F (BC-BF)                                    Bit 7        M/A (Initiator Mode: Phase Mismatch; Target
Adder Sum Output (ADDER)                                               Mode: SATN/ Active)
Read Only                                                 Bit 6        CMP (Function Complete)
                                                          Bit 5        SEL (Selected)
Register 40 (C0)                                          Bit 4        RSL (Reselected)
SCSI Interrupt Enable Zero (SIEN0)                        Bit 3        SGE (SCSI Gross Error)
Read/Write                                                Bit 2        UDC (Unexpected Disconnect)
                                                          Bit 1        RST (SCSI RST/ Received)
                                                          Bit 0        PAR (Parity Error)

M/A     CMP      SEL  RSL    SGE  UDC           RST  PAR

     7  6        5    4      3      2           1    0    Register 43 (C3)
                                                          SCSI Interrupt Status One (SIST1)
     Default>>>                                           Read Only

     0  0        0    0      0      0           0    0

Bit 7            M/A (SCSI Phase Mismatch -               RES       RES  RES  RES  RES        STO  GEN  HTH
                 Initiator Mode; SCSI ATN
Bit 6            Condition - Target Mode)                 7         6    5    4    3          2    1                0
Bit 5            CMP (Function Complete)
Bit 4            SEL (Selected)                           Default>>>
Bit 3            RSL (Reselected)
Bit 2            SGE (SCSI Gross Error)                   X         X    X    X    X          0    0                0
Bit 1            UDC (Unexpected Disconnect)
Bit 0            RST (SCSI Reset Condition)               Bits 7-3     Reserved
                 PAR (SCSI Parity Error)                  Bit 2        STO (Selection or Reselection Time-out)
                                                          Bit 1        GEN (General Purpose Timer Expired)
                                                          Bit 0        HTH (Handshake-to-Handshake Timer Expired)

                                                          Register 44 (C4)
                                                          SCSI Longitudinal Parity (SLPAR)
                                                          Read/Write

A-6                                                                                     SYM53C810A Data Manual
                                                                                                  Register Summary

Register 46 (C6)                                         Register 4A (CA)
Memory Access Control (MACNTL)                           Response ID (RESPID)
Read/Write                                               Read/Write

TYP3 TYP2 TYP1 TYP0 DWR DRD                PSCPT SCPTS

7         6    5        4    3        2    1        0    Register 4C (CC)
                                                         SCSI Test Zero (STEST0)
Default>>>                                               Read Only

0         1    0        0    0        0    0        0

Bits 7-4     TYP3-0 (Chip Type)                          RES       SSAID SSAID SSAID  SLT         ART  SOZ SOM
Bit 3        DWR (DataWR)
Bit 2        DRD (DataRD)                                          2    1    0
Bit 1        PSCPT (Pointer SCRIPTS)
Bit 0        SCPTS (SCRIPTS)                             7         6    5    4        3           2    1       0

                                                         Default>>>

                                                         X         X    X    X        0           X    1       1

Register 47 (C7)                                         Bit 7        Reserved
General Purpose Pin Control (GPCNTL)                     Bits 6-4     SSAID (SCSI Selected As ID)
Read/Write                                               Bit 3        SLT (Selection response logic test)
                                                         Bit 2        ART (Arbitration Priority Encoder Test)
ME        FE   RES      RES  RES      RES GPIO1 GPIO0    Bit 1        SOZ (SCSI Synchronous Offset Zero)
                                                         Bit 0        SOM (SCSI Synchronous Offset Maximum)

7         6    5        4    3        2    1        0

Default>>>

0         0    X        0    1        1    1        1    Register 4D (CD)
                                                         SCSI Test One (STEST1)
Bit 7        Master Enable                               Read/Write
Bit 6        Fetch Enable
Bit 5        Reserved                                    SCLK SISO RES       RES      RES         RES  RES     RES
Bits 1-0     GPIO1_EN­ GPIO0_EN (GPIO Enable)
                                                         7         6    5    4        3           2    1       0

                                                         Default>>>

Register 48 (C8)                                         0         0    X    X        X           X    X       X
SCSI Timer Zero (STIME0)
Read /Write                                              Bit 7        SCLK
                                                         Bit 6        SISO (SCSI Isolation Mode)
HTH       HTH  HTH      HRH  SEL      SEL  SEL      SEL  Bits 5-0     Reserved

7         6    5        4    3        2    1        0

Default>>>                                               Register 4E (CE)
                                                         SCSI Test Two (STEST2)
0         0    0        0    0        0    0        0    Read/Write

Bits 7-4     HTH (Handshake-to-Handshake Timer Period)   SCE       ROF  RES  SLB      SZM         RES  EXT     LOW
Bits 3-0     SEL (Selection Time-Out)

                                                         7         6    5    4        3           2    1       0

Register 49 (C9)                                         Default>>>
SCSI Timer One (STIME1)
Read/Write                                               0         0    X    0        0           X    0       0

RES       RES  RES      RES GEN3 GEN2 GEN1 GEN0          Bit 7        SCE (SCSI Control Enable)
                                                         Bit 6        ROF (Reset SCSI Offset)
7         6    5        4    3        2    1        0    Bit 5        Reserved
                                                         Bit 4        SLB (SCSI Loopback Mode)
Default>>>                                               Bit 3        SZM (SCSI High-Impedance Mode)
                                                         Bit 2        Reserved
X         X    X        X    0        0    0        0    Bit 1        EXT( Extend SREQ/SACK
                                                                      filtering)
Bits 7-4     Reserved                                    Bit 0        LOW (SCSI Low level Mode)
Bits 3-0     GEN3-0 (General Purpose Timer Period)

SYM53C810A Data Manual                                                                                         A-7
Register Summary

Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write

TE      STR      HSC  DSI  RES  TTM  CSF                  STW

     7  6        5    4     3   2    1                    0

     Default>>>

     0  0        0    0     X   0    0                    0

Bit 7            TE (TolerANT Enable)
Bit 6            STR (SCSI FIFO Test Read)
Bit 5            HSC (Halt SCSI Clock)
Bit 4            DSI (Disable Single Initiator Response)
Bit 3            Reserved
Bit 2            TTM (Timer Test Mode)
Bit 1            CSF (Clear SCSI FIFO)
Bit 0            STW (SCSI FIFO Test Write)

Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only

Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write

Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only

Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write)

A-8                                                            SYM53C810A Data Manual
                                                                      Mechanical Drawing

Appendix B

Mechanical Drawing

                                       23.9 ± 0.25
                                       20.0 ± 0.10

                                           18.85

                               Pin 81               Pin 51  0.22 min
                                                            0.38 max
 17.9 14.0 12.35               100-Pin Quad Flat Pack
± 0.25 ± 0.1                                                0.65

                                                    Pin 31

                        Pin 1

                                                            min      2.8
                                                            0.13  ± 0.025

   1.3
± 0.025

007
     0.8 ± 0.15

SYM53C810A Data Manual                                                     B-1
Mechanical Drawing

B-2                 SYM53C810A Data Manual
                                                                                                                                                                   Index

Index

Numerics                                            Assert SATN/ on parity error bit 5-6
3.3/5 Volt PCI interface 2-3                        Assert SCSI ACK bit 5-15
53C700 compatibility bit 5-35                       Assert SCSI ATN/ bit 5-15
                                                    Assert SCSI BSY/ bit 5-15
A                                                   Assert SCSI C_D/ bit 5-15
AAP bit 5-6                                         Assert SCSI data bus bit 5-7
Abort operation bit 5-20                            Assert SCSI I_O/ bit 5-15
Aborted bit 5-17, 5-33                              Assert SCSI MSG/ bit 5-15
ABRT bit 5-17, 5-20, 5-33                           Assert SCSI REQ/ signal bit 5-15
absolute maximum stress ratings 7-1                 Assert SCSI RST/ signal bit 5-7
AC characteristics 7-9­7-10                         Assert SCSI SEL/ bit 5-15
                                                    ATN bit 5-15, 5-16
    clock timing 7-9
    interrupt output 7-10                           B
ACK bit 5-15, 5-16                                  BBCK bit 5-27
active negation. See TolerANT                       BDIS bit 5-26
ADB bit 5-7                                         benefits summary 1-3
ADCK bit 5-27                                       BF bit 5-16, 5-33
ADDER register 5-35                                 bidirectional signals 7-5­??
Adder Sum Output register 5-35                      BL1-BL0 bits 5-31
Additional Interface Pins 4-7                       Block Move Instructions 6-4
Address and Data Pins 4-4                           BO6-BO0 bits 5-26
AESP bit 5-7                                        BOF bit 5-32
AIP bit 5-18                                        BSY bit 5-15, 5-16
ARB1-0 bits 5-5                                     Burst Disable bit 5-26
arbitration                                         Burst length bits 5-31
    arbitration mode bits 5-5                       Burst Mode Fetch Enable bit 5-32
    arbitration pins 4-5                            Bus fault bit 5-16, 5-33
Arbitration in progress bit 5-18                    Byte empty in DMA FIFO bits 5-23
Arbitration mode bits 5-5                           Byte full in DMA FIFO bits 5-23
Arbitration Priority Encoder Test bit 5-44          Byte offset counter bits 5-26
ART bit 5-44
Assert even SCSI parity (force bad parity) bit 5-7

SYM53C810A Data Manual                                                                    I-1
Index

C                                                    CTEST4 register 5-26
C_D bit 5-15, 5-16, 5-19                             CTEST5 register 5-27
Cache Line Size Enable bit 5-34, A-6                 CTEST6 register 5-28
cache mode, see PCI cache mode 3-2
capacitance 7-3                                      D
CCF2-0 bits 5-10                                     DACK bit 5-24
chip block diagram 1-5                               Data acknowledge status bit 5-24
chip revision level bits 5-24                        data path 2-7
Chip Test Five register 5-27                         Data request status bit 5-24
Chip Test Four register 5-26                         Data Structure Address register 5-20
Chip Test One register 5-23                          Data transfer direction bit 5-23
Chip Test Six register 5-28                          DataRD bit 5-41
Chip Test Two register 5-23                          DataWR bit
Chip Test Zero register 5-22
Chip Type bits 5-41                                      DWR bit 5-41
CIO bit 5-23                                         DBC register 5-28
Clear SCSI FIFO bit 5-47                             DC characteristics 7-1
Clock address incrementor bit 5-27
Clock byte counter bit 5-27                              absolute maximum stress ratings 7-1
Clock Conversion Factor bits 5-10                        bidirectional signals 7-5
CLSE bit 5-34, A-6                                       capacitance 7-3
CM bit 5-23                                              input signals 7-3
CMP bit 5-36, 5-38                                       operating conditions 7-2
COM bit 5-35                                             output signals 7-4
CON bit 5-7, 5-21                                        SCSI signals 7-2
configuration registers. See PCI configuration reg-  DCMD register 5-29
                                                     DCNTL register 5-34
         isters                                      DDIR bit 5-23, 5-27
Configured as I/O bit 5-23                           Destination I/O-Memory Enable bit 5-32
Configured as memory bit 5-23                        determining the data transfer rate 2-11
Connected bit 5-7, 5-21                              DF7-DF0 bits 5-28
CSF bit 5-47                                         DFE bit 5-16
CTEST0 register 5-22                                 DFIFO register 5-26
CTEST1 register 5-23                                 DHP bit 5-7
CTEST2 register 5-23                                 DIEN register 5-33
                                                     DIOM bit 5-32
                                                     DIP bit 5-22
                                                     Disable Halt on Parity Error or ATN bit 5-7
                                                     Disable Single Initiator Response bit 5-47

I-2                                                  SYM53C810A Data Manual
                                         Index

DMA Byte Counter register 5-28           ERL bit 5-32
DMA Command register 5-29                Error Reporting Pins 4-6
DMA Control register 5-34                EXC bit 5-7
DMA core 2-1                             EXT bit 5-46
DMA direction bit 5-27                   Extend SREQ/SACK filtering bit 5-46
DMA FIFO 2-6                             Extra clock cycle of data setup bit 5-7
DMA FIFO bits 5-28
DMA FIFO empty bit 5-16                  F
DMA FIFO register 5-26                   FBL2-FBL0 bits 5-27
DMA Interrupt Enable register 5-33       Fetch Enable bit 5-41
DMA interrupt pending bit 5-22           fetch op code bursting 2-3
DMA Mode register 5-31                   FF3-FF0 bits 5-18
DMA Next Address register 5-29           FFL3-0 bits 5-23
DMA SCRIPTS Pointer register 5-30        FIFO byte control bits 5-27
DMA SCRIPTS Pointer Save register 5-30   FIFO flags bits 5-18
DMA Status register 5-16                 FMT3-0 bits 5-23
DMODE register 5-31                      Function Complete bit 5-36, 5-38
DNAD register 5-29
DRD bit 5-41                             G
DREQ bit 5-24                            GEN bit 5-37, 5-40
DSA register 5-20                        GEN3-0 bits 5-43
DSI bit 5-47                             general description 1-1
DSP register 5-30                        General purpose bits 5-14
DSPS register 5-30                       General Purpose Pin Control register 5-41
DSTAT register 5-16                      General Purpose register 5-14
                                         General Purpose Timer Expired bit 5-37, 5-40
E                                        General Purpose Timer Period bits 5-43
ease of use 1-3                          GPCNTL register 5-41
Enable parity checking bit 5-6           GPIO Enable bits 5-41
Enable Read Line bit 5-32                GPIO1-0 bits 5-14
Enable Read Multiple bit 5-32, A-5       GPIO1EN_GPIO0EN bits 5-41
Enable Response to Reselection bit 5-11  GPREG register 5-14
Enable Response to Selection bit 5-11
Encoded Chip SCSI ID, bits 2-0 5-11      H
Encoded Destination SCSI ID bits 5-15    Halt SCSI Clock bit
Encoded destination SCSI ID bits 5-13
EPC bit 5-6                                  HSC bit 5-46
                                         Handshake to Handshake timer Expired bit 5-38
SYM53C810A Data Manual                   Handshake-to-Handshake Timer Expired bit 5-40

                                                                                                                      I-3
Index

Handshake-to-Handshake Timer Period bits 5-42  IRQ Disable bit 5-34, A-6
High impedance mode bit 5-26                   IRQ Mode bit 5-34
HTH bit 5-38, 5-40                             IRQD bit 5-34, A-6
                                               IRQM bit 5-34
I                                              ISTAT register 5-20
I/O bit 5-19
I/O Instructions 6-8                           L
I_O bit 5-15                                   Last Disconnect bit 5-19
IARB bit 5-8                                   Latched SCSI parity bit 5-18
IID bit 5-17, 5-33                             LDSC bit 5-19
Illegal instruction detected bit 5-17, 5-33    LOA bit 5-18
Immediate arbitration bit 5-8                  Load and Store instructions
Initiator Mode
                                                   no flush option 6-24
    Phase Mismatch 5-38                            prefetch unit and Store instructions 2-2, 6-24
input signals 7-3                              load and store instructions 6-24
instruction prefetch. See SCRIPTS instruction  Lost arbitration bit 5-18
                                               LOW bit 5-46
         prefetching
instruction set 6-1­6-25                       M
instructions                                   M/A bit 5-36, 5-38
                                               MACNTL register 5-41
    block move 6-4                             MAN bit 5-32
    I/O 6-8                                    Manual Start Mode bit 5-32
    load and store 6-24                        MASR bit 5-27
    memory move 6-21                           Master control for set or reset pulses bit 5-27
    read/write 6-14                            Master Data Parity Error bit 5-16
    transfer control 6-17
Interface Control Pins 4-5                         MDPE bit 5-33
Interrupt on the Fly bit 5-21                  Master Enable bit 5-41
interrupt output timings 7-10                  Master Parity Error Enable bit 5-27
Interrupt Status register 5-20                 Max SCSI Synchronous Offset bits 5-13
interrupts                                     MDPE bit 5-16
    fatal vs. non-fatal interrupts 2-14        Memory Access Control register 5-41
    halting 2-15                               Memory Move Instructions 6-21
    IRQ Disable bit 2-14, 5-34, A-6            Memory Move instructions
    masking 2-14
    polling vs. hardware 2-13                      and SCRIPTS instruction prefetching 2-2
    registers 2-13                                 No Flush option 6-23
    stacked interrupts 2-15                    Memory Read Line command 3-4
INTF bit 5-21                                  Memory Read Multiple command 3-4

I-4                                            SYM53C810A Data Manual
                                                                              Index

Memory Write and Invalidate command 3-3      Memory Access Control 5-41
    Write and Invalidate Mode bit 3-7        register address map 5-4
                                             Response ID Zero 5-43
move to/from SFBR cycles 6-14                Scratch Register A 5-31
MPEE bit 5-27                                Scratch Register B 5-49
MSG bit 5-15, 5-16, 5-19                     SCSI Bus Control Lines 5-16
                                             SCSI Bus Data Lines 5-48
N                                            SCSI Chip ID 5-11
NFMMOV instruction 6-23                      SCSI Control One register 5-7
No Flush Memory-to-Memory Move 6-23          SCSI Control Register Two 5-9
                                             SCSI Control Three 5-9
O                                            SCSI Control Zero 5-5
OLF bit 5-17                                 SCSI Destination ID 5-13
op code fetch bursting 2-2                   SCSI First Byte Received 5-14
operating conditions 7-2                     SCSI Input Data Latch 5-47
operating registers                          SCSI Interrupt Enable One 5-37
                                             SCSI Interrupt Enable Zero 5-36
    Adder Sum Output 5-35                    SCSI Interrupt Status One 5-40
    Chip Test Five 5-27                      SCSI Interrupt Status Zero 5-38
    Chip Test Four 5-26                      SCSI Longitudinal Parity 5-40
    Chip Test One 5-23                       SCSI Output Control Latch 5-15
    Chip Test Six 5-28                       SCSI Output Data Latch 5-48
    Chip Test Three 5-24                     SCSI Selector ID 5-15
    Chip Test Two 5-23                       SCSI Status One 5-18
    Chip Test Zero 5-22                      SCSI Status Two 5-19
    Data Structure Address 5-20              SCSI Status Zero 5-17
    DMA Byte Counter 5-28                    SCSI Test One 5-45
    DMA Command 5-29                         SCSI Test Three 5-46
    DMA Control 5-34                         SCSI Test Two 5-45
    DMA FIFO 5-26                            SCSI Test Zero 5-44
    DMA Interrupt Enable 5-33                SCSI Timer One 5-43
    DMA Mode 5-31                            SCSI Timer Zero 5-42
    DMA Next Address 5-29                    SCSI Transfer 5-11
    DMA SCRIPTS Pointer 5-30                 Temporary Stack 5-25
    DMA SCRIPTS Pointer Save 5-30        ORF bit 5-17
    DMA Status 5-16                      output signals 7-4
    DMA Watchdog Timer 5-33
    general information 5-1
    General Purpose 5-14
    General Purpose Pin Control 5-41
    Interrupt Status 5-20

SYM53C810A Data Manual                                                        I-5
Index

P                                                  Latency Timer 3-10
PAR bit 5-37, 5-39                                 Max_Lat 3-11
Parity 2-3­2-5                                     Min_Gnt 3-11
                                                   Revision ID 3-10
    Assert even SCSI parity bit 5-7                Status 3-8
    Assert SATN/ on parity error bit 5-6           Vendor ID 3-7
    Disable Halt on Parity Error bit 5-7       PCI configuration space 3-1
    Enable parity checking bit 5-6             PCI I/O space 3-1
    Master Data Parity Error bit 5-33          PCI memory space 3-1
    Master Parity Error Enable bit 5-27        PFEN bit 5-34, A-6
    Parity Error bit 5-39                      PFF bit 5-34, A-6
    SCSI Parity Error bit 5-37                 Phase Mismatch bit 5-38
Parity Error bit 5-39                          pins
                                                   additional interface pins 4-7
PCI                                                address and data pins 4-4
    addressing 3-1                                 arbitration pins 4-5
    bus commands and functions supported 3-1       error reporting pins 4-6
                                                   interface control pins 4-5
PCI addressing 3-1                                 SCSI pins 4-6
PCI bus commands and functions supported 3-1       system pins 4-4
PCI cache mode 2-3, 3-2                        Pointer SCRIPTS bit
                                                   PSCPT bit 5-41
    Cache Line Size Enable bit 5-34, A-6       Power and Ground Pins 4-2
    Cache Line Size register 3-10              Pre-fetch Enable bit 5-34, A-6
    Enable Read Line bit 5-32                  Pre-Fetch Flush bit 5-34, A-6
    Enable Read Multiple bit 5-32, A-5         prefetching
    Memory Read Line command 3-4               prefetching. See SCRIPTS instruction
    Memory Read Multiple command 3-4
    Memory Write and Invalidate command 3-3    R
                                               Read Multiple commands
         Write and Invalidate Mode bit 3-7
    Write and Invalidate Enable bit 5-25, A-4      Enable Read Multiple bit 5-32, A-5
PCI commands 3-1                               Read/Write Instructions 6-14
PCI configuration registers 3-6­3-11           read-modify-write cycles 6-14
    Base Address One (Memory) 3-11             register addresses
    Base Address Zero (I/O) 3-11
    Cache Line Size 3-10                           operating registers
    Class Code 3-10                                     00h 5-5
    Command 3-7                                         01h 5-7
    Device ID 3-7
    Header Type 3-11
    Interrupt Line 3-11
    Interrupt Pin 3-11

I-6                                            SYM53C810A Data Manual
         02h 5-9                                                                                  Index
         03h 5-9
         04h 5-11                48h 5-42
         05h 5-11                49h 5-43
         06h 5-13                4Ah 5-43
         07h 5-14                4Ch 5-44
         08h 5-14                4Dh 5-45
         09h 5-15                4Eh 5-45
         0Ah 5-15                4Fh 5-46
         0Bh 5-16                50h 5-47
         0Ch 5-16                54h 5-48
         0Dh 5-17                58h 5-48
         0Eh 5-18                5Ch-5Fh 5-49
         0Fh 5-19           PCI configuration registers
         10h-13h 5-20            00h 3-7
         14h 5-20                02h 3-7
         18 5-22                 04h 3-7
         19h 5-23                06h 3-8
         1Ah 5-23                08h 3-10
         1Ch-1Fh 5-25            09h 3-10
         20h 5-26                0Ch 3-10
         21h 5-26                0Dh 3-10
         22h 5-27                0Eh 3-11
         23h 5-28                10h 3-11
         24h-26h 5-28            14h 3-11
         27h 5-29                3Ch 3-11
         28h-2Bh 5-29            3Dh 3-11
         2Ch-2Fh 5-30            3Eh 3-11
         30h-33h 5-30            3Fh 3-11
         34h-37h 5-31   register bits
         38h 5-31           53C700 compatibility 5-35
         39h 5-33           Abort operation 5-20
         3Ah 5-33           Aborted 5-17, 5-33
         3Bh 5-34           Arbitration in progress 5-18
         3Ch-3Fh 5-35       Arbitration mode 5-5
         40h 5-36           Arbitration Priority Encoder Test 5-44
         41h 5-37           Assert even SCSI parity 5-7
         42h 5-38           Assert SATN/ on parity error 5-6
         43h 5-40           Assert SCSI ACK 5-15
         44h 5-40           Assert SCSI ATN/ 5-15
         46h 5-41           Assert SCSI BSY/ 5-15
         47h 5-41
                                                                                                     I-7
SYM53C810A Data Manual
Index                                       Enable Read Line 5-32
                                            Enable Read Multiple 5-32, A-5
    Assert SCSI C_D/ 5-15                   Enable Response to Reselection 5-11
    Assert SCSI data bus 5-7                Enable Response to Selection 5-11
    Assert SCSI I_O/ 5-15                   Encoded Chip SCSI ID, bits 2-0 5-11
    Assert SCSI MSG/ 5-15                   Encoded destination ID 5-13
    Assert SCSI REQ/ signal 5-15            Encoded Destination SCSI ID 5-15
    Assert SCSI RST/ signal 5-7             Encoded NCR 53C810A Chip SCSI ID, bits
    Assert SCSI SEL/ 5-15                   2-0 5-11, A-2
    Burst Disable 5-26                      Extend SREQ/SACK filtering 5-46
    Burst length 5-31                       Extra clock cycle of data setup 5-7
    Burst Mode Fetch Enable 5-32            Fetch Enable 5-41
    Bus fault 5-33                          Fetch pin mode 5-24
    Byte Empty in DMA FIFO 5-23             FIFO byte control 5-27
    Byte full in DMA FIFO 5-23              FIFO flags 5-18
    Byte offset counter 5-26                Flush DMA FIFO 5-24
    Cache Line Size Enable 5-34, A-6        Function Complete 5-36, 5-38
    Chip revision level 5-24                General Purpose Timer Expired 5-37, 5-40
    Chip Type 5-41                          General Purpose Timer Period 5-43
    Clear DMA FIFO 5-24                     GPIO Enable 5-41
    Clear SCSI FIFO 5-47                    GPIO1-GPIO0 5-14, A-2
    Clock address incrementor 5-27          Halt SCSI Clock 5-46
    Clock byte counter 5-27                 Handshake to Handshake timer Expired 5-38
    Clock Conversion Factor 5-10            Handshake-to-Handshake Timer Expired 5-40
    Configured as I/O 5-23                  Handshake-to-Handshake Timer Period 5-42
    Configured as memory 5-23               High impedance mode 5-26
    Connected 5-7, 5-21                     Illegal instruction detected 5-17, 5-33
    DACK 5-24                               Immediate arbitration 5-8
    Data transfer direction 5-23            Interrupt on the Fly 5-21
    DataRD 5-41                             IRQ disable 5-34, A-6
    DataWR 5-41                             IRQ Mode 5-34
    Destination I/O-Memory Enable 5-32      Last Disconnect 5-19
    Disable Halt on Parity Error 5-7        Latched SCSI parity 5-18
    Disable Single Initiator Response 5-47  Lost arbitration 5-18
    DMA direction 5-27                      Manual Start Mode 5-32
    DMA FIFO 5-28                           Master control for set or reset pulses 5-27
    DMA FIFO empty bit 5-16                 Master Data Parity Error 5-16, 5-33
    DMA interrupt pending 5-22              Master Enable 5-41
    DREQ 5-24
    Enable parity checking 5-6                                                        SYM53C810A Data Manual

I-8
                                              Index

Master Parity Error Enable 5-27                   SCSI Selected As ID 5-44, A-7
Max SCSI Synchronous Offset 5-13                  SCSI Synchrnous Offset Zero 5-44
Parity Error 5-39                                 SCSI Synchronous Offset Maximum 5-44
Phase Mismatch or SATN/ Active 5-38               SCSI Synchronous Transfer Period 5-11
Pointer SCRIPTS 5-41                              SCSI true end of process 5-24
Pre-Fetch Enable 5-34, A-6                        SCSI Valid 5-15
Pre-Fetch Flush 5-34, A-6                         Select with SATN/ on a start sequence 5-6
Reselected 5-36, 5-39                             Selected 5-36, 5-39
Reset SCSI Offset 5-45                            Selection or Reselection Time-Out 5-37
SACK/ status 5-16                                 Selection or Reselection Time-out 5-40
SATN/ status 5-16                                 Selection response logic test 5-44
SBSY/ status 5-16                                 Selection Time-Out 5-42
SC_D/ status 5-16                                 Semaphore 5-21
SCLK 5-45                                         Shadow Register Test Mode 5-26
SCRIPTS 5-41                                      SI_O/ status 5-16
SCRIPTS interrupt instruction received 5-17,      SIDL full 5-17
5-33                                              Signal process 5-21, 5-23
SCSI C_D/ signal 5-19                             Single step interrupt 5-17, 5-33
SCSI Control Enable 5-45                          Single-step mode 5-34
SCSI Data High Impedance 5-26                     SMSG/ status 5-16
SCSI Disconnect Unexpected 5-9                    SODL full 5-17
SCSI FIFO Test Read 5-46                          SODR full 5-17
SCSI FIFO Test Write 5-47                         Software reset 5-20
SCSI Gross Error 5-36, 5-39                       Source I/O-Memory Enable 5-31
SCSI High-Impedance Mode 5-45                     SREQ/ status 5-16
SCSI I_O/ signal 5-19                             SSEL/ status 5-16
SCSI interrupt pending 5-22                       Start DMA operation 5-34
SCSI Isolation 5-45, A-7                          Start SCSI transfer 5-8
SCSI Loopback Mode 5-45                           Start sequence 5-5
SCSI Low level Mode 5-46                          Synchronous Clock Conversion Factor bits 5-9
SCSI MSG/ signal 5-19                             Target mode 5-6
SCSI Parity Error 5-37                            Unexpected Disconnect 5-36, 5-39
SCSI Phase Mismatch or SCSI ATN Condi-            WATN 5-6
tion 5-36                                         Won arbitration 5-18
SCSI Reset Condition 5-37                         Write and Invalidate Enable 5-25, A-4
SCSI RST/ Received 5-39                       Registers
SCSI RST/ signal 5-18                             see operating registers
SCSI SDP/ signal 5-18                         reliability 1-4

SYM53C810A Data Manual                        I-9
Index                               sample operation 6-2
                                SCRIPTS bit 5-41
REQ bit 5-15, 5-16              SCRIPTS instruction prefetching
reselect
                                    No Flush Memory Move instruction 6-23
    during reselection 2-9          Pre-fetch Enable bit 5-34, A-6
    response to 2-9                 Pre-Fetch Flush bit 5-34, A-6
Reselected bit 5-36, 5-39       SCRIPTS interrupt instruction received bit 5-17,
Reset SCSI Offset bit 5-45
RESPID0 register 5-43                    5-33
Response ID Zero register 5-43  SCRIPTS processor 2-1
revision level bits 5-24
ROF bit 5-45                        performance 2-1
RRE bit 5-11                    SCSI
RSL bit 5-36, 5-39
RST bit 5-7, 5-37, 5-39             pins 4-6
RST/ bit 5-18                       termination 2-9
S                               SCSI ATN Condition - Target Mode 5-36
SACK/ status bit 5-16           SCSI Bus Control Lines register 5-16
SATN/ active bit 5-38           SCSI Bus Data Lines register 5-48
SATN/ status bit 5-16           SCSI bus interface 2-9
SBCL register 5-16              SCSI C_D/ signal 5-19
SBDL register 5-48              SCSI Chip ID register 5-11
SBR register 5-33               SCSI clock rates 5-10
SBSY/ status bit 5-16           SCSI Control Enable bit 5-45
SC_D/ status bit 5-16           SCSI Control One register 5-7
SCE bit 5-45                    SCSI Control Three register 5-9
SCF2-0 bits 5-9                 SCSI Control Two register 5-9
SCID register 5-11              SCSI Control Zero register 5-5
SCLK bit 5-45                   SCSI core 2-1
SCNTL0 register 5-5             SCSI Data High Impedance bit 5-26
SCNTL1 register 5-7             SCSI Destination ID register 5-13
SCNTL2 register 5-9             SCSI Device Management System (SDMS) 2-2
SCNTL3 register 5-9             SCSI Disconnect Unexpected bit 5-9
SCPTS bit 5-41                  SCSI FIFO Test Read bit 5-46
Scratch Byte register 5-33      SCSI FIFO Test Write bit 5-47
SCRATCHA register 5-31          SCSI First Byte Received register 5-14
SCRATCHB register 5-49          SCSI Gross Error bit 5-36, 5-39
SCRIPTS                         SCSI High-Impedance Mode bit 5-45
                                SCSI I_O/ bit 5-19
I-10
                                                                                SYM53C810A Data Manual
                                               Index

SCSI Input Data Latch register 5-47            SCSI Test Three register 5-46
SCSI instructions                              SCSI Test Two register 5-45
                                               SCSI Test Zero register 5-44
    block move 6-4                             SCSI Timer One register 5-43
    I/O 6-8                                    SCSI Timer Zero register 5-42
    load/store 6-24                            SCSI timings 7-23­7-28
    memory move 6-21                           SCSI Transfer register 5-11
    read/write 6-14                            SCSI true end of process bit 5-24
SCSI Interrupt Enable One register 5-37        SCSI Valid Bit 5-15
SCSI Interrupt Enable Zero register 5-36       SDID register 5-13
SCSI interrupt pending bit 5-22                SDP/ bit 5-18
SCSI Interrupt Status One register 5-40        SDPL bit 5-18
SCSI Interrupt Status Zero register 5-38       SDU bit 5-9
SCSI Isolation bit 5-45, A-7                   SEL bit 5-15, 5-16, 5-36, 5-39
SCSI Longitudinal Parity register 5-40         SEL bits 5-42
SCSI Loopback Mode bit 5-45                    Select with SATN/ on a start sequence bit 5-6
SCSI Low level Mode 5-46                       Selected bit 5-36, 5-39
SCSI MSG/ bit 5-19                             selection
SCSI Output Control Latch register 5-15
SCSI Output Data Latch register 5-48               during reselection 2-9
SCSI Parity Error bit 5-37                         during selection 2-9
SCSI Phase Mismatch - Initiator Mode bit 5-36      response to 2-9
SCSI Reset Condition bit 5-37                  Selection or Reselection Time-out bit 5-37
SCSI RST/ Received bit 5-39                        STO bit 5-40
SCSI RST/ signal bit 5-18                      Selection response logic test bit 5-44
SCSI SCRIPTS operation 6-1                     Selection Time-Out bits 5-42
SCSI SDP0/ parity signal bit 5-18              SEM bit 5-21
SCSI Selected As ID bits 5-44, A-7             Semaphore bit 5-21
SCSI Selector ID register 5-15                 SFBR register 5-14
SCSI signals 7-2                               SGE bit 5-36, 5-39
SCSI Status One register 5-18                  Shadow Register Test Mode bit 5-26
SCSI Status Two register 5-19                  SI_O bit 5-16
SCSI Status Zero register 5-17                 SI_O/ status bit 5-16
SCSI Synchronous Offset Maximum bit 5-44       SIDL bit 5-17
SCSI Synchronous Offset Zero bit 5-44          SIDL least significant byte full bit 5-17
SCSI Synchronous Transfer Period bits 5-11     SIDL register 5-47
SCSI Test One register 5-45                    SIEN0 register 5-36

SYM53C810A Data Manual                                                                        I-11
Index                                      SSTAT2 register 5-19
                                           stacked interrupts 2-15
SIEN1 register 5-37                        START bit 5-5
Signal process bit 5-21, 5-23              Start DMA operation bit 5-34
SIGP bit 5-21, 5-23                        Start SCSI Transfer bit 5-8
Single step interrupt bit 5-17, 5-33       Start sequence bit 5-5
single-ended operation 2-9                 STD bit 5-34
Single-step mode bit 5-34                  STEST0 register 5-44
SIOM bit 5-31                              STEST1 register 5-45
SIP bit 5-22                               STEST2 register 5-45
SIR bit 5-17, 5-33                         STEST3 register 5-46
SISO bit 5-45, A-7                         STIME0 register 5-42
SIST0 register 5-38                        STIME1 register 5-43
SIST1 register 5-40                        STO bit 5-37
SLB bit 5-45                               STR bit 5-46
SLPAR register 5-40                        STW bit 5-47
SLT bit 5-44                               SXFER register 5-11
SMSG/ status bit 5-16                      SYM53C810A
SOCL register 5-15
SODL least significant byte full bit 5-17      ease of use 1-3
SODL register 5-48                             flexibility 1-4
SODR least significant byte full bit 5-17      integration 1-3
Software reset bit 5-20                        performance 1-3
SOM bit 5-44                                   reliability 1-4
Source I/O-Memory Enable bit 5-31              testability 1-4
SOZ bit 5-44                               SYMTolerANT Technology
SRE bit 5-11                                   electrical characteristics 7-6
SREQ/ status bit 5-16                      Synchronous Clock Conversion Factor bits 5-9
SRST bit 5-20                              synchronous data transfer rate 2-11
SRTM bit 5-26                              synchronous operation 2-11
SSAID bits 5-44, A-7                       system diagram 1-5
SSEL/ status bit 5-16                      System Pins 4-4
SSI bit 5-17, 5-33                         SZM bit 5-45
SSID register 5-15
SSM bit 5-34                               T
SST bit 5-8                                Target Mode
SSTAT0 register 5-17
SSTAT1 register 5-18                           SATN/ Active 5-38
                                           Target mode bit 5-6
I-12
                                                                                           SYM53C810A Data Manual
                                                  Index

TE bit 5-46                                       W
TEMP register 5-25                                WATN bit 5-6
Temporary register 5-25                           what is covered in this manual 1-1
TEOP bit 5-24                                     WOA bit 5-18
termination 2-9                                   Won arbitration bit 5-18
testability 1-4                                   Write and Invalidate command
Timer Test Mode bit 5-47
timing diagrams 7-11­7-27                             Write and Invalidate Enable bit 5-25, A-4

    interrupt output 7-10                         Z
    PCI interface 7-22                            ZMOD bit 5-26
    SCSI 7-28                                     ZSD bit 5-26
    SCSI timings 7-23
timings
    clock 7-9
    PCI 7-22
    reset input 7-10
    SCSI 7-23
TolerANT 1-2
    Extend SREQ/SACK filtering bit 5-46
    TolerANT Enable bit 5-46
TolerANT Enable bit 5-46
TP2-0 bits 5-11
transfer control instructions 6-17
    prefetch unit flushing 2-2
transfer rate 1-3
    Clock conversion factor bits 5-10
    synchronous 2-11
    Synchronous clock conversion factor bits 5-9
TRG bit 5-6
TTM bit 5-47
TYP3-0 bits 5-41

U
UDC bit 5-36, 5-39
Unexpected Disconnect bit 5-36, 5-39

V
VAL bit 5-15

SYM53C810A Data Manual                                                                           I-13
Index

I-14   SYM53C810A Data Manual
Symbios Logic
Sales Locations

For literature on any Symbios Logic product or
service, call our hotline toll-free 1-800-856-3093

North American Sales Locations                      International Sales Locations
Western Sales Area
                                                    European Sales Headquarters
  1731 Technology Drive, Suite 610                    Westendstrasse 193\III
  San Jose, CA 95110                                  80686 Muenchen
  (408) 441-1080                                      Germany
                                                      011-49-89-547470-0
  3300 Irvine Avenue, Suite 255
  Newport Beach, CA 92660                           Asia/Pacific Sales Headquarters
  (714) 474-7095                                      37th Floor, Room 3702, Lippo Tower
                                                      Lippo Centre, 89 Queensway
Eastern Sales Area                                    Hong Kong
  8000 Townline Avenue, Suite 209                     011-852-253-00727
  Bloomington, MN 55438-1000
  (612) 941-7075

12377 Merit Dr.
Dallas, TX 75251
(972) 503-3205

92 Montvale Avenue, Suite 3500
Stoneham, MA 02180-3623
(617) 438-0043

30 Mansell Court, Suite 220
Roswell, GA 30076
(404) 641-8001
© Symbios Logic Inc.
Printed in the U.S.A.
T07962I
0696-2MH
