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avr
wdt.h
Go to the documentation of this file.
1
/* Copyright (c) 2002, 2004 Marek Michalkiewicz
2
Copyright (c) 2005, 2006, 2007 Eric B. Weddington
3
All rights reserved.
4
5
Redistribution and use in source and binary forms, with or without
6
modification, are permitted provided that the following conditions are met:
7
8
* Redistributions of source code must retain the above copyright
9
notice, this list of conditions and the following disclaimer.
10
11
* Redistributions in binary form must reproduce the above copyright
12
notice, this list of conditions and the following disclaimer in
13
the documentation and/or other materials provided with the
14
distribution.
15
16
* Neither the name of the copyright holders nor the names of
17
contributors may be used to endorse or promote products derived
18
from this software without specific prior written permission.
19
20
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30
POSSIBILITY OF SUCH DAMAGE. */
31
32
/* $Id: wdt.h 2211 2011-02-14 14:04:25Z aboyapati $ */
33
34
/*
35
avr/wdt.h - macros for AVR watchdog timer
36
*/
37
38
#ifndef _AVR_WDT_H_
39
#define _AVR_WDT_H_
40
41
#include <
avr/io.h
>
42
#include <
stdint.h
>
43
44
/** \file */
45
/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
46
\code #include <avr/wdt.h> \endcode
47
48
This header file declares the interface to some inline macros
49
handling the watchdog timer present in many AVR devices. In order
50
to prevent the watchdog timer configuration from being
51
accidentally altered by a crashing application, a special timed
52
sequence is required in order to change it. The macros within
53
this header file handle the required sequence automatically
54
before changing any value. Interrupts will be disabled during
55
the manipulation.
56
57
\note Depending on the fuse configuration of the particular
58
device, further restrictions might apply, in particular it might
59
be disallowed to turn off the watchdog timer.
60
61
Note that for newer devices (ATmega88 and newer, effectively any
62
AVR that has the option to also generate interrupts), the watchdog
63
timer remains active even after a system reset (except a power-on
64
condition), using the fastest prescaler value (approximately 15
65
ms). It is therefore required to turn off the watchdog early
66
during program startup, the datasheet recommends a sequence like
67
the following:
68
69
\code
70
#include <stdint.h>
71
#include <avr/wdt.h>
72
73
uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
74
75
void get_mcusr(void) \
76
__attribute__((naked)) \
77
__attribute__((section(".init3")));
78
void get_mcusr(void)
79
{
80
mcusr_mirror = MCUSR;
81
MCUSR = 0;
82
wdt_disable();
83
}
84
\endcode
85
86
Saving the value of MCUSR in \c mcusr_mirror is only needed if the
87
application later wants to examine the reset source, but in particular,
88
clearing the watchdog reset flag before disabling the
89
watchdog is required, according to the datasheet.
90
*/
91
92
/**
93
\ingroup avr_watchdog
94
Reset the watchdog timer. When the watchdog timer is enabled,
95
a call to this instruction is required before the timer expires,
96
otherwise a watchdog-initiated device reset will occur.
97
*/
98
99
#define wdt_reset() __asm__ __volatile__ ("wdr")
100
101
102
#if defined(WDP3)
103
# define _WD_PS3_MASK _BV(WDP3)
104
#else
105
# define _WD_PS3_MASK 0x00
106
#endif
107
108
#if defined(WDTCSR)
109
# define _WD_CONTROL_REG WDTCSR
110
#elif defined(WDTCR)
111
# define _WD_CONTROL_REG WDTCR
112
#else
113
# define _WD_CONTROL_REG WDT
114
#endif
115
116
#if defined(WDTOE)
117
#define _WD_CHANGE_BIT WDTOE
118
#else
119
#define _WD_CHANGE_BIT WDCE
120
#endif
121
122
123
/**
124
\ingroup avr_watchdog
125
Enable the watchdog timer, configuring it for expiry after
126
\c timeout (which is a combination of the \c WDP0 through
127
\c WDP2 bits to write into the \c WDTCR register; For those devices
128
that have a \c WDTCSR register, it uses the combination of the \c WDP0
129
through \c WDP3 bits).
130
131
See also the symbolic constants \c WDTO_15MS et al.
132
*/
133
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#if defined(__AVR_ATMXT112SL__) \
136
|| defined(__AVR_ATMXT224__) \
137
|| defined(__AVR_ATMXT224E__) \
138
|| defined(__AVR_ATMXT336S__) \
139
|| defined(__AVR_ATMXT540S__) \
140
|| defined(__AVR_ATMXT540SREVA__) \
141
|| defined(__AVR_ATxmega16A4__) \
142
|| defined(__AVR_ATxmega16A4U__) \
143
|| defined(__AVR_ATxmega16C4__) \
144
|| defined(__AVR_ATxmega16D4__) \
145
|| defined(__AVR_ATxmega32A4__) \
146
|| defined(__AVR_ATxmega32A4U__) \
147
|| defined(__AVR_ATxmega32C4__) \
148
|| defined(__AVR_ATxmega32D4__) \
149
|| defined(__AVR_ATxmega32E5__) \
150
|| defined(__AVR_ATxmega64A1U__) \
151
|| defined(__AVR_ATxmega64A3__) \
152
|| defined(__AVR_ATxmega64A3U__) \
153
|| defined(__AVR_ATxmega64A4U__) \
154
|| defined(__AVR_ATxmega64B1__) \
155
|| defined(__AVR_ATxmega64B3__) \
156
|| defined(__AVR_ATxmega64C3__) \
157
|| defined(__AVR_ATxmega64D3__) \
158
|| defined(__AVR_ATxmega64D4__) \
159
|| defined(__AVR_ATxmega128A1__) \
160
|| defined(__AVR_ATxmega128A1U__) \
161
|| defined(__AVR_ATxmega128A3__) \
162
|| defined(__AVR_ATxmega128A3U__) \
163
|| defined(__AVR_ATxmega128A4U__) \
164
|| defined(__AVR_ATxmega128B1__) \
165
|| defined(__AVR_ATxmega128B3__) \
166
|| defined(__AVR_ATxmega128C3__) \
167
|| defined(__AVR_ATxmega128D3__) \
168
|| defined(__AVR_ATxmega128D4__) \
169
|| defined(__AVR_ATxmega192A3__) \
170
|| defined(__AVR_ATxmega192A3U__) \
171
|| defined(__AVR_ATxmega192C3__) \
172
|| defined(__AVR_ATxmega192D3__) \
173
|| defined(__AVR_ATxmega256A3__) \
174
|| defined(__AVR_ATxmega256A3U__) \
175
|| defined(__AVR_ATxmega256C3__) \
176
|| defined(__AVR_ATxmega256D3__) \
177
|| defined(__AVR_ATxmega256A3B__) \
178
|| defined(__AVR_ATxmega256A3BU__) \
179
|| defined(__AVR_ATxmega384C3__) \
180
|| defined(__AVR_ATxmega384D3__)
181
182
/*
183
wdt_enable(WDT_PER_8KCLK_gc);
184
*/
185
#define wdt_enable(value) \
186
__asm__ __volatile__ ( \
187
"in __tmp_reg__, %0" "\n\t" \
188
"out %1, %3" "\n\t" \
189
"sts %2, %4" "\n\t" \
190
"wdr" "\n\t" \
191
"out %0, __tmp_reg__" "\n\t" \
192
: \
193
: "M" (_SFR_MEM_ADDR(RAMPD)), \
194
"M" (_SFR_MEM_ADDR(CCP)), \
195
"M" (_SFR_MEM_ADDR(WDT_CTRL)), \
196
"r" ((uint8_t)0xD8), \
197
"r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \
198
: "r0" \
199
)
200
201
202
#elif defined(__AVR_AT90CAN32__) \
203
|| defined(__AVR_AT90CAN64__) \
204
|| defined(__AVR_AT90CAN128__) \
205
|| defined(__AVR_AT90PWM1__) \
206
|| defined(__AVR_AT90PWM2__) \
207
|| defined(__AVR_AT90PWM216__) \
208
|| defined(__AVR_AT90PWM2B__) \
209
|| defined(__AVR_AT90PWM3__) \
210
|| defined(__AVR_AT90PWM316__) \
211
|| defined(__AVR_AT90PWM3B__) \
212
|| defined(__AVR_AT90PWM161__) \
213
|| defined(__AVR_AT90PWM81__) \
214
|| defined(__AVR_AT90USB1286__) \
215
|| defined(__AVR_AT90USB1287__) \
216
|| defined(__AVR_AT90USB162__) \
217
|| defined(__AVR_AT90USB646__) \
218
|| defined(__AVR_AT90USB647__) \
219
|| defined(__AVR_AT90USB82__) \
220
|| defined(__AVR_ATmega128A__) \
221
|| defined(__AVR_ATmega1280__) \
222
|| defined(__AVR_ATmega1281__) \
223
|| defined(__AVR_ATmega1284__) \
224
|| defined(__AVR_ATmega1284P__) \
225
|| defined(__AVR_ATmega128RFA1__) \
226
|| defined(__AVR_ATmega128RFA2__) \
227
|| defined(__AVR_ATmega128RFR2__) \
228
|| defined(__AVR_ATmega164__) \
229
|| defined(__AVR_ATmega164A__) \
230
|| defined(__AVR_ATmega164P__) \
231
|| defined(__AVR_ATmega164PA__) \
232
|| defined(__AVR_ATmega165__) \
233
|| defined(__AVR_ATmega165A__) \
234
|| defined(__AVR_ATmega165P__) \
235
|| defined(__AVR_ATmega165PA__) \
236
|| defined(__AVR_ATmega168__) \
237
|| defined(__AVR_ATmega168A__) \
238
|| defined(__AVR_ATmega168P__) \
239
|| defined(__AVR_ATmega168PA__) \
240
|| defined(__AVR_ATmega169__) \
241
|| defined(__AVR_ATmega169A__) \
242
|| defined(__AVR_ATmega169P__) \
243
|| defined(__AVR_ATmega169PA__) \
244
|| defined(__AVR_ATmega16HVA__) \
245
|| defined(__AVR_ATmega16HVA2__) \
246
|| defined(__AVR_ATmega16HVB__) \
247
|| defined(__AVR_ATmega16HVBREVB__) \
248
|| defined(__AVR_ATmega16M1__) \
249
|| defined(__AVR_ATmega16U2__) \
250
|| defined(__AVR_ATmega16U4__) \
251
|| defined(__AVR_ATmega2560__) \
252
|| defined(__AVR_ATmega2561__) \
253
|| defined(__AVR_ATmega256RFA2__) \
254
|| defined(__AVR_ATmega256RFR2__) \
255
|| defined(__AVR_ATmega26HVG__) \
256
|| defined(__AVR_ATmega32A__) \
257
|| defined(__AVR_ATmega324__) \
258
|| defined(__AVR_ATmega324A__) \
259
|| defined(__AVR_ATmega324P__) \
260
|| defined(__AVR_ATmega324PA__) \
261
|| defined(__AVR_ATmega325__) \
262
|| defined(__AVR_ATmega325A__) \
263
|| defined(__AVR_ATmega325P__) \
264
|| defined(__AVR_ATmega325PA__) \
265
|| defined(__AVR_ATmega3250__) \
266
|| defined(__AVR_ATmega3250A__) \
267
|| defined(__AVR_ATmega3250P__) \
268
|| defined(__AVR_ATmega3250PA__) \
269
|| defined(__AVR_ATmega328__) \
270
|| defined(__AVR_ATmega328P__) \
271
|| defined(__AVR_ATmega329__) \
272
|| defined(__AVR_ATmega329A__) \
273
|| defined(__AVR_ATmega329P__) \
274
|| defined(__AVR_ATmega329PA__) \
275
|| defined(__AVR_ATmega3290__) \
276
|| defined(__AVR_ATmega3290A__) \
277
|| defined(__AVR_ATmega3290P__) \
278
|| defined(__AVR_ATmega3290PA__) \
279
|| defined(__AVR_ATmega32C1__) \
280
|| defined(__AVR_ATmega32HVB__) \
281
|| defined(__AVR_ATmega32HVBREVB__) \
282
|| defined(__AVR_ATmega32M1__) \
283
|| defined(__AVR_ATmega32U2__) \
284
|| defined(__AVR_ATmega32U4__) \
285
|| defined(__AVR_ATmega32U6__) \
286
|| defined(__AVR_ATmega406__) \
287
|| defined(__AVR_ATmega48HVF__) \
288
|| defined(__AVR_ATmega48__) \
289
|| defined(__AVR_ATmega48A__) \
290
|| defined(__AVR_ATmega48PA__) \
291
|| defined(__AVR_ATmega48P__) \
292
|| defined(__AVR_ATmega64A__) \
293
|| defined(__AVR_ATmega64RFA2__) \
294
|| defined(__AVR_ATmega64RFR2__) \
295
|| defined(__AVR_ATmega640__) \
296
|| defined(__AVR_ATmega644__) \
297
|| defined(__AVR_ATmega644A__) \
298
|| defined(__AVR_ATmega644P__) \
299
|| defined(__AVR_ATmega644PA__) \
300
|| defined(__AVR_ATmega645__) \
301
|| defined(__AVR_ATmega645A__) \
302
|| defined(__AVR_ATmega645P__) \
303
|| defined(__AVR_ATmega6450__) \
304
|| defined(__AVR_ATmega6450A__) \
305
|| defined(__AVR_ATmega6450P__) \
306
|| defined(__AVR_ATmega649__) \
307
|| defined(__AVR_ATmega649A__) \
308
|| defined(__AVR_ATmega6490__) \
309
|| defined(__AVR_ATmega6490A__) \
310
|| defined(__AVR_ATmega6490P__) \
311
|| defined(__AVR_ATmega649P__) \
312
|| defined(__AVR_ATmega64C1__) \
313
|| defined(__AVR_ATmega64HVE__) \
314
|| defined(__AVR_ATmega64M1__) \
315
|| defined(__AVR_ATmega8A__) \
316
|| defined(__AVR_ATmega88__) \
317
|| defined(__AVR_ATmega88A__) \
318
|| defined(__AVR_ATmega88P__) \
319
|| defined(__AVR_ATmega88PA__) \
320
|| defined(__AVR_ATmega8HVA__) \
321
|| defined(__AVR_ATmega8U2__) \
322
|| defined(__AVR_ATtiny48__) \
323
|| defined(__AVR_ATtiny88__) \
324
|| defined(__AVR_ATtiny87__) \
325
|| defined(__AVR_ATtiny167__) \
326
|| defined(__AVR_AT90SCR100__) \
327
|| defined(__AVR_ATA6285__) \
328
|| defined(__AVR_ATA6286__) \
329
|| defined(__AVR_ATA6289__) \
330
|| defined(__AVR_ATA5272__) \
331
|| defined(__AVR_ATA5505__) \
332
|| defined(__AVR_ATA5790__) \
333
|| defined(__AVR_ATA5790N__) \
334
|| defined(__AVR_ATA5795__) \
335
|| defined(__AVR_ATA5831__)
336
337
/* Use STS instruction. */
338
339
#define wdt_enable(value) \
340
__asm__ __volatile__ ( \
341
"in __tmp_reg__,__SREG__" "\n\t" \
342
"cli" "\n\t" \
343
"wdr" "\n\t" \
344
"sts %0,%1" "\n\t" \
345
"out __SREG__,__tmp_reg__" "\n\t" \
346
"sts %0,%2" "\n\t" \
347
:
/* no outputs */
\
348
: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
349
"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
350
"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
351
_BV(WDE) | (value & 0x07)) ) \
352
: "r0" \
353
)
354
355
#define wdt_disable() \
356
__asm__ __volatile__ ( \
357
"in __tmp_reg__, __SREG__" "\n\t" \
358
"cli" "\n\t" \
359
"sts %0, %1" "\n\t" \
360
"sts %0, __zero_reg__" "\n\t" \
361
"out __SREG__,__tmp_reg__" "\n\t" \
362
:
/* no outputs */
\
363
: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
364
"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
365
: "r0" \
366
)
367
368
369
#elif defined(__AVR_ATtiny841__)
370
371
/* Use STS instruction. */
372
373
#define wdt_enable(value) \
374
__asm__ __volatile__ ( \
375
"in __tmp_reg__,__SREG__" "\n\t" \
376
"cli" "\n\t" \
377
"wdr" "\n\t" \
378
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
379
"out %[WDTREG],%[WDVALUE]" "\n\t" \
380
"out __SREG__,__tmp_reg__" "\n\t" \
381
:
/* no outputs */
\
382
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
383
[SIGNATURE] "r" ((uint8_t)0xD8), \
384
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
385
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
386
| _BV(WDE) | (value & 0x07) )) \
387
: "r0" \
388
)
389
390
#define wdt_disable() \
391
do { \
392
uint8_t temp_wd; \
393
__asm__ __volatile__ ( \
394
"in __tmp_reg__,__SREG__" "\n\t" \
395
"cli" "\n\t" \
396
"wdr" "\n\t" \
397
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
398
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
399
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
400
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
401
"out __SREG__,__tmp_reg__" "\n\t" \
402
:
/*no output */
\
403
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
404
[SIGNATURE] "r" ((uint8_t)0xD8), \
405
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
406
[TEMP_WD] "d" (temp_wd), \
407
[WDVALUE] "I" (1 << WDE) \
408
: "r0" \
409
); \
410
}while(0)
411
412
#elif defined(__AVR_ATtiny1634__) \
413
|| defined(__AVR_ATtiny828__)
414
415
#define wdt_enable(value) \
416
__asm__ __volatile__ ( \
417
"in __tmp_reg__,__SREG__" "\n\t" \
418
"cli" "\n\t" \
419
"wdr" "\n\t" \
420
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
421
"sts %[WDTREG],%[WDVALUE]" "\n\t" \
422
"out __SREG__,__tmp_reg__" "\n\t" \
423
:
/* no outputs */
\
424
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
425
[SIGNATURE] "r" ((uint8_t)0xD8), \
426
[WDTREG] "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
427
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
428
| _BV(WDE) | value)) \
429
: "r0" \
430
)
431
432
#define wdt_disable() \
433
do { \
434
uint8_t temp_wd; \
435
__asm__ __volatile__ ( \
436
"in __tmp_reg__,__SREG__" "\n\t" \
437
"cli" "\n\t" \
438
"wdr" "\n\t" \
439
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
440
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
441
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
442
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
443
"out __SREG__,__tmp_reg__" "\n\t" \
444
:
/*no output */
\
445
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
446
[SIGNATURE] "r" ((uint8_t)0xD8), \
447
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
448
[TEMP_WD] "d" (temp_wd), \
449
[WDVALUE] "I" (1 << WDE) \
450
: "r0" \
451
); \
452
}while(0)
453
454
#elif defined(__AVR_ATtiny4__) \
455
|| defined(__AVR_ATtiny5__) \
456
|| defined(__AVR_ATtiny9__) \
457
|| defined(__AVR_ATtiny10__) \
458
|| defined(__AVR_ATtiny20__) \
459
|| defined(__AVR_ATtiny40__)
460
461
#define wdt_enable(value) \
462
__asm__ __volatile__ ( \
463
"in __tmp_reg__,__SREG__" "\n\t" \
464
"cli" "\n\t" \
465
"wdr" "\n\t" \
466
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
467
"out %[WDTREG],%[WDVALUE]" "\n\t" \
468
"out __SREG__,__tmp_reg__" "\n\t" \
469
:
/* no outputs */
\
470
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
471
[SIGNATURE] "r" ((uint8_t)0xD8), \
472
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
473
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
474
| _BV(WDE) | value)) \
475
: "r16" \
476
)
477
478
#define wdt_disable() \
479
do { \
480
uint8_t temp_wd; \
481
__asm__ __volatile__ ( \
482
"in __tmp_reg__,__SREG__" "\n\t" \
483
"cli" "\n\t" \
484
"wdr" "\n\t" \
485
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
486
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
487
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
488
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
489
"out __SREG__,__tmp_reg__" "\n\t" \
490
:
/*no output */
\
491
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
492
[SIGNATURE] "r" ((uint8_t)0xD8), \
493
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
494
[TEMP_WD] "d" (temp_wd), \
495
[WDVALUE] "I" (1 << WDE) \
496
: "r16" \
497
); \
498
}while(0)
499
500
#elif defined(__AVR_ATxmega32X1__) \
501
||defined(__AVR_ATxmega64A1__)
502
503
#define wdt_enable(value) \
504
__asm__ __volatile__ ( \
505
"in __tmp_reg__,__SREG__" "\n\t" \
506
"cli" "\n\t" \
507
"wdr" "\n\t" \
508
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
509
"sts %[WDTREG],%[WDVALUE]" "\n\t" \
510
"out __SREG__,__tmp_reg__" "\n\t" \
511
:
/* no outputs */
\
512
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
513
[SIGNATURE] "r" ((uint8_t)0xD8), \
514
[WDTREG] "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
515
[WDVALUE] "r" ((uint8_t)((_BV(WDT_ENABLE_bp)) | (_BV(WDT_CEN_bp)) | \
516
(value << WDT_PER_gp))) \
517
: "r0" \
518
)
519
520
#define wdt_disable() \
521
__asm__ __volatile__ ( \
522
"in __tmp_reg__,__SREG__" "\n\t" \
523
"cli" "\n\t" \
524
"wdr" "\n\t" \
525
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
526
"sts %[WDTREG],%[WDVALUE]" "\n\t" \
527
"out __SREG__,__tmp_reg__" "\n\t" \
528
:
/* no outputs */
\
529
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
530
[SIGNATURE] "r" ((uint8_t)0xD8), \
531
[WDTREG] "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
532
[WDVALUE] "r" ((uint8_t)((_BV(WDT_CEN_bp)))) \
533
: "r0" \
534
)
535
536
/**
537
Undefining explicitly so that it produces an error.
538
*/
539
#elif defined(__AVR_AT90C8534__) \
540
|| defined(__AVR_M3000__)
541
#undef wdt_enable
542
#undef wdt_disale
543
544
#else
545
546
/* Use OUT instruction. */
547
548
#define wdt_enable(value) \
549
__asm__ __volatile__ ( \
550
"in __tmp_reg__,__SREG__" "\n\t" \
551
"cli" "\n\t" \
552
"wdr" "\n\t" \
553
"out %0,%1" "\n\t" \
554
"out __SREG__,__tmp_reg__" "\n\t" \
555
"out %0,%2" \
556
:
/* no outputs */
\
557
: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
558
"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
559
"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
560
_BV(WDE) | (value & 0x07)) ) \
561
: "r0" \
562
)
563
564
/**
565
\ingroup avr_watchdog
566
Disable the watchdog timer, if possible. This attempts to turn off the
567
Enable bit in the watchdog control register. See the datasheet for
568
details.
569
*/
570
#define wdt_disable() \
571
__asm__ __volatile__ ( \
572
"in __tmp_reg__, __SREG__" "\n\t" \
573
"cli" "\n\t" \
574
"out %0, %1" "\n\t" \
575
"out %0, __zero_reg__" "\n\t" \
576
"out __SREG__,__tmp_reg__" "\n\t" \
577
:
/* no outputs */
\
578
: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
579
"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
580
: "r0" \
581
)
582
583
#endif
584
585
586
587
/**
588
\ingroup avr_watchdog
589
Symbolic constants for the watchdog timeout. Since the watchdog
590
timer is based on a free-running RC oscillator, the times are
591
approximate only and apply to a supply voltage of 5 V. At lower
592
supply voltages, the times will increase. For older devices, the
593
times will be as large as three times when operating at Vcc = 3 V,
594
while the newer devices (e. g. ATmega128, ATmega8) only experience
595
a negligible change.
596
597
Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
598
500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
599
Symbolic constants are formed by the prefix
600
\c WDTO_, followed by the time.
601
602
Example that would select a watchdog timer expiry of approximately
603
500 ms:
604
\code
605
wdt_enable(WDTO_500MS);
606
\endcode
607
*/
608
#define WDTO_15MS 0
609
610
/** \ingroup avr_watchdog
611
See \c WDT0_15MS */
612
#define WDTO_30MS 1
613
614
/** \ingroup avr_watchdog See
615
\c WDT0_15MS */
616
#define WDTO_60MS 2
617
618
/** \ingroup avr_watchdog
619
See \c WDT0_15MS */
620
#define WDTO_120MS 3
621
622
/** \ingroup avr_watchdog
623
See \c WDT0_15MS */
624
#define WDTO_250MS 4
625
626
/** \ingroup avr_watchdog
627
See \c WDT0_15MS */
628
#define WDTO_500MS 5
629
630
/** \ingroup avr_watchdog
631
See \c WDT0_15MS */
632
#define WDTO_1S 6
633
634
/** \ingroup avr_watchdog
635
See \c WDT0_15MS */
636
#define WDTO_2S 7
637
638
#if defined(__DOXYGEN__) || defined(WDP3)
639
640
/** \ingroup avr_watchdog
641
See \c WDT0_15MS
642
Note: This is only available on the
643
ATtiny2313,
644
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
645
ATtiny25, ATtiny45, ATtiny85,
646
ATtiny261, ATtiny461, ATtiny861,
647
ATmega48, ATmega88, ATmega168,
648
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
649
ATmega164P, ATmega324P, ATmega644P, ATmega644,
650
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
651
ATmega8HVA, ATmega16HVA, ATmega26HVG, ATmega32HVB,
652
ATmega406, ATmega48HVF, ATmega1284P,
653
ATmega256RFA2, ATmega256RFR2, ATmega128RFA2, ATmega128RFR2, ATmega64RFA2, ATmega64RFR2,
654
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
655
AT90PWM81, AT90PWM161,
656
AT90USB82, AT90USB162,
657
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
658
ATtiny48, ATtiny88.
659
*/
660
#define WDTO_4S 8
661
662
/** \ingroup avr_watchdog
663
See \c WDT0_15MS
664
Note: This is only available on the
665
ATtiny2313,
666
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
667
ATtiny25, ATtiny45, ATtiny85,
668
ATtiny261, ATtiny461, ATtiny861,
669
ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
670
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
671
ATmega164P, ATmega324P, ATmega644P, ATmega644,
672
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
673
ATmega8HVA, ATmega16HVA, ATmega26HVG, ATmega32HVB,
674
ATmega406, ATmega48HVF, ATmega1284P,
675
ATmega256RFA2, ATmega256RFR2, ATmega128RFA2, ATmega128RFR2, ATmega64RFA2, ATmega64RFR2,
676
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
677
AT90PWM81, AT90PWM161,
678
AT90USB82, AT90USB162,
679
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
680
ATtiny48, ATtiny88,
681
ATxmega16a4u, ATxmega32a4u,
682
ATxmega16c4, ATxmega32c4,
683
ATxmega128c3, ATxmega192c3, ATxmega256c3.
684
*/
685
#define WDTO_8S 9
686
687
#endif
/* defined(__DOXYGEN__) || defined(WDP3) */
688
689
690
#endif
/* _AVR_WDT_H_ */
Automatically generated by Doxygen 1.8.1.1 on Fri Aug 17 2012.