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sleep.h
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1 /* Copyright (c) 2002, 2004 Theodore A. Roth
2  Copyright (c) 2004, 2007, 2008 Eric B. Weddington
3  Copyright (c) 2005, 2006, 2007 Joerg Wunsch
4  All rights reserved.
5 
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8 
9  * Redistributions of source code must retain the above copyright
10  notice, this list of conditions and the following disclaimer.
11 
12  * Redistributions in binary form must reproduce the above copyright
13  notice, this list of conditions and the following disclaimer in
14  the documentation and/or other materials provided with the
15  distribution.
16 
17  * Neither the name of the copyright holders nor the names of
18  contributors may be used to endorse or promote products derived
19  from this software without specific prior written permission.
20 
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE. */
32 
33 /* $Id: sleep.h 2238 2011-05-09 16:44:33Z arcanum $ */
34 
35 #ifndef _AVR_SLEEP_H_
36 #define _AVR_SLEEP_H_ 1
37 
38 #include <avr/io.h>
39 #include <stdint.h>
40 
41 
42 /** \file */
43 
44 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
45 
46  \code #include <avr/sleep.h>\endcode
47 
48  Use of the \c SLEEP instruction can allow an application to reduce its
49  power comsumption considerably. AVR devices can be put into different
50  sleep modes. Refer to the datasheet for the details relating to the device
51  you are using.
52 
53  There are several macros provided in this header file to actually
54  put the device into sleep mode. The simplest way is to optionally
55  set the desired sleep mode using \c set_sleep_mode() (it usually
56  defaults to idle mode where the CPU is put on sleep but all
57  peripheral clocks are still running), and then call
58  \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
59  to sleep, and clears the sleep enable bit.
60 
61  Example:
62  \code
63  #include <avr/sleep.h>
64 
65  ...
66  set_sleep_mode(<mode>);
67  sleep_mode();
68  \endcode
69 
70  Note that unless your purpose is to completely lock the CPU (until a
71  hardware reset), interrupts need to be enabled before going to sleep.
72 
73  As the \c sleep_mode() macro might cause race conditions in some
74  situations, the individual steps of manipulating the sleep enable
75  (SE) bit, and actually issuing the \c SLEEP instruction, are provided
76  in the macros \c sleep_enable(), \c sleep_disable(), and
77  \c sleep_cpu(). This also allows for test-and-sleep scenarios that
78  take care of not missing the interrupt that will awake the device
79  from sleep.
80 
81  Example:
82  \code
83  #include <avr/interrupt.h>
84  #include <avr/sleep.h>
85 
86  ...
87  set_sleep_mode(<mode>);
88  cli();
89  if (some_condition)
90  {
91  sleep_enable();
92  sei();
93  sleep_cpu();
94  sleep_disable();
95  }
96  sei();
97  \endcode
98 
99  This sequence ensures an atomic test of \c some_condition with
100  interrupts being disabled. If the condition is met, sleep mode
101  will be prepared, and the \c SLEEP instruction will be scheduled
102  immediately after an \c SEI instruction. As the intruction right
103  after the \c SEI is guaranteed to be executed before an interrupt
104  could trigger, it is sure the device will really be put to sleep.
105 
106  Some devices have the ability to disable the Brown Out Detector (BOD) before
107  going to sleep. This will also reduce power while sleeping. If the
108  specific AVR device has this ability then an additional macro is defined:
109  \c sleep_bod_disable(). This macro generates inlined assembly code
110  that will correctly implement the timed sequence for disabling the BOD
111  before sleeping. However, there is a limited number of cycles after the
112  BOD has been disabled that the device can be put into sleep mode, otherwise
113  the BOD will not truly be disabled. Recommended practice is to disable
114  the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
115  put the device to sleep (\c sleep_cpu()), like so:
116 
117  \code
118  #include <avr/interrupt.h>
119  #include <avr/sleep.h>
120 
121  ...
122  set_sleep_mode(<mode>);
123  cli();
124  if (some_condition)
125  {
126  sleep_enable();
127  sleep_bod_disable();
128  sei();
129  sleep_cpu();
130  sleep_disable();
131  }
132  sei();
133  \endcode
134 */
135 
136 
137 /* Define an internal sleep control register and an internal sleep enable bit mask. */
138 #if defined(SLEEP_CTRL)
139 
140  /* XMEGA devices */
141  #define _SLEEP_CONTROL_REG SLEEP_CTRL
142  #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
143 
144 #elif defined(SMCR)
145 
146  #define _SLEEP_CONTROL_REG SMCR
147  #define _SLEEP_ENABLE_MASK _BV(SE)
148 
149 #elif defined(__AVR_AT94K__)
150 
151  #define _SLEEP_CONTROL_REG MCUR
152  #define _SLEEP_ENABLE_MASK _BV(SE)
153 
154 #else
155 
156  #define _SLEEP_CONTROL_REG MCUCR
157  #define _SLEEP_ENABLE_MASK _BV(SE)
158 
159 #endif
160 
161 
162 /* Define set_sleep_mode() and sleep mode values per device. */
163 #if defined(__AVR_ATmega161__)
164 
165  #define SLEEP_MODE_IDLE 0
166  #define SLEEP_MODE_PWR_DOWN 1
167  #define SLEEP_MODE_PWR_SAVE 2
168 
169  #define set_sleep_mode(mode) \
170  do { \
171  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
172  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
173  } while(0)
174 
175 
176 #elif defined(__AVR_ATmega162__) \
177 || defined(__AVR_ATmega8515__)
178 
179  #define SLEEP_MODE_IDLE 0
180  #define SLEEP_MODE_PWR_DOWN 1
181  #define SLEEP_MODE_PWR_SAVE 2
182  #define SLEEP_MODE_ADC 3
183  #define SLEEP_MODE_STANDBY 4
184  #define SLEEP_MODE_EXT_STANDBY 5
185 
186  #define set_sleep_mode(mode) \
187  do { \
188  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
189  MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
190  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
191  } while(0)
192 
193 #elif defined(__AVR_AT90S2313__) \
194 || defined(__AVR_AT90S2323__) \
195 || defined(__AVR_AT90S2333__) \
196 || defined(__AVR_AT90S2343__) \
197 || defined(__AVR_AT43USB320__) \
198 || defined(__AVR_AT43USB355__) \
199 || defined(__AVR_AT90S4414__) \
200 || defined(__AVR_AT90S4433__) \
201 || defined(__AVR_AT90S8515__) \
202 || defined(__AVR_ATtiny22__)
203 
204  #define SLEEP_MODE_IDLE 0
205  #define SLEEP_MODE_PWR_DOWN _BV(SM)
206 
207  #define set_sleep_mode(mode) \
208  do { \
209  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \
210  } while(0)
211 
212 #elif defined(__AVR_ATtiny167__) \
213 || defined(__AVR_ATtiny87__) \
214 || defined(__AVR_ATtiny828__) \
215 || defined(__AVR_ATtiny841__)
216 
217  #define SLEEP_MODE_IDLE 0
218  #define SLEEP_MODE_ADC _BV(SM0)
219  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
220 
221  #define set_sleep_mode(mode) \
222  do { \
223  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
224  } while(0)
225 
226 #elif defined(__AVR_AT90S4434__) \
227 || defined(__AVR_ATA5505__) \
228 || defined(__AVR_ATA5272__) \
229 || defined(__AVR_AT76C711__) \
230 || defined(__AVR_AT90S8535__) \
231 || defined(__AVR_ATmega103__) \
232 || defined(__AVR_ATmega161__) \
233 || defined(__AVR_ATmega163__) \
234 || defined(__AVR_ATmega16HVB__) \
235 || defined(__AVR_ATmega16HVBREVB__) \
236 || defined(__AVR_ATmega32HVB__) \
237 || defined(__AVR_ATmega32HVBREVB__) \
238 || defined(__AVR_ATtiny13__) \
239 || defined(__AVR_ATtiny13A__) \
240 || defined(__AVR_ATtiny15__) \
241 || defined(__AVR_ATtiny24__) \
242 || defined(__AVR_ATtiny24A__) \
243 || defined(__AVR_ATtiny44__) \
244 || defined(__AVR_ATtiny44A__) \
245 || defined(__AVR_ATtiny84__) \
246 || defined(__AVR_ATtiny84A__) \
247 || defined(__AVR_ATtiny25__) \
248 || defined(__AVR_ATtiny45__) \
249 || defined(__AVR_ATtiny48__) \
250 || defined(__AVR_ATtiny85__) \
251 || defined(__AVR_ATtiny88__)
252 
253  #define SLEEP_MODE_IDLE 0
254  #define SLEEP_MODE_ADC _BV(SM0)
255  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
256  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
257 
258  #define set_sleep_mode(mode) \
259  do { \
260  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
261  } while(0)
262 
263 #elif defined(__AVR_ATmega48HVF__) \
264 || defined(__AVR_ATmega26HVG__)
265 
266  #define SLEEP_MODE_IDLE (0)
267  #define SLEEP_MODE_ADC _BV(SM0)
268  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
269  #define SLEEP_MODE_PWR_OFF _BV(SM2)
270 
271 
272  #define set_sleep_mode(mode) \
273  do { \
274  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
275  } while(0)
276 
277 #elif defined(__AVR_ATtiny2313__) \
278 || defined(__AVR_ATtiny2313A__) \
279 || defined(__AVR_ATtiny4313__)
280 
281  #define SLEEP_MODE_IDLE 0
282  #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
283  #define SLEEP_MODE_STANDBY _BV(SM1)
284 
285  #define set_sleep_mode(mode) \
286  do { \
287  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
288  } while(0)
289 
290 #elif defined(__AVR_AT94K__)
291 
292  #define SLEEP_MODE_IDLE 0
293  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
294  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
295 
296  #define set_sleep_mode(mode) \
297  do { \
298  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
299  } while(0)
300 
301 #elif defined(__AVR_ATtiny26__) \
302 || defined(__AVR_ATtiny261__) \
303 || defined(__AVR_ATtiny261A__) \
304 || defined(__AVR_ATtiny461__) \
305 || defined(__AVR_ATtiny461A__) \
306 || defined(__AVR_ATtiny861__) \
307 || defined(__AVR_ATtiny861A__) \
308 || defined(__AVR_ATtiny43U__) \
309 || defined(__AVR_ATtiny1634__)
310 
311  #define SLEEP_MODE_IDLE 0
312  #define SLEEP_MODE_ADC _BV(SM0)
313  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
314  #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
315 
316  #define set_sleep_mode(mode) \
317  do { \
318  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
319  } while(0)
320 
321 #elif defined(__AVR_AT90PWM216__) \
322 || defined(__AVR_AT90PWM316__) \
323 || defined(__AVR_AT90PWM161__) \
324 || defined(__AVR_AT90PWM81__)
325 
326  #define SLEEP_MODE_IDLE 0
327  #define SLEEP_MODE_ADC _BV(SM0)
328  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
329  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
330 
331  #define set_sleep_mode(mode) \
332  do { \
333  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
334  } while(0)
335 
336 #elif defined(__AVR_AT90CAN128__) \
337 || defined(__AVR_AT90CAN32__) \
338 || defined(__AVR_AT90CAN64__) \
339 || defined(__AVR_AT90PWM1__) \
340 || defined(__AVR_AT90PWM2__) \
341 || defined(__AVR_AT90PWM2B__) \
342 || defined(__AVR_AT90PWM3__) \
343 || defined(__AVR_AT90PWM3B__) \
344 || defined(__AVR_AT90USB162__) \
345 || defined(__AVR_AT90USB82__) \
346 || defined(__AVR_AT90USB1286__) \
347 || defined(__AVR_AT90USB1287__) \
348 || defined(__AVR_AT90USB646__) \
349 || defined(__AVR_AT90USB647__) \
350 || defined(__AVR_ATmega128__) \
351 || defined(__AVR_ATmega128A__) \
352 || defined(__AVR_ATmega1280__) \
353 || defined(__AVR_ATmega1281__) \
354 || defined(__AVR_ATmega1284__) \
355 || defined(__AVR_ATmega1284P__) \
356 || defined(__AVR_ATmega128RFA1__) \
357 || defined(__AVR_ATmega128RFA2__) \
358 || defined(__AVR_ATmega128RFR2__) \
359 || defined(__AVR_ATmega16__) \
360 || defined(__AVR_ATmega16A__) \
361 || defined(__AVR_ATmega162__) \
362 || defined(__AVR_ATmega164A__) \
363 || defined(__AVR_ATmega164P__) \
364 || defined(__AVR_ATmega164PA__) \
365 || defined(__AVR_ATmega165__) \
366 || defined(__AVR_ATmega165A__) \
367 || defined(__AVR_ATmega165P__) \
368 || defined(__AVR_ATmega165PA__) \
369 || defined(__AVR_ATmega168__) \
370 || defined(__AVR_ATmega168A__) \
371 || defined(__AVR_ATmega168P__) \
372 || defined(__AVR_ATmega168PA__) \
373 || defined(__AVR_ATmega169__) \
374 || defined(__AVR_ATmega169A__) \
375 || defined(__AVR_ATmega169P__) \
376 || defined(__AVR_ATmega169PA__) \
377 || defined(__AVR_ATmega16HVA__) \
378 || defined(__AVR_ATmega16HVA2__) \
379 || defined(__AVR_ATmega16M1__) \
380 || defined(__AVR_ATmega16U2__) \
381 || defined(__AVR_ATmega16U4__) \
382 || defined(__AVR_ATmega2560__) \
383 || defined(__AVR_ATmega2561__) \
384 || defined(__AVR_ATmega256RFA2__) \
385 || defined(__AVR_ATmega256RFR2__) \
386 || defined(__AVR_ATmega32__) \
387 || defined(__AVR_ATmega32A__) \
388 || defined(__AVR_ATmega323__) \
389 || defined(__AVR_ATmega324A__) \
390 || defined(__AVR_ATmega324P__) \
391 || defined(__AVR_ATmega324PA__) \
392 || defined(__AVR_ATmega325__) \
393 || defined(__AVR_ATmega325A__) \
394 || defined(__AVR_ATmega325P__) \
395 || defined(__AVR_ATmega325PA__) \
396 || defined(__AVR_ATmega3250__) \
397 || defined(__AVR_ATmega3250A__) \
398 || defined(__AVR_ATmega3250P__) \
399 || defined(__AVR_ATmega3250PA__) \
400 || defined(__AVR_ATmega328__) \
401 || defined(__AVR_ATmega328P__) \
402 || defined(__AVR_ATmega329__) \
403 || defined(__AVR_ATmega329A__) \
404 || defined(__AVR_ATmega329P__) \
405 || defined(__AVR_ATmega329PA__) \
406 || defined(__AVR_ATmega3290__) \
407 || defined(__AVR_ATmega3290A__) \
408 || defined(__AVR_ATmega3290P__) \
409 || defined(__AVR_ATmega3290PA__) \
410 || defined(__AVR_ATmega32C1__) \
411 || defined(__AVR_ATmega32M1__) \
412 || defined(__AVR_ATmega32U2__) \
413 || defined(__AVR_ATmega32U4__) \
414 || defined(__AVR_ATmega32U6__) \
415 || defined(__AVR_ATmega406__) \
416 || defined(__AVR_ATmega48__) \
417 || defined(__AVR_ATmega48A__) \
418 || defined(__AVR_ATmega48PA__) \
419 || defined(__AVR_ATmega48P__) \
420 || defined(__AVR_ATmega64__) \
421 || defined(__AVR_ATmega64A__) \
422 || defined(__AVR_ATmega640__) \
423 || defined(__AVR_ATmega644__) \
424 || defined(__AVR_ATmega644A__) \
425 || defined(__AVR_ATmega644P__) \
426 || defined(__AVR_ATmega644PA__) \
427 || defined(__AVR_ATmega645__) \
428 || defined(__AVR_ATmega645A__) \
429 || defined(__AVR_ATmega645P__) \
430 || defined(__AVR_ATmega6450__) \
431 || defined(__AVR_ATmega6450A__) \
432 || defined(__AVR_ATmega6450P__) \
433 || defined(__AVR_ATmega649__) \
434 || defined(__AVR_ATmega649A__) \
435 || defined(__AVR_ATmega6490__) \
436 || defined(__AVR_ATmega6490A__) \
437 || defined(__AVR_ATmega6490P__) \
438 || defined(__AVR_ATmega649P__) \
439 || defined(__AVR_ATmega64C1__) \
440 || defined(__AVR_ATmega64HVE__) \
441 || defined(__AVR_ATmega64M1__) \
442 || defined(__AVR_ATmega64RFA2__) \
443 || defined(__AVR_ATmega64RFR2__) \
444 || defined(__AVR_ATmega8__) \
445 || defined(__AVR_ATmega8515__) \
446 || defined(__AVR_ATmega8535__) \
447 || defined(__AVR_ATmega88__) \
448 || defined(__AVR_ATmega88A__) \
449 || defined(__AVR_ATmega88P__) \
450 || defined(__AVR_ATmega88PA__) \
451 || defined(__AVR_ATmega8HVA__) \
452 || defined(__AVR_ATmega8U2__)
453 
454 
455  #define SLEEP_MODE_IDLE (0)
456  #define SLEEP_MODE_ADC _BV(SM0)
457  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
458  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
459  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
460  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
461 
462 
463  #define set_sleep_mode(mode) \
464  do { \
465  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
466  } while(0)
467 
468 #elif defined(__AVR_ATmega8A__)
469 
470  #define SLEEP_MODE_IDLE (0)
471  #define SLEEP_MODE_ADC _BV(SM0)
472  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
473  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
474  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
475 
476 
477  #define set_sleep_mode(mode) \
478  do { \
479  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
480  } while(0)
481 
482 #elif defined(__AVR_ATMXT112SL__) \
483 || defined(__AVR_ATMXT224__) \
484 || defined(__AVR_ATMXT224E__) \
485 || defined(__AVR_ATMXT336S__) \
486 || defined(__AVR_ATMXT540S__) \
487 || defined(__AVR_ATMXT540SREVA__) \
488 || defined(__AVR_ATxmega16A4__) \
489 || defined(__AVR_ATxmega16A4U__) \
490 || defined(__AVR_ATxmega16C4__) \
491 || defined(__AVR_ATxmega16D4__) \
492 || defined(__AVR_ATxmega32A4__) \
493 || defined(__AVR_ATxmega32A4U__) \
494 || defined(__AVR_ATxmega32C4__) \
495 || defined(__AVR_ATxmega32D4__) \
496 || defined(__AVR_ATxmega32E5__) \
497 || defined(__AVR_ATxmega64A1__) \
498 || defined(__AVR_ATxmega64A1U__) \
499 || defined(__AVR_ATxmega64A3__) \
500 || defined(__AVR_ATxmega64A3U__) \
501 || defined(__AVR_ATxmega64A4U__) \
502 || defined(__AVR_ATxmega64B1__) \
503 || defined(__AVR_ATxmega64B3__) \
504 || defined(__AVR_ATxmega64C3__) \
505 || defined(__AVR_ATxmega64D3__) \
506 || defined(__AVR_ATxmega64D4__) \
507 || defined(__AVR_ATxmega128A1__) \
508 || defined(__AVR_ATxmega128A1U__) \
509 || defined(__AVR_ATxmega128A3__) \
510 || defined(__AVR_ATxmega128A3U__) \
511 || defined(__AVR_ATxmega128A4U__) \
512 || defined(__AVR_ATxmega128B1__) \
513 || defined(__AVR_ATxmega128B3__) \
514 || defined(__AVR_ATxmega128C3__) \
515 || defined(__AVR_ATxmega128D3__) \
516 || defined(__AVR_ATxmega128D4__) \
517 || defined(__AVR_ATxmega192A3__) \
518 || defined(__AVR_ATxmega192A3U__) \
519 || defined(__AVR_ATxmega192C3__) \
520 || defined(__AVR_ATxmega192D3__) \
521 || defined(__AVR_ATxmega256A3__) \
522 || defined(__AVR_ATxmega256A3U__) \
523 || defined(__AVR_ATxmega256C3__) \
524 || defined(__AVR_ATxmega256D3__) \
525 || defined(__AVR_ATxmega256A3B__) \
526 || defined(__AVR_ATxmega256A3BU__) \
527 || defined(__AVR_ATxmega384C3__) \
528 || defined(__AVR_ATxmega384D3__)
529 
530  #define SLEEP_MODE_IDLE (0)
531  #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
532  #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
533  #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
534  #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
535 
536  #define set_sleep_mode(mode) \
537  do { \
538  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
539  } while(0)
540 
541 #elif defined(__AVR_ATxmega32X1__)
542  #define SLEEP_MODE_IDLE (0)
543  #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE0_bm)
544  #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
545  #define SLEEP_MODE_PWR_OFF (SLEEP_SMODE0_bm | SLEEP_SMODE1_bm)
546 
547  #define set_sleep_mode(mode) \
548  do { \
549  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
550  } while(0)
551 
552 #elif defined(__AVR_AT90SCR100__)
553 
554  #define SLEEP_MODE_IDLE (0)
555  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
556  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
557  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
558  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
559 
560  #define set_sleep_mode(mode) \
561  do { \
562  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
563  } while(0)
564 
565 #elif defined(__AVR_ATA6285__) \
566 || defined(__AVR_ATA6286__) \
567 || defined(__AVR_ATA6289__)
568 
569  #define SLEEP_MODE_IDLE (0)
570  #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
571  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
572 
573  #define set_sleep_mode(mode) \
574  do { \
575  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
576  } while(0)
577 
578 #elif defined (__AVR_ATA5790__) \
579 || defined (__AVR_ATA5790N__) \
580 || defined (__AVR_ATA5795__) \
581 || defined (__AVR_ATA5831__)
582 
583  #define SLEEP_MODE_IDLE (0)
584  #define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
585  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
586  #define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
587 
588  #define set_sleep_mode(mode) \
589  do { \
590  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
591  } while(0)
592 
593 #elif defined(__AVR_ATtiny4__) \
594 || defined(__AVR_ATtiny5__) \
595 || defined(__AVR_ATtiny9__) \
596 || defined(__AVR_ATtiny10__) \
597 || defined(__AVR_ATtiny20__) \
598 || defined(__AVR_ATtiny40__)
599 
600  #define SLEEP_MODE_IDLE 0
601  #define SLEEP_MODE_ADC _BV(SM0)
602  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
603  #define SLEEP_MODE_STANDBY _BV(SM2)
604 
605  #define set_sleep_mode(mode) \
606  do { \
607  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
608  } while(0)
609 
610 #else
611 
612  #error "No SLEEP mode defined for this device."
613 
614 #endif
615 
616 
617 
618 /** \ingroup avr_sleep
619 
620  Put the device in sleep mode. How the device is brought out of sleep mode
621  depends on the specific mode selected with the set_sleep_mode() function.
622  See the data sheet for your device for more details. */
623 
624 
625 #if defined(__DOXYGEN__)
626 
627 /** \ingroup avr_sleep
628 
629  Set the SE (sleep enable) bit.
630 */
631 extern void sleep_enable (void);
632 
633 #else
634 
635 #define sleep_enable() \
636 do { \
637  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
638 } while(0)
639 
640 #endif
641 
642 
643 #if defined(__DOXYGEN__)
644 
645 /** \ingroup avr_sleep
646 
647  Clear the SE (sleep enable) bit.
648 */
649 extern void sleep_disable (void);
650 
651 #else
652 
653 #define sleep_disable() \
654 do { \
655  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
656 } while(0)
657 
658 #endif
659 
660 
661 /** \ingroup avr_sleep
662 
663  Put the device into sleep mode. The SE bit must be set
664  beforehand, and it is recommended to clear it afterwards.
665 */
666 #if defined(__DOXYGEN__)
667 
668 extern void sleep_cpu (void);
669 
670 #else
671 
672 #define sleep_cpu() \
673 do { \
674  __asm__ __volatile__ ( "sleep" "\n\t" :: ); \
675 } while(0)
676 
677 #endif
678 
679 
680 #if defined(__DOXYGEN__)
681 
682 extern void sleep_mode (void);
683 
684 #else
685 
686 #define sleep_mode() \
687 do { \
688  sleep_enable(); \
689  sleep_cpu(); \
690  sleep_disable(); \
691 } while (0)
692 
693 #endif
694 
695 
696 #if defined(__DOXYGEN__)
697 
698 extern void sleep_bod_disable (void);
699 
700 #else
701 
702 #if defined(BODS) && defined(BODSE)
703 
704 #define sleep_bod_disable() \
705 do { \
706  uint8_t tempreg; \
707  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
708  "ori %[tempreg], %[bods_bodse]" "\n\t" \
709  "out %[mcucr], %[tempreg]" "\n\t" \
710  "andi %[tempreg], %[not_bodse]" "\n\t" \
711  "out %[mcucr], %[tempreg]" \
712  : [tempreg] "=&d" (tempreg) \
713  : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
714  [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
715  [not_bodse] "i" (~_BV(BODSE))); \
716 } while (0)
717 
718 #endif
719 
720 #endif
721 
722 
723 /*@}*/
724 
725 #endif /* _AVR_SLEEP_H_ */

Automatically generated by Doxygen 1.8.1.1 on Fri Aug 17 2012.