#define OFFSET_x86_EAX 8
#define OFFSET_x86_EBX 20
#define OFFSET_x86_ECX 12
#define OFFSET_x86_EDX 16
#define OFFSET_x86_ESI 32
#define OFFSET_x86_EDI 36
#define OFFSET_x86_EBP 28
#define OFFSET_x86_ESP 24
#define OFFSET_x86_EIP 68
#define OFFSET_x86_CS 288
#define OFFSET_x86_DS 290
#define OFFSET_x86_ES 292
#define OFFSET_x86_FS 294
#define OFFSET_x86_GS 296
#define OFFSET_x86_SS 298
#define OFFSET_x86_SETC 344
#define OFFSET_amd64_RAX 16
#define OFFSET_amd64_RBX 40
#define OFFSET_amd64_RCX 24
#define OFFSET_amd64_RDX 32
#define OFFSET_amd64_RSI 64
#define OFFSET_amd64_RDI 72
#define OFFSET_amd64_RSP 48
#define OFFSET_amd64_RBP 56
#define OFFSET_amd64_R8 80
#define OFFSET_amd64_R9 88
#define OFFSET_amd64_R10 96
#define OFFSET_amd64_R11 104
#define OFFSET_amd64_R12 112
#define OFFSET_amd64_R13 120
#define OFFSET_amd64_R14 128
#define OFFSET_amd64_R15 136
#define OFFSET_amd64_RIP 184
#define OFFSET_amd64_SETC 868
#define OFFSET_ppc32_GPR0 16
#define OFFSET_ppc32_GPR1 20
#define OFFSET_ppc32_GPR2 24
#define OFFSET_ppc32_GPR3 28
#define OFFSET_ppc32_GPR4 32
#define OFFSET_ppc32_GPR5 36
#define OFFSET_ppc32_GPR6 40
#define OFFSET_ppc32_GPR7 44
#define OFFSET_ppc32_GPR8 48
#define OFFSET_ppc32_GPR9 52
#define OFFSET_ppc32_GPR10 56
#define OFFSET_ppc32_CIA 1168
#define OFFSET_ppc32_CR0_0 1187
#define OFFSET_ppc64_GPR0 16
#define OFFSET_ppc64_GPR1 24
#define OFFSET_ppc64_GPR2 32
#define OFFSET_ppc64_GPR3 40
#define OFFSET_ppc64_GPR4 48
#define OFFSET_ppc64_GPR5 56
#define OFFSET_ppc64_GPR6 64
#define OFFSET_ppc64_GPR7 72
#define OFFSET_ppc64_GPR8 80
#define OFFSET_ppc64_GPR9 88
#define OFFSET_ppc64_GPR10 96
#define OFFSET_ppc64_CIA 1296
#define OFFSET_ppc64_CR0_0 1327
#define OFFSET_arm_R0 8
#define OFFSET_arm_R1 12
#define OFFSET_arm_R2 16
#define OFFSET_arm_R3 20
#define OFFSET_arm_R4 24
#define OFFSET_arm_R5 28
#define OFFSET_arm_R7 36
#define OFFSET_arm_R13 60
#define OFFSET_arm_R14 64
#define OFFSET_arm_R15T 68
#define OFFSET_arm64_X0 16
#define OFFSET_arm64_X1 24
#define OFFSET_arm64_X2 32
#define OFFSET_arm64_X3 40
#define OFFSET_arm64_X4 48
#define OFFSET_arm64_X5 56
#define OFFSET_arm64_X6 64
#define OFFSET_arm64_X7 72
#define OFFSET_arm64_X8 80
#define OFFSET_arm64_XSP 264
#define OFFSET_arm64_PC 272
#define OFFSET_arm64_SETC 936
#define OFFSET_s390x_r2 592
#define OFFSET_s390x_r3 600
#define OFFSET_s390x_r4 608
#define OFFSET_s390x_r5 616
#define OFFSET_s390x_r6 624
#define OFFSET_s390x_r7 632
#define OFFSET_s390x_r15 696
#define OFFSET_s390x_IA 720
#define OFFSET_s390x_SYSNO 728
#define OFFSET_s390x_IP_AT_SYSCALL 792
#define OFFSET_s390x_fpc 712
#define OFFSET_s390x_CC_OP 736
#define OFFSET_s390x_CC_DEP1 744
#define OFFSET_s390x_CC_DEP2 752
#define OFFSET_s390x_CC_NDEP 760
#define OFFSET_mips32_r0 8
#define OFFSET_mips32_r1 12
#define OFFSET_mips32_r2 16
#define OFFSET_mips32_r3 20
#define OFFSET_mips32_r4 24
#define OFFSET_mips32_r5 28
#define OFFSET_mips32_r6 32
#define OFFSET_mips32_r7 36
#define OFFSET_mips32_r8 40
#define OFFSET_mips32_r9 44
#define OFFSET_mips32_r10 48
#define OFFSET_mips32_r11 52
#define OFFSET_mips32_r12 56
#define OFFSET_mips32_r13 60
#define OFFSET_mips32_r14 64
#define OFFSET_mips32_r15 68
#define OFFSET_mips32_r15 68
#define OFFSET_mips32_r17 76
#define OFFSET_mips32_r18 80
#define OFFSET_mips32_r19 84
#define OFFSET_mips32_r20 88
#define OFFSET_mips32_r21 92
#define OFFSET_mips32_r22 96
#define OFFSET_mips32_r23 100
#define OFFSET_mips32_r24 104
#define OFFSET_mips32_r25 108
#define OFFSET_mips32_r26 112
#define OFFSET_mips32_r27 116
#define OFFSET_mips32_r28 120
#define OFFSET_mips32_r29 124
#define OFFSET_mips32_r30 128
#define OFFSET_mips32_r31 132
#define OFFSET_mips32_PC 136
#define OFFSET_mips32_HI 140
#define OFFSET_mips32_LO 144
#define OFFSET_mips64_r0 16
#define OFFSET_mips64_r1 24
#define OFFSET_mips64_r2 32
#define OFFSET_mips64_r3 40
#define OFFSET_mips64_r4 48
#define OFFSET_mips64_r5 56
#define OFFSET_mips64_r6 64
#define OFFSET_mips64_r7 72
#define OFFSET_mips64_r8 80
#define OFFSET_mips64_r9 88
#define OFFSET_mips64_r10 96
#define OFFSET_mips64_r11 104
#define OFFSET_mips64_r12 112
#define OFFSET_mips64_r13 120
#define OFFSET_mips64_r14 128
#define OFFSET_mips64_r15 136
#define OFFSET_mips64_r15 136
#define OFFSET_mips64_r17 152
#define OFFSET_mips64_r18 160
#define OFFSET_mips64_r19 168
#define OFFSET_mips64_r20 176
#define OFFSET_mips64_r21 184
#define OFFSET_mips64_r22 192
#define OFFSET_mips64_r23 200
#define OFFSET_mips64_r24 208
#define OFFSET_mips64_r25 216
#define OFFSET_mips64_r26 224
#define OFFSET_mips64_r27 232
#define OFFSET_mips64_r28 240
#define OFFSET_mips64_r29 248
#define OFFSET_mips64_r30 256
#define OFFSET_mips64_r31 264
#define OFFSET_mips64_PC 272
#define OFFSET_mips64_HI 280
#define OFFSET_mips64_LO 288
#define OFFSET_loongarch64_R0 16
#define OFFSET_loongarch64_R1 24
#define OFFSET_loongarch64_R2 32
#define OFFSET_loongarch64_R3 40
#define OFFSET_loongarch64_R4 48
#define OFFSET_loongarch64_R5 56
#define OFFSET_loongarch64_R6 64
#define OFFSET_loongarch64_R7 72
#define OFFSET_loongarch64_R8 80
#define OFFSET_loongarch64_R9 88
#define OFFSET_loongarch64_R10 96
#define OFFSET_loongarch64_R11 104
#define OFFSET_loongarch64_R12 112
#define OFFSET_loongarch64_R13 120
#define OFFSET_loongarch64_R14 128
#define OFFSET_loongarch64_R15 136
#define OFFSET_loongarch64_R16 144
#define OFFSET_loongarch64_R17 152
#define OFFSET_loongarch64_R18 160
#define OFFSET_loongarch64_R19 168
#define OFFSET_loongarch64_R20 176
#define OFFSET_loongarch64_R21 184
#define OFFSET_loongarch64_R22 192
#define OFFSET_loongarch64_R23 200
#define OFFSET_loongarch64_R24 208
#define OFFSET_loongarch64_R25 216
#define OFFSET_loongarch64_R26 224
#define OFFSET_loongarch64_R27 232
#define OFFSET_loongarch64_R28 240
#define OFFSET_loongarch64_R29 248
#define OFFSET_loongarch64_R30 256
#define OFFSET_loongarch64_R31 264
#define OFFSET_loongarch64_PC 272
